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Fully-Differential Amplifier (FDA) Design for ADC Interfaces

Fully-Differential Amplifier (FDA) Design for ADC Interfaces

← Back to:Operational Amplifiers (Op Amps)

A Fully-Differential Amplifier is the most reliable way to drive differential signal chains and ADC inputs because it sets both the differential signal and the output common-mode (VOCM) intentionally. This page shows how to keep THD, settling, and stability under control in real AA/Cin loads by budgeting headroom, enforcing symmetry, and validating at the ADC handoff node.

What this page solves (FDA scope + when to use)

A Fully-Differential Amplifier (FDA) is a signal-chain building block that produces a differential output pair and uses VOCM to lock the output common-mode to a defined target (often an ADC’s VCM/REF node). This page focuses on FDA usage as a common-mode-controlled differential driver for ADC/AFE interfaces—not as a general-purpose op amp.

Three-sentence definition

  • Differential outputs: generates VOUT+ and VOUT− as a matched pair for a differential load or differential ADC input.
  • VOCM control: forces the output common-mode to a chosen reference, keeping headroom and linearity predictable on single-supply rails.
  • Interface-centric: turns “ADC range + CM target + load + stability” into a controlled, verifiable design instead of a trial-and-error hookup.

You need an FDA if…

  • The next stage is differential (differential-input ADC, differential cable/line, or a differential AFE), and a clean VOUT+/VOUT− pair is required.
  • The output common-mode must be defined (common in single-supply systems) so the signal sits correctly inside the ADC input range across temperature and load.
  • Even-order spurs / CM sensitivity must be controlled, and the layout + network can maintain good symmetry so differential benefits are preserved.

Do not use an FDA if…

  • The whole chain is single-ended and the next stage does not need differential drive; a standard op amp buffer/filter stage is often simpler.
  • Common-mode is already created downstream (for example, the next block defines its own VCM and does not rely on an external driver’s CM behavior).
  • A passive transformer/balun or dedicated interface block is clearly better for isolation or line drive; FDA is not the only way to create a differential signal.

Mini decision flow (3 steps)

  1. Is the next stage differential? If yes, proceed; if no, prefer a single-ended op amp solution.
  2. Is a defined output common-mode required? If yes (most single-supply ADC chains), VOCM control becomes a primary selection driver.
  3. Are stability/settling/THD constraints tight at the target bandwidth? If yes, plan isolation-R + AAF interface and verify with step response + SFDR tests.

Engineering hook: common “wrong block” signatures

  • Output CM drifts with load/temperature → ADC codes shift, even-order spurs rise.
  • Ringing/oscillation appears only after connecting AAF/ADC input → loop margin is being eaten by capacitive loading.
  • SFDR degrades unexpectedly after “simple differential hookup” → symmetry, VOCM noise, or load interaction is dominating.
FDA in the signal chain: Source to ADC with VOCM common-mode target Block diagram showing Sensor/Source feeding an FDA, then an anti-alias network, then a differential-input ADC. VOCM from the ADC sets the output common-mode target. Sensor / Source FDA VOUT+ / VOUT− AA network ADC diff input VOCM from ADC VCM/REF CM target VOUT+ VOUT−

FDA vs Op Amp vs ADC Driver: choose the right building block

FDA is not “a regular op amp with two outputs.” It is a differential driver with an explicit common-mode control input (VOCM). “ADC driver” describes the job (meet range, CM, settling, noise, and SFDR at the ADC pins); FDA is a common implementation when the ADC expects a differential input and a defined common-mode target.

Quick comparison (engineering dimensions)

Dimension Op Amp (single-ended) FDA Other driver solutions
Output format Single output node Matched VOUT+ / VOUT− pair Transformer/balun, dedicated drivers, discrete stages
Common-mode control Implicit (depends on biasing) Explicit VOCM sets output CM target May have no CM control or CM is defined elsewhere
Swing & headroom Referenced to ground/rail limits Referenced to VOCM center per output node Depends on topology; may need extra biasing blocks
AA network / ADC Cin interaction Often stable only with careful C-load handling Must be planned with isolation-R / damping for loop margin Varies; transformers avoid some C-load issues but add others
Best fit Buffers, filters, simple gain stages Differential ADC/AFE interfaces that require defined CM Isolation/line interfaces, special constraints, or dedicated drivers

Top pitfalls (mistake → symptom → pointer)

Mistake 1: VOCM treated as “optional”

Symptom: output common-mode shifts with load/temperature; ADC codes drift; even-order spurs rise. Pointer: VOCM source impedance/noise, routing, and local decoupling become first-order design items.

Mistake 2: AA network / ADC Cin assumed “light load”

Symptom: ringing/oscillation appears only after connecting the filter/ADC; THD/SFDR collapses near certain frequencies. Pointer: isolation resistors and damping are loop-margin tools, not optional “noise adders.”

Mistake 3: differential symmetry broken in parts or layout

Symptom: differential signal leaks into common-mode; unexpected spurs; channel-to-channel mismatch. Pointer: resistor matching, trace symmetry, and return paths determine whether differential benefits survive.

Choosing between Op Amp, FDA, and other driver solutions Three side-by-side mini diagrams: single-ended op amp, FDA with VOCM and differential outputs, and a transformer/buffer solution feeding a differential ADC input. Op Amp FDA Other solutions Op Amp single output VOUT FDA VOCM controlled VOUT+ VOUT− VOCM Transformer / Buffer diff Best for simple single-ended chains Best when ADC/line needs CM-controlled diff Best for isolation or special constraints

Internal architecture: differential signal path + common-mode control loop

A fully-differential amplifier behaves like two control loops running at the same time. The differential loop sets gain, bandwidth, distortion, and settling for the signal that the ADC actually converts. The common-mode (CM) loop forces the output center line to match VOCM, keeping headroom predictable and preventing CM drift from turning into spurs.

Two loops, two responsibilities

Differential loop (signal loop)

  • Sets closed-loop gain via the differential feedback network.
  • Defines bandwidth and phase margin for the differential signal path.
  • Dominates THD/SFDR when the load is symmetric and the driver is not near output limits.
  • Controls settling to the ADC pins (especially with RC networks and input capacitance present).

Common-mode loop (center-line loop)

  • Forces output CM so that (VOUT+ + VOUT−)/2 tracks VOCM.
  • Preserves headroom on single-supply rails by anchoring the output center line.
  • Stabilizes CM behavior against load/temperature changes that would otherwise shift the center line.
  • Limits CM-to-diff leakage when symmetry is good; when symmetry is poor, CM movement can convert into spurs.

Engineering conclusion

Adjusting VOCM does not set gain. VOCM sets the output center line (common-mode target) and therefore the available headroom and operating point. Closed-loop gain is set by the differential feedback network and the differential loop margin.

Quick diagnostics (what symptoms usually mean)

  • Output CM moves with load/temperature: VOCM source impedance/noise or CM-loop return path is dominating.
  • Ringing appears only after connecting RC/ADC input: capacitive loading is eating loop margin (often differential loop margin).
  • Even-order spurs rise while differential gain is “correct”: symmetry is broken and CM activity is converting into differential error.

Verification hook (simple measurements)

  • Measure output common-mode: compute (VOUT+ + VOUT−)/2 and confirm it tracks VOCM under load and across frequency.
  • Step response with the real load: check differential settling and CM movement at the ADC pins (not only at the amplifier package).
FDA dual-loop model: differential loop and common-mode loop with VOCM Block diagram showing an FDA with differential inputs and outputs, a differential feedback path, a common-mode sense node feeding a CM error amplifier, and VOCM as the target input to the CM loop. Input SE / Diff FDA core Diff loop CM loop Load / AA / ADC VOUT+ VOUT− Differential feedback CM sense VOCM CM target Two loops run simultaneously: Diff loop sets gain/linearity; CM loop sets center line.

VOCM & reference interfacing: where does the common-mode target come from?

VOCM is not a “bias convenience.” It is a signal-quality node. Any impedance, noise, or coupling on VOCM is translated into output common-mode movement by the CM loop, and part of that common-mode can appear as measurable error at the ADC pins when symmetry or CMRR is finite.

Common VOCM sources (pick the one that matches the system boundary)

1) ADC VCM pin

  • Best match for ADC input range and intended CM operating point.
  • Watch drive strength: the pin may not be designed to feed multiple channels without buffering.

2) Mid-rail (VDD/2)

  • Easy to generate in single-supply systems.
  • Risk: supply noise becomes CM noise unless the node is buffered, filtered, and routed as an analog reference.

3) External reference buffer

  • Best control of impedance, noise, and distribution for multi-channel designs.
  • Enables isolation so one channel’s CM dynamics does not disturb the others.

Connection checklist (Do / Don’t)

  • Do treat VOCM like a reference: short routing, quiet return, and local decoupling near each FDA VOCM pin.
  • Do use per-channel isolation (small series resistor) when one VOCM node feeds multiple FDA channels.
  • Do keep VOCM away from fast digital edges; avoid sharing return paths with switching currents.
  • Don’t leave VOCM floating or “assumed internally biased” unless the device explicitly supports that mode.
  • Don’t directly parallel multiple VOCM pins on a weak source without a buffer or isolation; cross-channel CM coupling is common.

Failure signatures (what “wrong VOCM” often looks like)

  • CM drift: (VOUT+ + VOUT−)/2 moves when load changes or temperature shifts.
  • Noise floor lift: wideband noise rises after connecting the VOCM network or routing it across the board.
  • Even-order spurs: second-harmonic components increase when CM is not stable or symmetry is weak.
  • Channel coupling: activity on one channel changes the CM behavior of other channels sharing VOCM.
  • Power-up pop: large output transients during enable/boot because VOCM is not settled when the CM loop engages.

Verification hook (quick checks)

  • Correlation check: measure VOCM noise and output CM noise; strong correlation indicates VOCM quality is limiting.
  • Multi-channel isolation check: disturb one channel’s load and confirm other channels’ CM does not move.
VOCM source and distribution to multiple FDA channels Block diagram showing a VOCM source feeding a distribution node, then per-channel isolation resistors and local decoupling capacitors near each FDA VOCM pin. Three FDA channels are shown. VOCM source ADC VCM / REF Distribution node FDA 1 FDA 2 FDA 3 VOCM VOCM VOCM Riso Riso Riso Cdecap Cdecap Cdecap quiet AGND return Per-channel isolation + local decoupling reduces cross-channel CM coupling.

Input/output range & headroom budgeting (single-supply & dual-supply)

Most “mystery distortion” in FDA-to-ADC designs comes from an incomplete range budget: the differential amplitude is chosen correctly, but one output node runs out of headroom under the real load, or recovery becomes slow after a large transient. This section turns swing, common-mode, load, and frequency into a small checklist that can be verified with a scope at the ADC pins.

Budget checklist (5 values that must be known)

  • VCM target: typically VOCM (ADC VCM/REF or a buffered mid-rail).
  • VDIFF target: ADC full-scale or the required differential amplitude at the ADC pins.
  • Load: effective R and CIN,total (ADC input capacitance + AA capacitors + parasitics).
  • Frequency / bandwidth: highest input frequency and settling bandwidth that must remain linear.
  • Supply rails: single-supply or dual-supply, including output headroom to each rail under load.

VDIFF ↔ per-node swing (the conversion that prevents clipping surprises)

  • Symmetric differential output: each node swings about VOCM by approximately ±(VDIFF,peak/2).
  • Node limits: VOUT+ and VOUT− must both stay inside the device’s output swing vs load limits, not only DC swing specs.
  • Peak vs p-p: ensure VDIFF units are consistent (peak and p-p mix-ups are a common budgeting failure).

Dynamic headroom (why “DC swing looks fine” can still fail)

  • Output swing shrinks with frequency because the output stage must supply more dynamic current into CIN,total.
  • Heavier effective loads (smaller R, larger C) reduce available swing and can push the driver into non-linear regions earlier.
  • AA/ADC capacitance is a current demand: large C at the ADC pins increases instantaneous output current and can degrade THD and settling.

Overload recovery (when the output “sticks” or returns slowly)

  • Rail / current limiting: if either output node hits a limit, differential linearity collapses and recovery can take many cycles.
  • Input CM range violation: front-end stages can enter a non-linear state even if the differential math looks correct.
  • VOCM disturbed: a weak or noisy VOCM node forces the CM loop to fight, extending recovery tails.
  • Large capacitive charge/discharge: AA/ADC capacitance stores energy; recovery may be limited by output current and loop behavior.

Mini example (from ADC full-scale to per-node swing)

  1. Take the ADC requirement as VDIFF at the ADC pins (confirm whether it is peak or p-p).
  2. Compute each node’s required swing around VOCM as approximately ±(VDIFF,peak/2).
  3. Validate headroom using output swing vs load & frequency limits and confirm the output stage can drive CIN,total without slow recovery.

Verification hook (what to measure early)

  • At the ADC pins, measure VOUT+, VOUT−, and compute output CM: (VOUT+ + VOUT−)/2; confirm it stays close to VOCM.
  • Run a large-signal step and confirm settling and recovery are fast enough for the ADC acquisition window.
Differential swing and headroom around VOCM Diagram showing VOCM center line, VOUT+ and VOUT- swing bands, top and bottom headroom to rails, and differential amplitude relation between the two outputs. Top rail Bottom rail VOCM (Vcm target) Top headroom Bottom headroom VOUT+ VOUT− VDIFF Clipping risk Validate swing using output limits vs load/frequency, not only DC specs.

Stability with AAF / capacitive loads: isolation R, snubbers, and loop margins

The hardest part of an FDA interface is not the nominal gain—it is the interaction with the anti-alias network and the ADC’s input capacitance. Capacitive loading shifts poles/zeros seen by the loop, reducing phase margin and causing ringing, oscillation, noise “bumps,” or sudden THD/SFDR degradation. The goal is a repeatable, testable stability workflow.

Why AAF + ADC Cin can collapse phase margin

  • CIN,total (ADC Cin + filter capacitors + parasitics) makes the load strongly frequency-dependent.
  • The output stage must supply dynamic current into CIN,total, shifting the effective loop response and reducing damping.
  • If the network is not symmetric, differential-to-common-mode conversion increases and can amplify spurs and THD.

Stabilization tools (mechanism → tradeoff)

Isolation resistors (Riso)

Adds damping and isolates CIN,total from the output stage. Tradeoff: thermal noise, small gain error, and potentially slower settling if oversized.

Output series R (per side, symmetric)

Prevents one node from seeing a “hard” capacitive edge first; improves symmetry. Tradeoff: similar to Riso; may change filter corner and impedance.

RC snubber (HF damping)

Targets high-frequency ringing and reduces Q of the output/load resonance. Tradeoff: extra load and power; can reduce bandwidth if too aggressive.

Capacitance placement & symmetry

Keeps parasitic imbalance small and avoids unintended CM paths. Tradeoff: tighter layout constraints; requires deliberate return-path control.

Symmetry rule (non-negotiable for SFDR/CMRR)

Riso, filter elements, trace lengths, and return paths should be matched on both outputs. Asymmetry converts differential energy into common-mode movement and back into differential spurs at the ADC input.

Symptom → likely cause → first fix

Symptom Likely cause First fix
Sustained oscillation CIN,total directly loads the outputs; margin collapse Add symmetric Riso; reduce exposed capacitance at the output node
Ringing only after connecting ADC/filter Load resonance with filter capacitors and parasitics Increase damping (Riso) or add a small RC snubber
Noise “bump” / step in spectrum Lightly damped pole/zero interaction; HF peaking Add snubber or adjust Riso for lower Q
THD suddenly degrades near certain frequencies Margin reduction under dynamic current; asymmetry converts CM activity Enforce symmetry; tune damping; verify at ADC pins
VOUT+ and VOUT− look different Component/trace mismatch; CM paths differ Match R/C values and placement; correct return paths

MVP stability workflow (start conservative, then optimize)

  1. Model the real load: include CIN,total (ADC Cin + AA caps + parasitics) from the start.
  2. Add symmetric Riso first: stabilize before optimizing noise or bandwidth.
  3. Validate with step response at the ADC pins: confirm damping and fast settling.
  4. Add an RC snubber only if needed: tune one parameter at a time to reduce ringing Q.
  5. Reduce damping carefully: decrease Riso only after stability is proven across frequency and temperature.
FDA stability with AAF and ADC capacitive input Block diagram showing FDA outputs with symmetric isolation resistors, an anti-alias network, ADC input capacitance, optional differential and common-mode capacitors, parasitics, and loop margin risk arrows. FDA outputs VOUT+ VOUT− Riso Riso AA network Cdiff Ccm ADC diff input Cin parasitics loop margin risk path Keep both sides symmetric; tune damping first (Riso), then optimize.

Settling, distortion & noise budgeting (what limits SFDR/ENOB in practice)

SFDR and ENOB are limited by the weakest link at the sampling instant: residual settling error, non-linear distortion under the real load, and integrated noise across the effective bandwidth. A single datasheet plot rarely captures the interaction between output drive, common-mode control, and the AAF/ADC input network.

Distortion sources (what usually dominates in practice)

Output-stage limits (current / slew / headroom)

  • Most sensitive to high frequency + large amplitude + large CIN,total.
  • Shows up as sudden THD rise or node-by-node asymmetry near headroom limits.
  • First check: VOUT+/VOUT− symmetry and proximity to rails at the ADC pins.

Common-mode loop non-linearity (CM-to-diff conversion)

  • Driven by VOCM quality and asymmetry in output networks and layout.
  • Often increases even-order components when CM motion leaks into differential error.
  • First check: track (VOUT+ + VOUT−)/2 versus spur behavior.

Load-induced intermodulation (AAF/Cin dynamics)

  • Lightly-damped networks create peaking, ringing, and IMD sensitivity.
  • Appears as noise bumps, frequency-specific THD cliffs, or two-tone IMD worsening.
  • First check: step-response Q and sensitivity to small changes in Riso/snubber.

Noise budgeting (where noise enters and why it grows)

  • en / in vs source impedance: high source-Z can make current noise dominate; low source-Z can make voltage noise dominate.
  • Bandwidth integration: noise is an area under the curve; peaking and excess bandwidth raise integrated noise.
  • VOCM injection: VOCM noise becomes output CM noise; finite symmetry/CMRR can convert it into differential error.

Settling (small-signal vs large-signal, and why the sampling instant matters)

  • Small-signal settling is loop/phase-margin dominated (ringing and long tails).
  • Large-signal settling is output-stage dominated (slew, current limit, or overload recovery tails).
  • Residual settling error at the ADC pins directly becomes amplitude/phase error at the sampling instant.

Budget table (structure only)

Bucket Represents Where it enters How to validate
Source noise Sensor/driver noise and impedance-related noise Input node before the FDA Short input or replace source; compare integrated noise
FDA noise Amplifier input/output noise shaped by gain and bandwidth Differential path through the amplifier Measure noise vs gain/bandwidth changes; check peaking
VOCM noise Common-mode target noise injected by the CM loop VOCM node → output CM → ADC input Correlate VOCM noise with output CM and spurs
ADC noise Quantization + internal noise floors + sampling effects ADC itself at the sampling instant Measure with known low-noise driver; compare to datasheet floor

Rule-based decisions (3 if-then)

  • If high-frequency, high-amplitude spurs are the concern and CIN,total is significant, then prioritize low distortion with strong output drive and stable damping (Riso/snubber).
  • If acquisition windows are short and settling error dominates, then prioritize fast large-signal settling and overload recovery, and isolate CIN,total from the output node.
  • If source impedance is high or noise margin is tight, then prioritize noise matching (en/in vs source-Z), control peaking/bandwidth, and protect VOCM from becoming a noise injector.

Verification hook (fast tests that close the loop)

  • Step test at ADC pins: compare small-signal vs large-signal steps; look for ringing and recovery tails.
  • Two-tone IMD check: identify load-induced intermodulation and sensitivity to damping changes.
  • VOCM correlation: measure VOCM noise and output CM noise; check for correlation with spur behavior.
Signal chain with error budget bars Left side shows Source, FDA, AA network, and ADC blocks. Right side shows four horizontal bars labeled Source, FDA, VOCM, and ADC to represent error contributions. Minimal labels only. Source FDA AA ADC settling dist VOCM Error budget Source FDA VOCM ADC Budget and validate at the ADC pins: distortion + integrated noise + residual settling.

Practical interface patterns: single-ended to differential, fully differential, and gain setting

These patterns are meant to be copied into real designs. Each card lists when to use the topology, the typical failure modes, and the first debug checks. Filter synthesis is intentionally out of scope; only the interface boundary to the AA network is covered.

Topology 1: Single-ended → Differential (SE2Diff)

Use when: the source is single-ended but the ADC expects a differential input range with a defined common-mode target.

  • Risk: missing bias/return paths or asymmetry increases even-order spurs.
  • Risk: weak VOCM distribution allows output CM to drift or inject noise.
  • Debug: confirm VOUT+/VOUT− symmetry and output CM tracking VOCM at the ADC pins.

Topology 2: Differential → Differential (buffer or fixed gain)

Use when: the upstream signal is already differential and needs buffering, range matching, or stronger drive into AA/ADC.

  • Risk: stability sensitivity rises with CIN,total and AA networks.
  • Risk: CM alignment between input and VOCM can be mishandled, reducing headroom.
  • Debug: validate stability with and without the AA/ADC load; confirm CM stays centered.

Topology 3: Differential gain / attenuation (Rg/Rf network)

Use when: the amplitude must be mapped to ADC full-scale (gain) or protected with attenuation while keeping symmetry.

  • Risk: resistor mismatch/thermal drift becomes channel-to-channel error and spur growth.
  • Risk: layout parasitics differ between sides, converting diff/CM and breaking SFDR.
  • Debug: inspect symmetry, then compare small- vs large-signal steps at the ADC pins.

Gain network checklist (what matters more than the formula)

  • Match Rg/Rf pairs and keep them thermally coupled for drift tracking.
  • Keep both sides symmetric in component placement, routing length, and return paths.
  • Control parasitics: avoid one output node seeing extra capacitance first.
  • Use VOCM as a reference node: local decoupling and isolation if shared across channels.
  • Stabilize first (Riso/snubber), then optimize noise and gain accuracy.

AA interface rules (no filter synthesis)

  • Place the AA network close to the ADC; keep output traces short and matched.
  • Use symmetric Riso between FDA outputs and the AA network as a default stability handle.
  • If Cdiff/Ccm are used, keep values and placement symmetric and control the return path.
  • Validate response at the ADC pins, not only at the amplifier package.
Three FDA interface topologies Three columns showing SE-to-diff, diff-to-diff, and differential gain/attenuation topologies with key labels: Rg/Rf, VOCM, Riso, AA network, and ADC. SE2Diff Diff → Diff Gain / Atten SE FDA VOCM Riso AA ADC Diff FDA VOCM Riso AA ADC Diff FDA Rg/Rf VOCM Riso AA ADC Copy patterns, keep symmetry, and validate at the ADC pins.

Layout, grounding & EMI: symmetry, return paths, and common-mode leakage

FDA performance is often limited by the PCB, not the datasheet. The most reliable way to protect SFDR/ENOB is to enforce symmetry, keep return paths continuous, and prevent common-mode motion from leaking into the differential path at the ADC pins.

Symmetry means “both sides see the same world”

  • Geometry: matched length, layer changes, and via count for both sides.
  • Impedance: consistent reference plane and spacing to keep diff behavior predictable.
  • Parasitics: avoid one side running near plane splits, copper voids, or noisy traces.
  • Load symmetry: Riso and AA parts placed as a mirrored pair with identical return paths.

Layout checklist (prioritized, ≤10)

  1. Keep diff routing continuous: do not cross plane splits; keep a solid reference under both traces.
  2. Mirror the AA interface: Riso + AA components must be value-matched and physically symmetric.
  3. Define three return paths: output return, supply decap return, and VOCM decap return must stay short and clean.
  4. Place supply decaps at pins: minimize loop area from pin → cap → return plane.
  5. Place VOCM decap locally: VOCM is a reference node; keep its return away from noisy digital currents.
  6. Control via transitions: if one side changes layer, the other side must change similarly (paired vias).
  7. Protect sensitive nodes: input, feedback, and VOCM traces must be short and shielded by a stable reference.
  8. Prevent CM pickup: avoid asymmetrical nearby aggressors (clocks, fast edges, switching nodes).
  9. Maintain plane continuity: no narrow neck-downs under diff paths; avoid long return detours.
  10. Verify at ADC pins: place test pads or coax points where the ADC actually sees the signal.

Do not do (3 high-impact mistakes)

  • Do not route across plane splits: diff pairs over discontinuities force return detours and create CM leakage.
  • Do not make one side “see” extra capacitance first: asymmetric AA/Cin loads convert diff energy into CM motion.
  • Do not run VOCM long and noisy: shared VOCM without local decoupling/isolation injects coherent CM noise.
PCB top-view layout concept for an FDA driving an AA network and ADC Simplified top-down PCB diagram showing connector/source, FDA, AA network, and ADC. Differential pairs are drawn symmetrically. Three return path arrows are indicated: output return, supply decap return, and VOCM decap return. Plane split is shown as a dashed line to avoid crossing. Plane split (do not cross) Source FDA AA ADC Riso Decap VOCM VOCM decap Output return Supply decap return VOCM return (keep clean) Output return Supply return VOCM return

Verification & debug: what to measure and how to interpret results

A useful verification flow proves stability, settling, noise, distortion, and common-mode behavior at the ADC pins under the real load. Measurements are only actionable when the test chain (source, fixture, probing, and load) is treated as part of the system.

Must-measure items (minimum set)

  • Stability: step response (overshoot, ringing, tails) and sweep for peaking sensitivity.
  • THD/SFDR: sweep amplitude and frequency; look for sudden “cliffs” or even-order growth.
  • Noise: wideband noise (integration trend) and low-frequency behavior (drift / LF noise).
  • CM behavior: output CM tracking VOCM and CM noise correlation with spurs.

Test plan (repeatable steps)

Step Action Pass / fail cue
Step 1 Power-up sanity: verify VOCM level, output CM, and idle stability. No rail pinning, no burst oscillation, CM is centered.
Step 2 Baseline stability with minimal load (or known dummy load). Step response is well damped; no strong peaking.
Step 3 Attach the real AA + ADC input network; repeat stability check at ADC pins. Any new ringing indicates load/Cin sensitivity.
Step 4 Settling: compare small-signal and large-signal steps; observe tails. No long recovery tail; symmetry holds for VOUT+/VOUT−.
Step 5 THD/SFDR: sweep amplitude then frequency; identify “cliffs”. Cliffs typically map to headroom/drive limits or stability margins.
Step 6 Noise: measure wideband and low-frequency behavior; note peaking bumps. Noise bumps correlate with damping/peaking; LF issues correlate with reference nodes.
Step 7 CM correlation: measure output CM and VOCM; check correlation with spurs. Even-order spur growth often tracks CM leakage and VOCM quality.

Interpretation map: symptom → likely cause → re-test action

Symptom Likely cause Re-test / next move
Sustained oscillation Insufficient phase margin, Cin/AA directly loading the outputs Increase symmetric Riso or add snubber; A/B test with load removed
Ringing appears only when ADC is connected ADC input Cin and AA network reduce damping Tune damping (Riso/snubber); confirm mirrored placement and routing
Noise floor bump in a band Peaking from light damping or layout parasitics Sweep Riso/snubber values; confirm return continuity under diff routes
Even-order spur growth CM leakage from asymmetry or VOCM contamination Measure output CM vs VOCM; compare spurs after improving VOCM decoupling
THD cliff with amplitude sweep Headroom/drive limit (slew, current, or output swing) Check node clipping and symmetry at ADC pins; repeat with lighter load
Spurs change when probing/fixture changes Fixture/probing introduces asymmetry and CM paths Use symmetric probing; reduce ground lead inductance; validate with consistent fixtures

Production hooks (record for repeatability)

  • Temperature points (cold / ambient / hot)
  • VOCM source and version (and any calibration/firmware identifier if applicable)
  • Key metrics binning: stability pass/fail, settling pass/fail, THD/SFDR, noise
  • Fixture version and measurement bandwidth notes (to keep data comparable)
Verification setup and measurement chain Block diagram showing signal source, fixture/cables, FDA board, AA/ADC, and analyzer. Markers indicate error injection points such as source distortion, fixture common-mode coupling, load/Cin effects, and VOCM noise. Source Fixture FDA board AA / ADC Analyzer dist CM Cin VOCM noise Validate at the ADC pins and control the test chain: source, fixture, load/Cin, and VOCM.

Applications & design hooks (FDA-only patterns)

This section lists FDA-relevant application patterns only. Each card is intentionally structured as: use case → key risks → selection focus → verification focus, with representative example parts to anchor choices without expanding into general op-amp categories.

A) Differential-input SAR / Pipeline ADC front-ends

Use case

FDA drives an ADC interface with controlled output common-mode (VOCM), typically through symmetric damping (Riso) and a simple AA handoff network at the ADC pins.

Key risks

  • VOCM mismatch: wrong common-mode target reduces headroom and can worsen distortion.
  • ADC Cin + sampling transients: phase margin collapses → ringing, peaking, or THD “cliffs”.
  • Asymmetry: unequal R/C/layout converts differential energy into CM leakage → even-order spurs.

Selection focus

  • Common-mode control: VOCM range and CMFB behavior must cover the ADC’s VCM requirement.
  • Dynamic linearity: THD/SFDR at the target frequency and load, not only DC plots.
  • Settling and drive: output current/swing must hold under the real AA + Cin environment.

Verification focus

  • Step response at ADC pins with the real AA/Cin: overshoot, ringing, long tails.
  • THD/SFDR sweep (amplitude + frequency) to find cliffs and CM-correlated spur growth.
  • Measure output CM vs VOCM to catch CM leakage paths early.

Representative FDA parts (examples)

TI THS4551 TI THS4531(A) ADI ADA4932-1 ADI ADA4940-1 ADI ADA4945-1 ADI/LTC LTC6363

Note: final part selection must match supply voltage, required output swing/drive, and measured stability with the intended AA/Cin.

B) Wideband differential chain (driving differential lines)

Use case

FDA provides a clean differential output with a controlled common-mode target to drive a differential trace/cable, feeding a differential receiver or ADC.

Key risks

  • Mismatch at high frequency: phase/amplitude imbalance → CM leakage and EMI.
  • Fixture/probing asymmetry: “spurs change with the probe” indicates injected CM paths.
  • Load variability: cables/connectors alter effective capacitance and damping.

Selection focus

  • Bandwidth with margin: choose FDA bandwidth to keep loop behavior stable at the target signal band.
  • Output drive: current/swing must survive cable + termination variations.
  • CM handling: predictable VOCM behavior reduces CM motion that otherwise converts into differential errors.

Verification focus

  • Repeat stability and distortion tests using consistent fixtures; compare short vs long interconnect.
  • Check CM leakage by monitoring output CM and even-order spur trends.
  • Confirm symmetric routing/termination to prevent diff-to-CM conversion.

Representative wideband FDA parts (examples)

TI THS4567 TI LMH6554 ADI ADA4932-1 ADI ADA4945-1

C) Precision DAQ handoff around PGA / multi-range (hint only)

Use case

FDA is placed at the handoff to a differential ADC, often near a gain-ranging stage. The goal is consistent VOCM alignment and predictable settling after range changes.

Key risks

  • Range-switch transients: charge injection and handoff imbalance create long settling tails.
  • Reference node contamination: VOCM noise behaves like a reference-noise injection into the ADC.
  • Asymmetric handoff: unequal paths after the gain stage create even-order distortion growth.

Selection focus

  • Low drift/noise tendency: prioritize stable behavior over temperature and time when DAQ accuracy dominates.
  • Predictable CMFB: VOCM range and behavior must match the DAQ common-mode plan.
  • Settling after events: fast recovery matters when range steps or multiplexing are present.

Verification focus

  • Compare small-signal vs large-signal settling after a “range event” (step or mux switch).
  • Track VOCM quality vs spur/noise changes; validate clean VOCM decoupling and return paths.
  • Record temperature points and configuration fields to support repeatable production binning.

Representative DAQ-leaning FDA parts (examples)

TI THS4531(A) ADI ADA4940-1 ADI/LTC LTC6363

D) DAC differential output buffering (handoff to reconstruction)

Use case

FDA buffers a differential DAC output, manages common-mode, and hands off into a reconstruction stage. This section covers the interface hooks only (stability, CM, and drive), not filter synthesis.

Key risks

  • Input/output headroom: DAC swing and CM must fit FDA input range and output swing limits.
  • Capacitive loading: reconstruction handoff adds C and can destabilize the loop without damping.
  • Mismatch: asymmetrical networks increase even-order distortion and CM leakage.

Selection focus

  • Low distortion priority: choose a part with strong THD/SFDR at the DAC output band.
  • Recovery behavior: fast overload recovery helps when large steps or glitches occur.
  • Stable handoff: ensure the device tolerates the intended C/load with symmetric damping options (Riso/snubber).

Verification focus

  • Check step response and distortion with the real handoff network connected (C/load sensitivity).
  • Sweep amplitude/frequency for THD/SFDR cliffs; verify CM behavior remains controlled.
  • Keep both sides symmetric: component values, placement, routing, and return paths.

Representative FDA parts (examples)

TI THS4551 ADI ADA4945-1 ADI ADA4932-1

Handoff only: for AA/reconstruction mathematics, use the dedicated filter pages. For PGA/multi-range architecture choices, use the PGA/INA pages. This page stays focused on FDA interface behavior (CM control, stability, settling, and symmetry).

FDA application mosaic: four FDA-relevant system patterns A four-tile mosaic diagram. Each tile shows a small system block diagram containing an FDA and its neighbors: ADC front-end, wideband differential line, precision DAQ handoff, and DAC buffering with reconstruction handoff. Minimal labels are used for clarity. A) ADC front-end B) Diff line drive C) Precision DAQ handoff D) DAC buffer handoff Source FDA VOCM AA ADC Riso Source FDA VOCM Line Rx/ADC Sensor PGA FDA VOCM Riso ADC DAC FDA VOCM Recon Load Four FDA-only patterns: ADC front-end, diff line drive, DAQ handoff, DAC buffering (handoff only).

IC selection logic (spec fields → risk mapping → RFQ template)

FDA selection becomes reliable when datasheet numbers are tied to conditions and mapped to failure signatures. This section turns selection into a repeatable workflow: gather the right fields, map them to risks, and ask vendors for missing conditions and recommended networks.

A) Spec fields to collect (FDA-relevant)

Each field must be recorded with its test conditions (supply, load, frequency, output swing, VOCM, and network). Without conditions, curves cannot be compared across parts.

Linearity / distortion

  • THD vs frequency (include output swing, load, gain, supply, VOCM, and interface network).
  • SFDR/IMD (two-tone if available; note amplitude spacing and load).
  • Distortion “cliffs” (any sudden worsening vs amplitude/frequency under realistic loading).

Speed / settling

  • Small-signal vs large-signal settling (record target accuracy, step size, and load/Cin).
  • Slew rate (necessary but not sufficient; must match the required swing and frequency).
  • GBW / closed-loop bandwidth (record intended gain; bandwidth alone does not guarantee stability).

Common-mode interface (FDA core)

  • VOCM range and VOCM input impedance (whether buffering or isolation is recommended).
  • Output CM range and CM behavior vs load/frequency (how the CM loop behaves in real networks).
  • Input/output headroom vs supply and load (verify at operating frequency, not only DC).

Drive / stability under real loading

  • Output current capability and swing vs frequency (include load and any series damping).
  • Capacitive load stability statement and the recommended network (Riso/snubber ranges).
  • Reference circuits for driving ADC Cin / AA handoff (symmetry requirements and component placement cues).

Noise / power / thermal

  • en / in with the intended source impedance and bandwidth integration plan.
  • VOCM noise coupling risk (VOCM quality becomes output CM noise that the ADC can see).
  • IQ, package RθJA, and temperature behavior (drift and distortion sensitivity in hot conditions).

B) Risk mapping (spec → failure signature → likely cause → fix direction)

Spec shortfall Failure signature Likely cause Fix direction
THD vs freq is insufficient Harmonics rise or SFDR drops; “cliff” appears with amplitude/frequency sweep Output stage nonlinearity, CM loop interaction, or load-induced distortion Verify conditions; reduce load sensitivity (Riso/snubber); ensure symmetry at ADC pins
VOCM/CM behavior is unclear Even-order spurs grow; code pattern drifts with VOCM noise or layout changes CM leakage from asymmetry, VOCM contamination, or CM loop instability Improve VOCM decoupling/return; add isolation; enforce symmetric networks and routing
Output drive is insufficient Settling error; long recovery tails; distortion worsens at high swing Current limit, headroom loss, or load/Cin too heavy at the target band Budget swing and load; add damping; reduce Cin; choose a stronger driver or higher supply
Stability network is not defined Ringing/oscillation appears only after AA/ADC is connected Cin/AA loads collapse phase margin; parasitics add hidden poles Start with conservative symmetric Riso; add snubber; validate at ADC pins
EMI/layout sensitivity is high Intermittent issues on site; spurs change with cables/probes/hand proximity CM pickup and diff-to-CM conversion due to asymmetry and return path breaks Enforce symmetry; keep returns continuous; isolate VOCM; verify with consistent fixtures
Noise budget is mismatched Noise floor higher than expected; peaking bump appears in-band Bandwidth integration, peaking from light damping, or VOCM noise injection Integrate noise over the real band; improve damping; clean VOCM and its return path

C) Vendor RFQ template (copy/paste)

Please provide the following information for FDA evaluation. Responses must include test conditions and recommended networks for ADC/Cin loading.

  • THD/SFDR conditions: frequency points, output swing (per-side and differential), gain, supply, load, VOCM, and interface network.
  • VOCM specifications: VOCM range, VOCM input impedance, recommended VOCM driver/buffer, local decoupling guidance, and multi-channel sharing guidance.
  • Stability guidance: recommended Riso range, snubber options (if any), and a stated Cin/load range for stable operation.
  • Settling behavior: small-signal and large-signal settling definitions, target error level, step size, and load/Cin conditions.
  • Reference resources: evaluation board part number, reference schematic, and PCB layout files (or layout guidance) for ADC driving use cases.
  • Thermal behavior: RθJA by package and any distortion/CM sensitivity vs temperature.
FDA selection funnel: specs to risks to vendor questions Three-column funnel diagram. Left column lists key spec fields such as THD vs f, Iout, VOCM range, and capacitive load stability. Middle column lists failure signatures such as even-order spur, ringing, and long settling tail. Right column lists RFQ questions such as THD conditions, VOCM specs, and recommended stability network. Spec fields Risk signatures Vendor questions THD vs freq GBW / BW Slew rate Iout / drive VOCM range VOCM input Z C-load stable Noise / thermal Even-order spur THD cliff Ringing / peaking Long settling tail CM drift/leakage EMI sensitivity THD conditions VOCM specs Stability network Cin/load range EVM & layout Settling method Record conditions with every spec; map to signatures; then request missing stability/VOCM details and reference networks.

Engineering checklist (reusable review sheets)

The checklist below compresses FDA best practices into repeatable review items. Each block is grouped as P0 (must) and P1 (should), with short, checkable statements suitable for reviews and bring-up.

A) Schematic checklist (VOCM, decoupling, Riso/RC, symmetry)

P0 (must)

  • VOCM source is defined and compatible with the target output CM level.
  • VOCM has local decoupling and a clean return path (no noisy current sharing).
  • Output damping (Riso) is symmetric and placed for a clean handoff to the load/ADC pins.
  • Any RC/snubber footprints preserve symmetry (matched values and mirrored placement).
  • Input/feedback network is symmetric and does not add one-sided capacitance.

P1 (should)

  • Riso/snubber tuning footprints are provided for bring-up (value sweep without re-spin).
  • Symmetric test points are placed at the real measurement location (ADC pins / handoff node).
  • Power domains and decoupling plan are explicit (which caps serve which pins and returns).

Quick signature: even-order spurs or CM-sensitive behavior typically points to VOCM quality and symmetry gaps.

B) PCB checklist (returns, symmetry, sensitive nodes, partitioning)

P0 (must)

  • Differential paths are routed over continuous reference planes (no plane splits under either side).
  • Both sides see the same environment: matched vias, layer changes, and nearby aggressors.
  • Decoupling loops are minimized; return paths are short and do not detour across gaps.
  • VOCM return is kept clean and local; it does not share large switching/digital currents.
  • Riso/AA components are mirrored; routing from FDA to the handoff is symmetric.

P1 (should)

  • Sensitive nodes (inputs, feedback, VOCM) are short and shielded by stable references.
  • Keep fast clocks and switching edges away from the FDA output/AA handoff region.
  • Provide a consistent probing strategy that does not introduce asymmetry during debug.

Quick signature: “spurs change with cables/probes” usually indicates fixture-induced asymmetry and CM coupling.

C) Bring-up checklist (step, ringing, CM motion, temperature)

P0 (must)

  1. Power-up sanity: verify VOCM and output CM center; confirm no burst oscillation.
  2. Stability baseline: step response with minimal known load, then with real AA/Cin.
  3. Settling: compare small-signal vs large-signal steps; check long tails.
  4. Distortion: sweep amplitude and frequency to locate THD/SFDR cliffs.
  5. CM correlation: monitor output CM vs spur changes (even-order trends).
  6. Thermal: repeat key checks after warm-up; confirm stability and distortion do not drift unexpectedly.

P1 (should)

  • Run A/B tests with consistent fixtures (short vs long cables, controlled terminations).
  • Record the exact measurement bandwidth and probing method to keep results comparable.
  • Validate damping tuning range (Riso/snubber) and capture “safe” default values.

Quick signature: ringing that appears only with the real load usually points to Cin/AA interaction and missing damping.

D) Production test suggestions (temperature points, binning fields, versioning)

Recommended record fields

  • Serial number, lot, board revision, and fixture revision.
  • Temperature points: cold / ambient / hot (use consistent soak time).
  • VOCM source and configuration identifier (and any calibration/reference version fields if applicable).
  • Binning metrics: stability pass/fail, settling pass/fail, THD/SFDR, wideband noise.
  • Measurement bandwidth and probing method notes (avoid non-comparable data across runs).

Quick signature: consistent binning requires consistent fixtures, bandwidth settings, and clearly recorded VOCM/config conditions.

FDA checklist dashboard: schematic, PCB, bring-up, and production A four-lane dashboard diagram. Lanes represent Schematic, PCB, Bring-up, and Production. Each lane contains check icons with short labels such as VOCM, decap, Riso symmetry, return path, step test, CM monitor, and temp bins. Arrows show the flow from design to production. Design Production Schematic PCB Bring-up Production VOCM defined Decap loops Riso symmetry Tuning pads No plane splits Return path Symmetric vias VOCM return Step test THD sweep CM monitor Thermal recheck Temp bins Binning fields VOCM version Fixture rev Use this dashboard as a review gate: schematic → PCB → bring-up → production data.

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FAQs – Fully-Differential Amplifier (FDA) Design

These FAQs focus only on FDA-specific failure signatures and interface decisions (VOCM, symmetry, Cin/AA loading, and verification). They intentionally avoid expanding into filter design, generic op amp selection, or ADC architecture.

Why does THD get worse after adding the anti-alias RC network?

THD often worsens because the RC network changes the effective load and phase margin, and any imbalance converts differential signal into common-mode error.

Most likely causes

  • No (or too small) symmetric isolation resistors, so ADC Cin/RC loads collapse loop margin.
  • RC parts are not perfectly symmetric between +/− paths (diff-to-CM leakage rises).
  • Measurements are taken away from the real handoff node (ADC pins), hiding peaking/ringing.

Quick checks / fixes

  • Add symmetric Riso first, then retune RC with the real load connected.
  • Mirror placement and values; verify both sides see the same parasitics and return paths.
  • Repeat THD sweep after confirming step response has no excessive ringing/peaking.
How should VOCM be generated and filtered without injecting noise?

Generate VOCM from a low-impedance, low-noise source (often the ADC VCM), then decouple it locally with a clean return path so VOCM noise does not become output common-mode noise.

Most likely causes of noisy VOCM

  • VOCM is high impedance or comes through a noisy divider without buffering.
  • VOCM decoupling shares return current with switching/digital paths.
  • VOCM is routed long and picks up interference, then feeds the CM loop.

Quick checks / fixes

  • Use the ADC VCM pin when available; otherwise buffer the mid-reference.
  • Place VOCM decoupling near the FDA VOCM pin with a dedicated, short return.
  • Add small isolation between the VOCM source and each channel if sharing.
Can one VOCM source drive multiple FDA channels safely?

Yes, if the VOCM source is buffered and distributed in a star topology with per-channel isolation and local decoupling; otherwise channels can modulate each other through VOCM.

Most likely failure modes

  • Correlated even-order spurs across channels (shared VOCM noise becomes coherent).
  • Cross-talk where activity in one channel shifts CM behavior in another.
  • VOCM line resonance due to long routing and insufficient damping.

Quick checks / fixes

  • Buffer VOCM, distribute by star, and add a small isolation resistor per channel.
  • Give each channel its own local VOCM decoupling and short return path.
  • Measure channel-to-channel correlation of spurs to confirm shared coupling.
What is the most common reason for “mystery” oscillation with an ADC input?

The most common cause is inadequate damping when the FDA drives the ADC input capacitance and sampling transients, especially if the interface network is not symmetric.

Most likely causes

  • Missing/undersized symmetric Riso between FDA outputs and the Cin/AA node.
  • Unbalanced RC/AA network or placement, converting diff energy into CM excitation.
  • Hidden parasitics and broken return paths near the handoff node.

Quick checks / fixes

  • Temporarily increase symmetric Riso and check if ringing collapses.
  • Check step response at the ADC pins (not only at the FDA pins).
  • Mirror routing/parts and keep the RC/AA node compact with clean returns.
How to choose isolation resistors without degrading noise too much?

Choose isolation resistors to secure stability first, then reduce value while keeping symmetric placement and acceptable step response; the noise penalty is often smaller than the cost of peaking or oscillation.

Most likely pitfalls

  • Picking Riso only by “noise fear” and ending up with marginal phase margin.
  • Using different values/placement on the + and − paths, increasing CM leakage.
  • Placing Riso far from the handoff node, leaving the Cin/AA node undamped.

Quick checks / fixes

  • Start conservative, validate step response, then reduce value until peaking returns.
  • Keep both sides perfectly matched and mirrored at the same electrical location.
  • Verify THD/SFDR again after stability is confirmed at the ADC pins.
Why does output common-mode drift with temperature or load?

Output common-mode can drift when headroom changes with load or temperature, when VOCM source impedance shifts, or when return paths inject CM error into the CM loop.

Most likely causes

  • Output stage headroom or current capability changes with load and supply margin.
  • VOCM source is not low impedance or is shared without isolation/decoupling.
  • Asymmetric routing/returns convert load current into CM movement.

Quick checks / fixes

  • Hold VOCM fixed and sweep load to see if CM drift follows load current.
  • Improve VOCM buffering/decoupling and confirm its return stays clean.
  • Re-check headroom budget at operating frequency and real load.
Why do even-order spurs increase when the layout is slightly asymmetric?

Even-order spurs rise when asymmetry converts differential content into common-mode error, which the ADC can interpret as distortion and spur energy.

Most likely causes

  • One side has extra vias/layer changes or a different reference plane environment.
  • One side’s RC/AA component placement adds extra parasitic capacitance.
  • Return paths are different, causing unequal CM pickup and leakage.

Quick checks / fixes

  • Mirror routing and component placement; ensure both sides see the same parasitics.
  • Probe both outputs symmetrically; avoid adding extra capacitance to only one side.
  • Confirm VOCM return and local decoupling are not coupling load current into CM.
How to check settling error without an ultra-fast scope?

Settling can be checked using ADC-based methods (code-domain windows and step patterns) and by verifying step-response peaking rather than relying on extremely fast scopes.

Practical methods

  • Use a repeatable step stimulus and analyze ADC codes in time windows after the step.
  • Compare small-step vs large-step responses; long tails often show up only on large steps.
  • Check frequency-domain peaking signatures that correlate with time-domain ringing.

Quick checks / fixes

  • Run the test with and without the real AA/Cin load to isolate load-driven settling limits.
  • Validate at the handoff node (ADC pins) and keep measurement fixtures symmetric.
What probe/fixture mistakes can fake distortion or stability issues?

Asymmetric probing and unknown fixture impedance can inject extra capacitance or CM pickup, creating fake spurs, ringing, or an apparent THD cliff that is not from the FDA itself.

Common mistakes

  • Probing only one side with high capacitance or long ground leads.
  • Using different probes/cables on + and − outputs (fixture becomes asymmetric).
  • Measuring at a node that is not the real handoff point (misleading stability picture).

Quick checks / fixes

  • Use symmetric probing (or a true differential probe) and keep grounds extremely short.
  • Lock down fixture impedance and cable lengths so tests remain comparable.
  • Repeat a known-good reference measurement to validate the setup.
When is a transformer or passive balun a better option than an FDA?

A transformer/balun can be better when DC coupling and VOCM control are not required, and when passive conversion offers simpler wideband matching or isolation at the target band.

Use passive options when

  • DC coupling is not needed (AC coupling is acceptable).
  • Output common-mode must not be actively controlled by VOCM.
  • Isolation or simple wideband conversion is the priority over tunable gain.

Quick checks

  • Confirm the ADC input CM requirements and whether the front-end can be AC-coupled.
  • Compare fixture complexity, bandwidth, and sensitivity to layout asymmetry.
How to interpret FDA datasheet THD plots vs real ADC SFDR?

Datasheet THD is valid only under its stated conditions, while real ADC SFDR also includes sampling transients, Cin loading, AA networks, and layout symmetry at the handoff node.

Condition alignment checklist

  • Frequency point, amplitude (per-side vs differential), gain, supply, and load.
  • VOCM source/decoupling and whether the CM loop sees noise or impedance.
  • ADC Cin and AA network present (and measured at the ADC pins).
  • Measurement bandwidth and fixture symmetry (avoid setup-induced spurs).

Quick checks

  • Validate step response and peaking first; instability can dominate distortion.
  • Compare a “minimal load” case vs the real ADC load to quantify degradation.
What minimum production data should be logged to catch drift early?

Log a small, consistent dataset that ties performance to configuration and conditions: identifiers, temperature points, key metrics, and the VOCM/setup versions that affect CM behavior.

Minimum fields

  • Serial number, lot, board revision, and fixture revision.
  • Temperature points (cold / ambient / hot) and soak time definition.
  • VOCM source/config identifier and any reference/firmware version fields.
  • Binning metrics: stability pass/fail, settling pass/fail, THD/SFDR, wideband noise.

Quick checks

  • Trend even-order spur levels and CM-related metrics across temperature and lots.
  • Keep measurement bandwidth and fixture definitions fixed to avoid false drift.
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