Three deliverables

1. Selection constraints: the minimal parameter set that determines whether a driver can meet settling/THD/noise targets.
2. Connection topology: a proven wiring pattern (including Riso/snubber/VOCM) that avoids “works in sim, fails on board”.
3. Verification plan: a short bring-up checklist that isolates root cause with one variable change at a time.

Input condition / setup	Typical symptom	Likely risk	First response (minimal change)
SAR ADC, low source impedance requirement, fast sampling window	Code-dependent ripple, missing ENOB, step looks “slow”	Kickback + insufficient settling (effective RC too large)	Add Riso close to driver output; reduce impedance level; validate with single-tone + step test
Differential ADC with VOCM pin or CM target	Unexpected clipping, THD rises near peaks, drift with load	CM/range mismatch (headroom loss, CM modulation)	Lock VOCM to the converter reference; verify CM with DC sweep + large-signal THD at same amplitude
AAF added (higher order / high-Q / low impedance)	Ringing, sporadic oscillation, SFDR worse than expected	Stability margin collapse (extra poles/zeros + C-load)	Increase damping (Riso / RC snubber); reduce filter impedance sensitivity; confirm by step response with/without AAF
DAC → buffer → reconstruction → capacitive/low-Ω load	Overshoot, long settle, “stable in sim” but rings on board	Output stage current/phase margin limits + load C	Add isolation + snubber near the load; verify with midscale step + worst-case cable/load C

Converter I/O	What the driver sees	Must-know parameters	Dominant risk	Typical driver topology
SAR ADC input	Switched-cap load with sampling kickback; the load changes at the sampling edge.	Cineff, sampling rate, acquisition window, allowed Rsource, input range and CM target	Settling + stability (C-load) → ENOB/SFDR loss	Inverting driver or FDA, with Riso and controlled RC at the interface node
Pipeline ADC input	More continuous input behavior, but linearity and bandwidth demands are strict at high input frequency.	Input range/CM window, input impedance vs frequency, required SFDR/THD vs fin	Distortion + phase margin erosion through AAF/driver chain	FDA + symmetric AAF; impedance level chosen for distortion and stability
ΣΔ ADC input (front-end)	Often lower signal bandwidth; front-end bandwidth choices interact with noise and anti-alias strategy.	Signal BW, required noise density / 0.1–10 Hz needs, input CM/range constraints	Noise budgeting + stability with input protection/RC	Precision buffer / INA / PGA class drivers with controlled input RC
Voltage-output DAC	Output step + settling requirement; stability depends on load R/C and reconstruction network.	Output range, update rate, target settling time, worst-case load R/C (including cable)	Overshoot/ringing + long settle → code-to-code errors	Buffer + Riso/snubber; reconstruction chosen to avoid phase-margin collapse
Current-output DAC	A current source with compliance limits; I/V conversion defines linearity and noise.	Compliance window, full-scale current, Rf/Cf, output swing and headroom	I/V stability + distortion from output swing/current	TIA (I/V) with explicit compensation and short feedback loop

Minimum parameter set to extract (before committing to layout)

• Range window: full-scale input/output range, reference level, and required headroom at the chosen supply.
• CM target: VOCM source, allowable CM error, and whether CM is enforced by the converter or must be generated/buffered.
• Interface loading: Cin_eff (or switched-C hints), recommended source impedance, and any internal input network notes.
• Timing: sampling/update rate plus the actual acquisition/settling window that the driver must meet.
• Worst-case load: resistive load, capacitive load, cable capacitance, and connector ESD/EMI components.

If the datasheet does not provide enough I/O detail (what to measure)

1. Step response at the interface node: compare ringing/settle with and without the filter network connected.
2. One-variable THD scan: keep amplitude fixed, change only load (R then C), and observe which change creates the THD knee.
3. Riso sensitivity: sweep a small series resistor (close to the driver output). If performance improves, the problem is likely C-load/kickback driven.

Start here (quick entry points)

• Differential ADC or VOCM target is required → prefer FDA (explicit CM control and symmetric filtering).
• SAR / switched-cap input with a tight acquisition window → prefer inverting driver or FDA (controlled interface impedance).
• Current-output DAC → use TIA (I/V) (virtual-ground stability and compliance window define linearity).

Input / output condition	Recommended topology	Main risks (Top 3)	Minimal verification (3–5 tests)
SAR ADC, single-ended input, tight acquisition window, low allowed source impedance	Inverting driver (or FDA if differential is acceptable), with controlled interface RC + Riso	(1) Kickback-driven settling error (2) C-load stability collapse (3) Noise-gain peaking from feedback network	Step response at interface node 1-tone SFDR vs amplitude (same f) Riso sweep sensitivity Compare with/without AAF connected
Single-ended ADC, moderate Cin, relaxed settling window, light load	Non-inverting buffer (unity or small gain), optional Riso for safety	(1) Output swing headroom loss (2) C-load ringing from ESD/RC networks (3) Probe/cable capacitance altering stability	DC sweep for clipping margin Step response with worst-case probe/cable THD vs load (R then C)
Differential ADC, VOCM target required, symmetric AAF desired	FDA (explicit VOCM), symmetric RC/AAF around the interface node	(1) CM loop interaction with filter poles (2) Range/CM mismatch → hidden THD knee (3) Mismatch/asymmetry from layout/tolerances	Measure VOCM (DC + dynamic) THD/SFDR vs amplitude at fixed f Step response differential + CM node Swap filter values (sensitivity)
High-frequency chain where galvanic/AC coupling helps, CM control is not tight	Single-ended to differential (transformer / driver stage) with proper termination	(1) Low-frequency droop/phase mismatch (2) Termination imbalance → spurs (3) CM behavior depends on environment/ground	SFDR vs frequency sweep Balance check (amplitude/phase mismatch) Termination tolerance sensitivity
Current-output DAC (Iout), compliance window matters, linearity is critical	TIA (I/V): short feedback loop, explicit Rf/Cf compensation, keep virtual ground stable	(1) Compliance violation (virtual ground shifts) (2) Rf/Cf peaking → ringing/long-tail settle (3) Output swing headroom → THD knee	Midscale-to-fullscale step settle THD vs amplitude (knee detection) Rf/Cf sensitivity sweep

Practical selection rules (stable, measurable)

• Tight SAR acquisition favors inverting or FDA: the interface impedance can be set by resistors rather than by output stage behavior.
• VOCM matters → use FDA: CM and differential swing can be controlled independently.
• Current DAC → use TIA: compliance and feedback stability define linearity more than “high GBW” marketing.

Map the converter window to the driver linear window

• Converter window: input range definition (Vref/full-scale) plus the required CM point (VOCM or bias level).
• Driver linear window: the output swing that remains linear at the actual load and supply (R load, C load, frequency class, temperature).
• Usable window is the overlap. If overlap shrinks, the system loses codes or hits a THD knee long before visible clipping.

Two practical rules that prevent hidden failures

• Headroom loss causes THD collapse first. THD vs amplitude typically shows a clear knee before hard clipping appears.
• Input CM range affects both linearity and stability. A “valid CM range” on paper can still be a poor operating point at high swing or high frequency.

Budget item	What to enter	Why it matters	Verification hook
Vref / full-scale window	Vmin/Vmax (or Vdiff_pp + Vcm target)	Defines required peak swing and where clipping starts	DC sweep and code histogram near endpoints
VOCM source	ADC VOCM pin / divider / buffered reference	CM error turns into asymmetric headroom and spur growth	Measure CM (DC and under large-signal)
Driver swing capability	Vout_min_lin / Vout_max_lin @ (load R/C, supply, temp)	“RRIO” does not guarantee linear swing near rails at the target load	THD vs amplitude knee detection
Margin (mV)	Margin_high and margin_low (computed from above)	If margin is small, temperature and load variation will break linearity first	Repeat sweep across supply and temperature corners

Typical symptom map (what to suspect first)

• SNR/ENOB below expectation → settling error inside the sampling window is often dominant.
• SFDR/THD knee vs amplitude → headroom and recovery dynamics can collapse before visible clipping.
• Step response rings or has a long tail → phase margin reduced by effective C-load and multi-pole network.
• Only “certain” AAF values cause trouble → filter impedance/Q shifted the loop into a fragile region (handled in H2-6).

What happens at the sampling edge (event chain)

1. Switch action → the sampling network reconfigures.
2. Charge injection → charge is pushed/pulled at the input node.
3. Output tug → the driver output sees a fast transient (glitch / kickback).
4. Closed-loop recovery → the amplifier must return inside the error band before the acquisition window ends.

• Error target: define the allowed in-window error (example: a fraction of 1 LSB).
• Time constant contributors: the effective τ is driven by the impedance feeding the node and the effective input capacitance.
• Multi-pole sources: AAF, output isolation/snubber, and the amplifier closed-loop response can add poles/zeros that create ringing or long tails.

Item	Enter / estimate	Pass check	Measure hook
Sampling rate / mode	fs and any reduced acquisition window	Window is known (not assumed)	Scope capture aligned to sample edge
Error target	Allowed in-window error (LSB fraction)	Target is written and reviewed	ENOB/SFDR vs amplitude knee
Cin_eff	Datasheet/estimate/measurement note	Source is documented	Compare with/without AAF connected
R budget	Rsource + Riso + impedance level	Margins exist (not zero)	Riso sweep sensitivity
Multi-pole risk	AAF / snubber / closed-loop peaking	Ringing and tail are controlled	Step response with worst-case load

Three coupling axes (what changes when AAF is added)

• Shape / Q: higher Q and sharper transitions can add rapid phase rotation near the loop crossover.
• Impedance level: low impedance forces higher output current, exposing output-stage nonlinearity and earlier THD knees.
• Capacitor placement: capacitors at the output node or inside feedback are high-risk for stability sensitivity.

Stability-first procedure (do this order)

1. Pick a conservative impedance level (avoid extreme low-R filters on the first pass).
2. Add damping (Riso / small snubber) to remove ringing and long tails.
3. Only then adjust Q/roll-off to meet alias rejection goals.
4. Verify with step response, then THD/SFDR vs amplitude, then tolerance sensitivity.

Goal	Recommended bucket	Sensitive parameters (Top 3)	Primary symptom	Priority checks
Mild roll-off + minimal risk	Buffered RC (simple, damped)	Output C, Riso, input RC level	Small ringing / settle tail	Step response → Riso sweep → THD vs amplitude
Steeper roll-off with controlled behavior	Symmetric differential AAF (with FDA)	Component ratio matching, VOCM stability, impedance level	SFDR worse than expected	Diff + CM step capture → THD knee → tolerance sensitivity
Aggressive stopband target (higher risk)	Active high-order / MFB style blocks	Feedback capacitors, high-Q node, output C-load	Oscillation / peaking / long settle	Step response first → stability margin check → THD/SFDR

Distortion sources (system-relevant buckets)

• Output current stress: heavier R load or higher frequency increases current demand and nonlinearity.
• Headroom near rails: THD knee appears before visible clipping when swing approaches the linear window edges.
• CM modulation (FDA): VOCM path and CM loop can move operating points and generate spurs.
• Capacitive loading: C-load or AAF coupling reshapes the loop and deforms waveforms.
• Crossover / output stage regions: certain current regions can show disproportionate harmonics.

Dominant-term workflow (change one variable at a time)

1. Hold frequency, amplitude, supply, and load constant → measure baseline THD.
2. Sweep R load (light → heavy) → observe THD slope sensitivity to current demand.
3. Add/sweep C load (or connect AAF) → check if THD worsens with ringing / long tails.
4. Sweep amplitude → find a clear THD knee (headroom / output stage limit).
5. Sweep supply → if the knee moves strongly, headroom is likely dominant.
6. FDA only: change VOCM source/RC → strong THD change indicates CM-loop contribution.

Dominant cause	Signature in sweeps	Top fixes	Must re-verify
Output current stress	THD worsens strongly with heavier R load and/or higher f	Raise impedance level (larger R in AAF) Reduce load current demand (lighter load / buffer stage) Use a driver with higher linear output current	THD vs load and THD vs frequency
Headroom / linear window limit	Clear THD knee vs amplitude; knee shifts with supply	Increase supply headroom (if allowed) Reduce output swing / re-center CM target Choose a part with better near-rail linearity at the real load	THD knee and clipping margin across corners
Stability / waveform deformation	THD worsens when C-load/AAF is connected; step rings/long tail	Add damping (Riso / snubber) Lower Q / reduce output-node capacitance Use a topology with more predictable interface impedance	Step response + THD vs amplitude after damping
FDA CM-loop contribution	THD changes with VOCM source/RC even when diff path is unchanged	Buffer VOCM / reduce VOCM impedance Review CM RC and symmetry around the AAF Verify CM node behavior under large-signal	CM node capture + THD knee comparison

Category	Set points	Record fields	Conclusion
Frequency points	Low / mid / high (application-relevant)	THD, H2, H3, notes	Slope vs frequency
Amplitude points	20% / 50% / 80% / 95% FS	THD knee, clipping note	Headroom indicator
Load sets	R: light/mid/heavy + C: none/added/AAF	R/C config, step response note	Current vs stability
Supply sets	Nominal / low / high	Knee movement vs V	Headroom confirmation
FDA VOCM (if used)	VOCM pin vs divider vs buffered	VOCM node level and THD delta	CM-loop contribution

Key tradeoffs (what matters most)

• en vs in: low source-Z tends to be en-dominated; high source-Z tends to be in×Rs dominated.
• Effective noise bandwidth: set by AAF/RC and any digital processing (averaging/decimation), not by GBW.
• 0.1–10 Hz vs wideband: low-frequency noise matters for slow measurements; wideband matters for instantaneous SNR.
• Priority rule: if ADC input noise dominates, chasing ultra-low en in the driver brings little benefit.

Field	Meaning	Contribution to compute	Use to decide
Rs (effective)	Sensor + series resistors + filter impedance level	Rs thermal noise	Whether in×Rs dominates
Op amp en	Input voltage noise density	en integrated over BW	Low-Z optimization
Op amp in	Input current noise density	(in × Rs) integrated over BW	High-Z optimization
Gain / noise gain	Signal gain and noise amplification path	Scale each term to the same reference	Avoid wrong comparisons
Effective noise BW	Set by AAF/RC + processing	Integrate densities into RMS	BW is the lever
ADC input noise	Converter noise floor (ADC-referred)	ADC RMS in same band	Whether ADC dominates
Total RMS + ENOB impact	RSS sum of all contributions	Total RMS at ADC codes	Prioritize the dominant term

Practical decision rule (use as a checklist)

• If ADC input noise is the largest bar, reduce bandwidth or improve the converter/reference path first.
• If in × Rs dominates, reduce Rs or choose a part with lower current noise / higher input impedance class.
• If en dominates, pick lower en only after confirming the BW and gain/noise-gain are realistic.

Break down “DAC settling” into three measurable segments

1. DAC core settling: internal step response under datasheet conditions (often a light, ideal load).
2. Buffer settling: closed-loop recovery and damping against the real output node (Cload, impedance level).
3. Reconstruction delay: group delay and tails that extend time-to-error-band even when overshoot is controlled.

Define pass/fail with concrete step metrics (no vague “looks stable”)

• Overshoot: peak excursion beyond final value (mV or %FS).
• Ringing: number of cycles and dominant ringing band (helps localize pole/zero interactions).
• Settling-to-band: time to enter and remain within an error band (e.g., %FS or a code-equivalent band).
• Worst-case code pattern: midscale jump is typically the most revealing for energy and recovery.

Reconstruction co-design (only the coupling that changes settling)

• RC vs active recon: both reshape the output node impedance and can change damping and recovery.
• Impedance level: larger resistor values reduce current stress but may increase sensitivity to parasitics and noise.
• Load capacitance (including cables): can dominate the waveform unless isolation/damping is planned in early.

Item	Set points	Record	Conclusion
Step amplitude	10% / 50% / 90% FS	overshoot, ringing cycles, settling-to-band	knee vs amplitude
Code pattern	midscale jump + small-step (optional)	worst-case waveform notes	pattern sensitivity
Load sets	R light/mid/heavy + C none/small/large + cable A/B	dominant ringing band, settling delta	load-dominant?
Recon options	none / RC / active, target BW	group-delay tail, time-to-band	delay-dominant?
Probe setup	10×, short ground spring, bandwidth note	waveform change vs probe config	measurement artifact?

Common stability pitfalls (field-proven)

• “Unity-gain stable” ≠ any network: external RC and load C create extra poles/zeros the datasheet test never saw.
• Probe capacitance is a component: probing the wrong node can add a pole and fake or hide ringing.
• Long return paths: ground leads and loop inductance can manufacture “ringing” that is not in the circuit.

Step	Configuration	Single variable added	Observe
1	Minimal loop, short routing	None (baseline)	step overshoot, ringing, DC shift
2	Baseline + capacitive load	Add Cload	margin loss, peaking
3	Baseline + filter network	Add AAF / recon RC	new poles/zeros, tail
4	Filter + interface load	Add ADC/DAC input network	peaking, distortion, recovery
5	Full reality	Cable / connector / remote load	worst-case ringing

Reusable fix toolbox (where it acts + what it costs)

• Riso at the output pin: isolates C-load and increases damping; cost is higher output impedance and potential settling impact.
• RC snubber at the problem node: absorbs HF energy and reduces ringing; cost is added load current and heat.
• Feedback shaping (noise-gain / compensation): improves phase margin at crossover; cost can be higher noise gain or reduced bandwidth.

Bring-up priorities (run in this order)

Start with P0 even if the waveform looks good. A wrong CM/range setup can make THD and settling numbers meaningless.

If only 3 tests are allowed, run these 3

1. DC range & common-mode check (prevent code loss and clipping).
2. Step response with the worst-case pattern (capture overshoot, ringing, settling-to-band).
3. THD/SFDR sweep using a small set of frequency points and a sweep of amplitude and load (find distortion knees).

For low-frequency precision projects, replace the third item with noise integration vs averaging.

Measurement playbook (how to avoid false conclusions)

• One variable at a time: change only load, only filter, or only damping—never multiple knobs at once.
• Worst-case stimulus first: midscale jump for step tests; high swing for THD knee discovery.
• Probe is part of the circuit: prefer 10× probes with short ground springs; log probe type and bandwidth limits.
• Regression discipline: after every fix, re-run the same test set with the same schema and compare deltas.

Test record schema (log fields that make results reproducible)

Use the same schema for every change. “Better” without a comparable log is not a result.

Example part numbers for a validation toolkit (fixtures & interconnect)

These are commonly used examples for building repeatable test conditions (termination, coupling, impedance control, probing). Verify frequency range, power, voltage, and interface constraints for the target chain.

Why can SFDR get worse after adding an anti-alias (AAF) or reconstruction filter?

Adding a filter changes the impedance and phase seen by the driver; reduced phase margin or stressed output current can raise distortion and spurs even if the magnitude response looks correct.

• Most-likely causes: Q/impedance too aggressive; extra output-node capacitance; noise-gain peaking from the RC network.
• Fast checks: lower Q or raise impedance level; add/remove C at the output node to see sensitivity; compare THD/SFDR with filter bypass.
• Fix + verify: add output isolation (Riso) or damping; re-run step settling and THD/SFDR at the same amplitude/load.

Data fields

Signals: sine + step · Knobs: filter on/off, Q/values, load(R/C), Riso · Readouts: SFDR, THD, overshoot, settling-to-band

“Unity-gain stable” — why can an op amp still oscillate when driving an ADC input?

Unity-gain stability is validated under specific loads and networks; ADC inputs and external RC networks add poles/zeros that can reduce phase margin.

• Most-likely causes: effective C-load at the output node; noise-gain increase from feedback/filter; probe/cable parasitics.
• Fast checks: test baseline (no ADC/filter) then add one element at a time; swap probe ground method; add small Riso as a diagnostic.
• Fix + verify: permanent Riso/snubber/feedback shaping; re-run step response and confirm no oscillation across load cases.

Data fields

Signals: step · Knobs: Cload, filter, ADC network, probe · Readouts: ringing cycles, overshoot, oscillation frequency, settling-to-band

For a SAR ADC, how can kickback be confirmed as the dominant settling problem?

If the error scales strongly with source impedance and improves immediately with isolation/damping, kickback and the acquisition transient are likely dominant.

• Most-likely causes: high effective source resistance; insufficient driver recovery during acquisition; output-node resonance with Cin/network.
• Fast checks: add a small Riso and observe step recovery; reduce source R (or use inverting drive) and compare; shorten/clean the input loop to reduce parasitics.
• Fix + verify: control the output node (Riso + small C if needed) and re-check settling-to-band at the acquisition window limit.

Data fields

Signals: step + sampled sine · Knobs: Rsource/Riso, Cin estimate, acquisition window · Readouts: settling margin, SNR/ENOB delta, transient amplitude

If settling is short, should resistance be reduced first or should a higher-GBW op amp be used?

Reduce effective source resistance first (or isolate the output node) unless evidence shows loop gain/phase margin is the limiting factor; GBW alone does not guarantee better settling.

• Most-likely causes: RC time constant dominates; output-node resonance; phase margin collapse under the real load/network.
• Fast checks: halve the key series R and re-measure settling; add small Riso and compare; reduce swing to see if distortion/headroom is coupling into the waveform.
• Fix + verify: meet a controlled RC target first, then tune stability; re-run the same step test across loads.

Data fields

Signals: step · Knobs: series R, Riso, swing · Readouts: settling-to-band, overshoot, ringing cycles

Should VOCM come from the ADC pin or an external divider, and when is buffering mandatory?

Use the ADC VOCM pin when it is intended to drive the required CM load; buffer it when the CM node sees significant loading, filtering, or multiple channels that can modulate CM.

• Most-likely causes (when wrong): CM droop under load; CM ripple coupled into distortion; clipping from wrong CM window.
• Fast checks: measure VOCM under dynamic output; compare THD with CM source A vs B; check CM node for unexpected ripple.
• Fix + verify: buffer VOCM and keep routing clean; verify CM error and THD knee do not move with load.

Data fields

Signals: sine + DC · Knobs: VOCM source, CM load, channel count · Readouts: CM error, THD/SFDR, clip flags

The same op amp has good THD at 10 kΩ, but collapses at 600 Ω. What is the most common root cause?

Output-stage current and headroom stress are the most common causes; heavier loads push the output closer to nonlinear regions and can amplify crossover and near-rail distortion.

• Most-likely causes: output current limit; near-rail swing; load capacitance adding peaking; CM modulation (FDA).
• Fast checks: reduce swing and see if THD improves sharply; raise supply (if allowed) and see if knee moves; add/remove Cload to see sensitivity.
• Fix + verify: increase headroom, reduce load, or add buffering; re-run THD vs swing vs load to confirm knee shift.

Data fields

Signals: sine · Knobs: load R/C, swing, supply · Readouts: THD, H2/H3, SFDR, knee amplitude

Why does inverting drive often pass SAR settling more easily than non-inverting buffering?

Inverting drive can present a more controlled effective source impedance to the sampling network and better isolate input capacitance interactions, improving acquisition recovery.

• Most-likely causes: non-inverting output node sees stronger C interaction; inverting path shapes impedance and reduces kickback impact.
• Fast checks: compare settling with the same RC target; swap to inverting and keep the same bandwidth; compare step overshoot and settle.
• Fix + verify: choose the topology that meets settling margin under worst-case Cin/load; verify across acquisition window limits.

Data fields

Signals: step · Knobs: topology (inv/non-inv), R/C, Cin · Readouts: settling-to-band, overshoot, ringing cycles

Large overshoot on a DAC output: is it caused by the filter or by an unstable buffer?

If overshoot changes strongly with load C or probe/cable parasitics, it is usually buffer stability/damping; if overshoot is consistent but settling-to-band is long, group delay/tails from the filter may dominate.

• Most-likely causes: output-node underdamping; filter Q too high; load capacitance interaction; insufficient Riso.
• Fast checks: bypass filter and compare; add small Riso and compare; change load C and observe whether overshoot scales.
• Fix + verify: stabilize/damp first, then optimize filter; verify both overshoot and time-to-band with the same step plan.

Data fields

Signals: DAC step · Knobs: filter bypass, Riso, load C, cable · Readouts: overshoot, ringing cycles, settling-to-band

Why does the response change when a scope probe is connected, and how can measurement-induced issues be avoided?

A probe adds capacitance and a return-path loop; it can introduce a new pole/zero pair or excite ringing, especially at high-impedance or high-speed nodes.

• Most-likely causes: probe capacitance; long ground lead inductance; probing at the wrong node (high impedance).
• Fast checks: use a ground spring; compare 10× vs active probe; move probe point closer to the driver output pin; enable/disable bandwidth limit to identify HF artifacts.
• Fix + verify: standardize a probing method and log it; confirm results are consistent across repeated connections.

Data fields

Signals: step · Knobs: probe type/mode, ground method, node location · Readouts: overshoot, ringing, measured oscillation frequency

What is the minimum test sequence to distinguish “low phase margin” from “too much load capacitance”?

Run a step test with a controlled baseline, then add capacitance in known increments; if behavior changes sharply with small C additions, C-load sensitivity dominates; if instability persists even at baseline, phase margin is insufficient.

• Most-likely causes: insufficient loop margin; C-load pole at the output node; peaking from filter network.
• Fast checks: baseline (no filter/ADC) → add C steps → add filter → add ADC network; keep probe method constant.
• Fix + verify: add Riso/snubber for C sensitivity; reshape feedback/noise gain for margin; regress the same sequence.

Data fields

Signals: step · Knobs: added C steps, Riso, filter, ADC network · Readouts: overshoot, ringing cycles, settling-to-band

In a noise budget, which should be prioritized: 0.1–10 Hz noise or wideband noise?

Prioritize the noise region that matches the effective measurement bandwidth: wideband noise dominates for higher bandwidth or lightly averaged systems, while 0.1–10 Hz noise dominates for slow, heavily averaged, DC-like measurements.

• Most-likely causes of “no improvement”: ADC input noise dominates; bandwidth definition is wrong; filtering introduces peaking.
• Fast checks: lock the true BW (analog + digital); change averaging/decimation and observe RMS scaling; compare with/without the analog filter.
• Fix + verify: align BW and averaging to the target; confirm RMS noise scales predictably and ENOB delta is explainable.

Data fields

Signals: noise · Knobs: BW (analog+digital), averaging/decimation · Readouts: RMS noise, noise vs averaging slope, ENOB delta

In differential chains, what visible symptoms can common-mode (CM) drift create?

CM drift can reduce headroom, shift the linear window, and modulate distortion; symptoms include earlier clipping, rising even-order distortion, shifting THD knees, and load-dependent SFDR changes.

• Most-likely causes: VOCM source loading; CM loop interaction with the filter; supply/reference drift; multi-channel CM coupling.
• Fast checks: record CM node under dynamic operation; swap VOCM source/buffer and compare; change load and see if CM ripple changes.
• Fix + verify: buffer and decouple VOCM properly; verify CM error stays in window and THD/SFDR knees stop moving.

Data fields

Signals: sine + DC · Knobs: VOCM source, channel count, filter, load · Readouts: CM error/ripple, THD (even-order), SFDR, clip flags