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Clock & Jitter Design Guide for High-Speed Serial I/O

Clock & Jitter Design Guide for High-Speed Serial I/O

← Back to: USB / PCIe / HDMI / MIPI — High-Speed I/O Index

Core idea
Clock & jitter are not “mystical” problems: they are budgetable, locatable, and verifiable. This page provides a practical path to decide whether the bottleneck is reference/distribution & power, channel ISI, or training policy—then pick the right lever: cleanup (retimer) or boost (redriver), with clear pass/fail gates.

H2-1. Positioning & Outcomes

What this page is for

Turn clock/jitter from “mysterious” into an engineering workflow that is budgetable, diagnosable, and acceptance-ready across high-speed serial I/O.

Scope contract (anti-overlap guard)
Covers
  • Clock quality and jitter entry points that reduce eye/margin and raise error rate.
  • Practical jitter taxonomy and measurement definitions for consistent budgeting and validation.
  • Decision logic: when to use retimers (re-timing/cleanup) vs redrivers (channel boost).
  • Verification gates: what to measure, how to correlate, and how to define pass criteria (threshold placeholders).
Does NOT cover
  • Protocol-specific CTS/requirements or numeric masks/templates (handled in protocol pages).
  • Protocol state machines or training details (USB/PCIe/HDMI/MIPI-specific behavior is out-of-scope here).
  • Deep PLL loop derivations or academic oscillator modeling (only engineering-relevant knobs are used).
  • Full power-tree design; only jitter-sensitive power entry points and isolation hooks are included.
Symptom → first check → where to go
Goal: make the “first cut” in 5–15 minutes before changing hardware.
Symptom (what shows up) Likely domain First check (fast) Where to go (this page)
Eye looks “open”, but errors happen under heavy traffic Measurement / power-induced jitter Correlate error counters with load/temperature; check ref clock stability under load H2-2 (taxonomy) → H2-10 (measurement)
Stable with short cable; fails with dock/long cable Channel loss vs clock margin Decide dominant impairment: loss/ISI (needs EQ/boost) vs clock/jitter (needs cleanup) H2-2 → H2-7/8 (retimer vs redriver)
Link trains sometimes, fails sometimes (same hardware) Clock stability / policy mismatch Check reference clock quality + distribution; verify training knobs vs static presets H2-6 (clean refs) → H2-9 (EQ/training alignment)
Errors appear only at hot/cold corners Oscillator drift / jitter sensitivity Check ref frequency accuracy/stability; observe jitter change with temperature sweep H2-2 → H2-4 (budget) → H2-10 (validation)
Redriver/retimer change makes link “worse” Wrong lever for dominant impairment Check if the issue is clock-dominant (needs cleanup) or ISI/loss-dominant (needs boost/EQ) H2-2 → H2-7 (retimer) / H2-8 (redriver)
Notes: “Looks good” is not a pass. A pass requires a defined metric, controlled setup, threshold, and correlation against stress (load/temperature/cable).
Diagram — Clock/Jitter → Link Margin → BER (cause chain)
Noise → Clock/Data Path → Metrics Noise sources Clock / data path Metrics Ref clock noise Power noise → PLL/VCO Crosstalk / EMI Connector / return Source Buffer / Fanout Mux / Routing Retimer (cleanup) RX CDR Eye width/height Jitter (RMS / p-p) Margin BER / error counters Rule: diagnose dominant impairment (clock vs channel vs measurement) before changing hardware.

H2-2. Jitter Taxonomy That Engineers Actually Use

Minimal vocabulary (the only terms used for budgeting/acceptance)

A practical jitter workflow needs a small, consistent vocabulary: RJ (random), DJ (deterministic), PJ (periodic), ISI (channel-induced data dependence), and TJ@BER (total jitter at a stated error probability).

How each component harms margin and error rate (engineering view)
  • RJ spreads crossings in an unbounded statistical tail; it dominates very-low-BER targets and is sensitive to noise floors.
  • DJ is bounded and repeatable; it collapses eye width in a structured way (often linked to data patterns, duty distortion, or asymmetry).
  • PJ is sinusoidal/tonal modulation; it creates “beating” failure modes where some stress conditions look fine while others fail.
  • ISI is channel memory (loss/reflections/crosstalk); it turns data patterns into timing shifts and can be amplified by aggressive EQ.
  • TJ@BER is meaningful only when the BER point and the measurement definition are explicitly stated.
Term mapping (definition → measurement → first lever)
RJ
Random jitter (noise-floor driven)
  • Typical sources: oscillator/PLL noise floor, power noise coupling, broadband EMI.
  • How to measure: integrated jitter from phase-noise (ref clock) or time-interval error statistics (data).
  • Dominant signature: distribution widens with longer observation; tails matter at low BER.
  • Typical symptom: “Everything looks okay” but error rate refuses to drop under stress.
  • First lever: reduce noise floor (clean ref, isolate supplies, improve grounding/shielding).
DJ
Deterministic jitter (bounded, repeatable)
  • Typical sources: duty-cycle distortion, asymmetry, data-dependent crossing shifts.
  • How to measure: histogram shows bounded shoulders; decomposition tools reveal pattern linkage.
  • Dominant signature: repeatable width collapse at specific patterns/conditions.
  • Typical symptom: errors cluster with certain traffic/patterns rather than uniform randomness.
  • First lever: fix asymmetry, reduce pattern sensitivity, verify equalization/presets alignment.
PJ
Periodic jitter (tonal modulation)
  • Typical sources: switching regulators, spread-spectrum interactions, clock spurs, periodic aggressors.
  • How to measure: phase-noise spurs / jitter spectrum; time-domain shows periodic wandering.
  • Dominant signature: failures depend on specific stress states (load, cable, EMI environment).
  • Typical symptom: “passes sometimes” across seemingly identical test runs.
  • First lever: remove/relocate spurs (power filtering, clock routing isolation, spur-aware clocking plan).
ISI
Inter-symbol interference (channel memory)
  • Typical sources: insertion loss, reflections/return discontinuities, crosstalk, connectors/cables.
  • How to measure: eye closure correlates with channel loss/return; pattern sensitivity is strong.
  • Dominant signature: “short works, long fails” and EQ changes have large effects.
  • Typical symptom: improvement with proper EQ/retimer placement, degradation with over-EQ.
  • First lever: fix channel + correct EQ/training; use boost/retiming based on dominant impairment.
TJ@BER
Total jitter at a stated BER
  • Meaning: a scalar summary used for budgeting only when the BER point and method are explicit.
  • How to measure: define BER target, observation window, decomposition method, and instrument setup.
  • Dominant signature: two “TJ” numbers can disagree if setup/definitions differ.
  • Typical symptom: teams argue about “good/bad” because metric definitions are not aligned.
  • First lever: lock metric definitions before tuning; then allocate/measure/close the budget.
Measurement gates (write these down before comparing numbers)
  • Metric definition: RMS vs p-p, TIE method, decomposition options, BER point for TJ@BER.
  • Observation window: record length, histogram confidence, spur visibility for periodic effects.
  • Instrument chain: timebase quality, triggering method, probe loading, bandwidth/filter settings.
  • Stress controls: fixed temperature/load/cable state; correlate errors with environmental changes.
  • Pass criteria placeholder: define thresholds as X/Y/N and keep them consistent across builds.
Diagram — Jitter composition and eye-width closure
RJ / DJ / PJ / ISI → TJ@BER → less eye width → less margin Jitter composition RJ DJ PJ ISI TJ@BER Eye width More TJ@BER → narrower usable window Gate: compare jitter numbers only when definitions + setup + stress conditions match.

H2-3. Where Jitter Enters a High-Speed Link

Goal

Jitter entry points are ranked by controllability and observability to accelerate root-cause isolation. The workflow prioritizes quick checks (5–15 minutes) before major rework.

Ranking principle (first cut)
  • Controllability: can a small, safe change reliably shift margin/error rate?
  • Observability: can a simple measurement show a consistent before/after delta?
  • Propagation path: does the impairment hit the ref clock, PLL/VCO, crossing threshold, or channel memory?
  • Side effects: does the “fix” introduce noise amplification, training instability, or thermal load?
Entry-point checklist (entry → affects → fastest check → fastest fix)
Entry (ranked) Affects Dominant signature Fastest check (5–15 min) Fastest fix Verification gate (X/Y/N)
1) Reference clock path
(XO/TCXO/OCXO → buffer/fanout → routing) 		PLL input, CDR tracking, system timing margin “Good oscillator” yet unstable system; changes track distribution or load Check ref quality at the consumer pin (not only at source); correlate errors with ref activity / temperature Reduce additive jitter (buffer choice, isolation), improve routing/return, stabilize ref supply Error rate ≤ X over Y minutes across temps; ref jitter improves by N%
2) Power-induced jitter
(PLL/VCO supply noise, buffer PSRR, ground bounce) 		RJ/PJ floor, crossing wander under load, intermittent training Fails mainly under heavy traffic / load; “looks okay” at light load Correlate errors with power events; observe spur/noise coupling; compare idle vs stress jitter Improve decoupling/partitioning; isolate PLL/buffer rails; reduce ground impedance Under stress, jitter delta ≤ X; error bursts disappear for Y cycles
3) Data-dependent jitter
(ISI, reflections, EQ side effects) 		Eye closure tied to patterns/length; sensitivity to EQ presets Short works, long fails; knob changes swing outcomes strongly A/B: short vs long path; step EQ one notch; watch margin/error response Fix channel discontinuities; align EQ/training with policy; select boost/retiming by dominance Margin improves by ≥ X dB/UI; errors ≤ Y over window
4) Crosstalk-induced jitter
(aggressor → threshold crossing wander) 		Threshold timing wander, burst errors with external activity Errors correlate with neighbor port, cable motion, or switching events Toggle aggressor on/off; log correlation; change routing/cable posture and observe deltas Increase spacing/shielding; improve return continuity; reduce common-mode conversion Correlation coefficient ≤ X; burst rate ≤ Y per hour
Practical rule: start with entries that are both easy to control and easy to observe, then move to channel/EMI work that has higher side effects.
Diagram — System layers and jitter entry points
Physical layers + functional path (where jitter enters) Physical layers Package Board Connector Cable EMI Functional path Ref source Buffer / fanout PLL / TX Channel RX CDR Retimer Ref entry Power entry ISI entry XTALK Work order: definition/setup → ref/distribution → power coupling → channel/ISI → crosstalk/EMI.

H2-4. Practical Jitter Budgeting

Objective

Convert specification-level jitter requirements into a system acceptance margin by enforcing a closed loop: define → allocate → measure → converge. No numeric comparison is valid without consistent definitions and setup.

Step 1 — Define target (lock the terms)
  • Metric definition: RMS vs p-p, TIE method, TJ@BER definition.
  • Stress state: temperature, load, cable/fixture condition, traffic pattern class.
  • Acceptance placeholder: BER ≤ X over Y minutes, margin ≥ N.
Step 2 — Allocate budget (make each item measurable)
  • Partition into Ref clock, TX PLL, Channel-induced, RX residual, and measurement error.
  • Allocate by controllability: reserve more headroom for items that drift with manufacturing and environment.
  • Guard band is mandatory: it protects against corner drift and measurement uncertainty (placeholders: X% or Y absolute).
Step 3 — Measure consistently (no setup drift)
  • Control timebase/trigger/probe loading and record settings with the data.
  • Use the same observation window and stress state when comparing builds.
  • Log correlation: margin/error counters vs temperature/load/cable state.
Step 4 — Converge (priority tree)
  • 1) Metric/setup mismatch (fix definitions before tuning hardware).
  • 2) Ref clock & distribution (highest controllability).
  • 3) Power-induced coupling (load/temperature sensitivity).
  • 4) Channel/ISI/EQ (higher side effects; verify training/presets alignment).
  • 5) Crosstalk/EMI (solve via correlation + physical mitigation).
Budget template (copy/paste for reviews)
Budget item Allocated Measured Margin Gate (X/Y/N) Action if fail
Ref clock @ consumer pin X Y (X−Y) ≤ N Reduce additive jitter; isolate supply; reroute return
TX PLL contribution X Y (X−Y) ≤ N Improve rail noise; verify reference coupling; validate load sensitivity
Channel-induced (ISI / reflections) X Y (X−Y) ≤ N Fix discontinuities; align EQ/training; choose boost vs cleanup by dominance
RX residual (CDR tracking limit) X Y (X−Y) ≤ N Insert retimer if clock-dominant; verify cleanup vs latency/power
Measurement error (instrument + setup) X Y (X−Y) ≤ N Lock setup; calibrate; document timebase/trigger/probe and window
Guard band is not optional. It absorbs corner drift (temperature/manufacturing) and measurement uncertainty so acceptance does not rely on luck.
Diagram — Budget funnel (requirements → allocation → measurement → margin)
Budget funnel: define → allocate → measure → converge 1) Requirements / Target Definition locked 2) Allocation / Budget table Guard band 3) Measurement control Setup fixed 4) Margin & Gate Pass / Fail Priority 1) Setup 2) Ref 3) Power 4) Channel Gate rule: no tuning is accepted without before/after metrics under the same definitions and stress.

H2-5. Clocking Architectures Across Protocols

Scope

This section covers clocking architecture types and their engineering tradeoffs. It intentionally avoids protocol-specific numbers and compliance details, focusing on: who owns the sampling clock, how timing is transported, and where jitter is filtered or amplified.

Architecture primitives (cross-protocol)
  • Clock ownership: transmitter-owned, receiver-owned, or shared reference.
  • Clock transport: embedded in data, forwarded alongside data, or supplied as an external reference.
  • Sampling authority: recovered clock (CDR) sets the sampling instant vs. forwarded/reference clock defines the sampling window.
  • Filtering locus: jitter shaping happens at TX PLL, along distribution, inside a retimer, or within RX CDR tracking.
Architecture comparison table
Architecture Ref dependency Jitter transfer path Typical pitfalls Best-fit scenarios First sanity check
Embedded clock
(clock in data) 		Moderate: external ref helps stability, but sampling is primarily recovered at RX TX PLL → channel memory/ISI → RX CDR tracking → sampling instant “Good oscillator” yet unstable link; training/EQ changes swing outcomes; stress-only failures High-speed serial links where RX must recover timing from the stream Compare margin/error under short vs long channel; check correlation with stress state and EQ presets
Forwarded clock
(source-synchronous) 		High: sampling depends on clock/data alignment delivered to RX Clock + data path matching → sampling window; coupling affects both edges and phase relationship Skew drift between clock and data; return discontinuity; aggressor coupling into clock net Short-reach links where deterministic sampling is preferred over recovery uncertainty Verify clock↔data skew stability across temperature and load; confirm return path continuity
External reference + recovered clock
(ref sets framework, CDR samples) 		Variable: ref can be common-related or independent; CDR closes local sampling loop Ref distribution sets long-term stability; RX CDR filters/tracks short-term components Wrong assumption about ref relationship; under-budgeted distribution additive jitter; measurement setup mismatch Systems that need timing coherence across endpoints while keeping RX sampling robust Identify whether endpoints are common-related or independent; validate ref at consumer pins; check CDR tracking behavior under stress
Practical boundary: architecture selection is driven by clock ownership, transport method, and the dominant jitter path—not by protocol names.
Diagram — Three clocking architectures (side-by-side)
Clock transport + sampling authority (protocol-agnostic) Embedded Forwarded External ref + CDR TX LINK RX TX LINK RX TX LINK RX Ref TX PLL Data stream CDR Sampler clock in data Ref TX Data FWD CLK Align Sampler clock + data delivered Ext Ref TX PLL Data stream CDR Sampler ref sets framework Key view: who defines sampling time, and where jitter is filtered (PLL / retimer / CDR).

H2-6. Clean External References

Objective

“Clean reference” must be defined at the consumer pin, not only at the oscillator output. This section converts a clean-ref claim into reviewable engineering actions: source selection, distribution isolation, layout hooks, power hooks, and minimum viable measurement.

What “clean” means (engineer-friendly)
  • Spectral cleanliness: low phase-noise and controlled spurs in the bands that matter to sampling recovery.
  • Delivered cleanliness: additive jitter from buffer/mux/fanout and routing is included.
  • Stress robustness: jitter does not degrade sharply with load/temperature changes.
Ref source selection checklist
  • Frequency plan: ref frequency and multiplication path are compatible with consumers.
  • Phase-noise focus: prioritize the offsets that dominate system margin (placeholder: band A/B/C).
  • Drift: temperature drift, aging, and warm-up stability are reviewed for system repeatability.
  • Spurs: spur management is treated as a first-class risk (burst errors can be spur-driven).
Distribution checklist (buffer / fanout / mux)
  • Additive jitter: distribution is budgeted as a non-zero contributor.
  • Isolation: noisy consumers are separated by partitioning or buffering to prevent back-injection.
  • Topology: star vs daisy vs partition is chosen by noise-domain boundaries, not convenience.
  • Reset/enable behavior: distribution switching is checked for transient disturbance.
Layout hooks checklist
  • Return continuity: clock nets avoid broken return paths and plane splits.
  • Ground bounce control: keep clock reference stable; avoid long shared impedance.
  • Crosstalk control: add spacing/guarding; avoid parallel runs with high-slew aggressors.
  • Signaling choice: differential vs single-ended is decided by noise immunity and reference-plane dependence.
Power hooks checklist
  • Spend where it matters: PLL/buffer rails usually dominate jitter sensitivity.
  • Isolation: partition rails and filtering to block noise injection and up-conversion.
  • Decoupling strategy: target impedance control and placement are reviewed (no hand-waving).
Minimum viable measurement (MVM)
  • Two-point rule: measure at source and at the consumer pin.
  • Stress delta: compare idle vs stress (traffic/load/thermal) using the same setup.
  • Setup lock: record bandwidth, coupling, probe/loading, trigger/timebase, and observation window.
  • Gate placeholder: consumer-pin jitter ≤ X, delta under stress ≤ Y, errors ≤ N.
Hard gate

A “clean reference” claim is invalid unless consumer-pin measurements exist and are compared under a controlled, repeatable stress state.

Diagram — Clock tree with jitter add-points (source → distribution → consumers)
Clean ref delivery: source → distribution → consumer pins Clock chain Consumers (noise domains) Ref source Cleaner / PLL Buffer Fanout Mux Route Add jitter Add jitter Add jitter Power Power Power Power Quiet domain Noisy domain Consumer A Consumer B Consumer C Consumer D TP Consumer pin Return XTALK Review rule: budget distribution additive jitter and validate at consumer pins under stress.

H2-7. Retimers as Jitter Cleaners

Scope

A retimer can reduce sensitivity to certain timing impairments by rebuilding a timing domain and re-sampling the data stream. It is not simply “stronger equalization”. This section defines when re-timing delivers real cleanup and when it cannot.

Retimer vs. “just EQ” (core distinction)
Retimer (re-timing)
  • Builds a new clocking domain internally (CDR/PLL behavior).
  • Re-samples and regenerates edges in that domain.
  • Cleanup effectiveness depends on tracking behavior, reference coupling, power noise, and input quality.
Equalization only
  • Shapes frequency response or gain of the waveform.
  • Does not rebuild the sampling clock domain.
  • May amplify noise and crosstalk; “better looking” waveforms do not guarantee fewer errors.
Cleanup intuition (concept level)
  • Slow wander: behaves like long-term phase/frequency drift; retimer behavior is tied to tracking and reference coupling.
  • Fast random components: appear as short-term timing noise; retimer can reduce sensitivity only if internal noise and power integrity do not dominate.
  • Rule: “Cleanup” must be verified using a consistent measurement and stress state—not assumed from device class.
Why a retimer can make things worse (common root causes)
  1. Training / configuration mismatch: auto behavior and static presets fight, creating unstable operating points.
  2. Over-peaking / aggressive equalization: noise and crosstalk are boosted along with the desired signal.
  3. Reference coupling: the rebuilt timing domain inherits issues from an unclean or poorly delivered reference.
  4. Power noise / thermal drift: supply ripple and ground bounce degrade internal clocking behavior under load and temperature.
What a retimer can / cannot solve (executive table)
Problem signature Dominant domain Retimer helps? Why First check Pass criteria (X/Y/N)
Short channel OK, long channel fails Channel loss / ISI dominates Often YES Re-timing reduces sensitivity to accumulated timing uncertainty across the long channel Measure margin/error vs channel length; compare before/after insertion under identical stress Margin ≥ Y, error ≤ N, jitter delta ≤ X
Eye improves but errors do not Reference / power / measurement mismatch Uncertain Physical waveform gains may not translate to sampling robustness if timing domain or counters are mis-accounted Verify consumer-pin reference quality; confirm identical stress state and counter definition Before/after use same setup; errors ≤ N over T
Only fails under load or high temperature Power integrity / thermal coupling Often NO (alone) Retimer cannot compensate for supply noise and thermal drift that dominates internal timing behavior Correlate errors with rail ripple/temperature; repeat with controlled power and cooling Error ≤ N at worst-case stress; delta ≤ X
Gets worse after inserting retimer Over-peaking / training mismatch / ref coupling / power noise Investigate Internal timing rebuild can amplify weaknesses if operating point is unstable or rails/reference are dirty Reduce EQ aggressiveness; validate ref at consumer pins; audit rails and grounding under stress After tuning: margin ≥ Y, errors ≤ N
Verification metrics (before/after definition)
  • Physical: jitter trend, eye opening (use consistent bandwidth/window and identical probing).
  • Link: margin trend (same stress, same presets; no counter redefinition).
  • System: error counters and service stability (same traffic pattern and duration).
  • Pass gate placeholders: jitter ≤ X, margin ≥ Y, errors ≤ N over T.
Diagram — Before/After retiming insertion (long channel)
Retimer effect: re-timing (new domain) vs channel-only accumulation Before After Source Long channel Loss / ISI Sink Small margin Source Channel Retimer CDR Re-sample New timing domain Channel Sink Margin improves if root cause matches Cleanup

H2-8. Redrivers: Channel Boost Without Cleanup

Scope

A redriver primarily provides channel boost (gain/CTLE-like shaping) and does not rebuild the timing domain. It can improve loss-limited channels but may worsen jitter-limited systems by amplifying noise and crosstalk.

CTLE / linear EQ side effects (why “boost” can backfire)
  • Noise amplification: high-frequency boost can raise noise floor at the sampling threshold.
  • Crosstalk sensitivity: steeper edges and higher gain can magnify aggressor coupling.
  • Metric mismatch risk: an eye that “looks larger” may not translate into fewer errors under stress.
Redriver decision workflow (symptom → measure → decide → accept)
Step Input Observation Decision Acceptance gate (X/Y/N)
1. Classify symptom “Short OK, long fails”
“Extra connector breaks stability”
“Stress-only errors” 		Symptoms hint whether the channel is loss-limited or timing-noise-limited Proceed to measurement Baseline errors ≤ N over T
2. Measure trends Loss trend
Jitter trend
Margin trend 		Loss-dominant channels often benefit from boost; jitter-dominant systems often do not If loss-dominant → candidate
If jitter-dominant → high risk 		Margin ≥ Y at stress; jitter delta ≤ X
3. Place intentionally Near source / mid / near sink Placement changes what is boosted (pre-channel vs mid-channel vs end correction) Choose by dominant impairment location Errors ≤ N after placement change
4. Accept only if system metrics improve Before/after A/B
Same stress 		Eye alone is insufficient; use error and margin consistency Accept only with consistent gains Margin ≥ Y, errors ≤ N, stable over T
Practical boundary: redrivers help when loss is dominant; they are risky when timing noise dominates.
Placement principles (connector / mux proximity)
  • Near connector: sees the worst waveform and can compensate loss, but is exposed to harsh noise and transient environments.
  • Near source: acts like pre-boost; may not fix impairments accumulated later in the channel.
  • Near sink: improves end-of-channel amplitude, but can amplify local noise coupling near the receiver.
Diagram — Redriver placement points (boost only, no cleanup)
Redriver: channel boost (CTLE) — no timing-domain rebuild Source Sink Loss XTALK Loss Near source Mid-channel Near sink Redriver Redriver Redriver CTLE CTLE CTLE NO CLEANUP Acceptance must use margin + error counters under the same stress state (not eye shape alone).

H2-9. EQ & Training vs Static Settings

Scope

Cross-protocol rule: automatic training and static presets must optimize the same objective. If policy and overrides disagree, the system can converge to a point that looks aggressive but is operationally fragile.

The conflict model (why “cleanup” can be canceled)
  • Training loop: measure margin/quality, adjust, and converge.
  • Static overrides: lock or bias parameters toward a preferred operating point.
  • Mismatch: training is forced to converge within the wrong constraints, causing non-convergence or a brittle stable point.
Common root-cause categories (training fails or never truly stabilizes)
A. Clock quality
  • Signature: drift, retries, and “works once” behavior.
  • First check: reference delivery at consumer points and supply-noise trend.
  • Fix direction: stabilize reference coupling and rails before tuning aggressiveness.
B. Channel too lossy
  • Signature: short channel works, long channel cannot converge.
  • First check: margin trend vs channel length/topology.
  • Fix direction: move back into a trainable envelope (loss budget) before knob tuning.
C. Wrong initial condition
  • Signature: converges, but to a poor point; “stronger” presets look worse.
  • First check: compare mild/default/aggressive trends under identical stress.
  • Fix direction: reduce aggressiveness to regain repeatable convergence.
D. Policy mismatch (FW vs HW)
  • Signature: “passes” yet becomes fragile under temperature/load/EMI shifts.
  • First check: stress sensitivity of margin and error counters.
  • Fix direction: align objective functions and acceptance gates across layers.
Static override risk (aggressive-looking but fragile)
  • Noise and crosstalk amplification: stronger EQ can raise sensitivity at threshold crossings.
  • Edge-of-stability operating point: temperature and supply variation can push the system out of the narrow stable region.
  • Poor repeatability: the same environment can converge differently when overrides constrain the search space.
Alignment checklist (FW knobs vs HW knobs)
Layer Knob group Lock / allow Alignment rule Evidence required
FW Training policy (objective, retry, stop condition) Define + document Same objective function as acceptance gate; avoid “optimize eye only” Convergence repeatability across power/temperature states
FW Static preset / override limits Prefer bounded Do not force aggressiveness beyond trainable region Margin and error trend improve under worst-case stress
HW EQ mode / strength limits Constrain Keep noise and crosstalk amplification within acceptable bounds Jitter delta ≤ X, errors ≤ N
HW Reference delivery / power mode Must satisfy Stable reference and rails are prerequisites for any tuning strategy Stability at worst-case load/temperature; margin ≥ Y
Verification gate (every knob change requires these 3 re-tests)
  1. Margin trend: margin ≥ Y with stable spread across time.
  2. Error trend: errors ≤ N over T at stress.
  3. Stress sensitivity: delta ≤ X when temperature/load/noise conditions change.
Diagram — Training loop with FW/HW knobs (same objective)
Training + Static alignment: same objective function, stable convergence SAME OBJECTIVE FUNCTION FW knobs Policy Preset bounds Retry rules Lock / allow Logging HW knobs EQ mode Ref path Power mode Limits Board coupling Training loop Measure Adjust Re-measure Converge Override risk if misaligned

H2-10. Measurement & Validation

Scope

Measurement quality is part of the system. Budget closure, retiming gains, and training alignment require repeatable and layer-consistent definitions from lab bring-up through production validation.

Measurement targets (layered definitions)
Reference layer
  • Phase noise proxy and integrated jitter trend
  • Reference delivery quality at the consumer pins
Link layer
  • Eye opening trend and margin proxy under the same stress state
  • Before/after comparisons with identical setup and windows
System layer
  • BER proxy and error-counter stability across time
  • Service-level stability under temperature/load/noise changes
Instrument-chain error sources (common and avoidable)
  • Probe/fixture loading: measurement hardware can change the channel and bias results.
  • Trigger and timebase quality: trigger jitter and reference instability leak into measured timing.
  • Bandwidth and window selection: inconsistent bandwidth/window makes results non-comparable.
  • Stress-state mismatch: comparing data under different load/temperature invalidates conclusions.
MVP validation (sanity checks without top-tier instruments)
  1. One-knob A/B: change only one variable (channel length, load, cooling, or supply filtering) and record trends.
  2. Stress sweep: temperature/load/noise sweeps reveal dominant failure drivers.
  3. Three-metric sync: log margin proxy, error counters, and a reference-quality proxy on the same timeline.
  4. Repeatability check: confirm the same setup converges to the same result across repeated runs.
Measurement checklist (setup / calibration / pass criteria)
Item Setup requirement Common pitfall Sanity check Pass criteria (X/Y/N)
Time window Fixed duration T for all runs Comparing different windows Repeat run-to-run; verify spread is stable Spread ≤ X
Probe/fixture Known loading; consistent attachment point Loading changes the channel Compare with/without fixture; check trend consistency Trend preserved; delta ≤ X
Trigger/timebase Same reference source and trigger method across runs Trigger jitter contaminates timing results Re-run with a different trigger path; compare stability Measurement stability ≥ Y
Bandwidth/window Fixed bandwidth and analysis window definitions Results become incomparable A/B with one controlled change; keep definitions fixed Differences explainable; delta ≤ X
Pass gate Fixed acceptance gates for production “Looks good” without system metrics Validate with margin + counters under stress jitter ≤ X, margin ≥ Y, errors ≤ N
Correlation template (errors vs jitter / temperature / load)
Timestamp Stress knob Ref-quality proxy Margin proxy Error counters Notes
t0 Temperature proxy A proxy B count C state
t1 Load proxy A proxy B count C state
Goal: identify dominant drivers by time-aligned trends rather than single snapshots.
Diagram — Measurement setup (DUT → fixture → instruments → logger)
Measurement setup: consistent chain, consistent stress, repeatable gates DUT Clock + Data Breakout / Fixture Probe points Instruments Scope Spectrum / PN BERT / Analyzer Data logger Time-aligned metrics Stress knobs (controlled sweeps) Temp Load Supply noise Same stress state for before/after comparisons Data Metrics Pass gate: jitter ≤ X, margin ≥ Y, errors ≤ N

H2-11. Engineering Checklist (Design → Bring-up → Production)

Outcome
A project-usable checklist that turns clock/jitter from “mysterious” into budgetable, debuggable, and auditable. Each gate is written as Why / How / Pass criteria so reviews, bring-up, and production can share one acceptance language.
Scope guard: protocol-specific registers and numeric limits are intentionally omitted here. Keep Pass criteria as placeholders (X/Y/N/T) and fill them per product/program.
A) Design review gates (schematic / layout / PI / return path)
Goal: eliminate dominant jitter injection paths before PCB release. These gates catch the “silent killers”: reference contamination, supply modulation, and return-path discontinuities.
Clock source & distribution gates
G1 · Reference path ownership
Why: unknown coupling points make every “fix” non-repeatable.
How: draw the full clock tree: source → buffer/mux → fanout → consumers; mark every connector/via-field crossing and every enable pin.
Pass criteria: tree is single-source-of-truth; every add-point has a measurable proxy (X).
G2 · Fanout topology sanity
Why: “one-to-many” often fails by skew, enable glitches, or return-path sharing.
How: prefer a clean trunk then short local branches; avoid long daisy-chains of buffers unless skew is explicitly closed.
Pass criteria: output-to-output skew ≤ X; enable/disable is glitch-free under reset sequencing.
G3 · Edge-rate control vs crosstalk
Why: overly fast edges increase aggressor coupling → threshold wander (jitter).
How: keep clock traces short; isolate from high-swing aggressors; keep reference plane continuous; do not share tight bundles with high-speed data.
Pass criteria: clock coupling risk is reviewed; worst-case aggressor scenario has margin ≥ Y.
Power integrity gates (PLL/VCO/buffer rails)
G4 · Rail partition & “quiet island”
Why: supply noise becomes phase modulation; it looks like random jitter in the eye.
How: separate sensitive rails; keep return loops compact; ensure no shared high di/dt path from load-switches/DC-DC into PLL/buffer rails.
Pass criteria: “quiet island” defined; worst-case load step does not violate noise proxy ≤ X.
G5 · Decoupling placement realism
Why: “correct values” fail if loop inductance dominates.
How: place high-frequency caps at pins with direct via-to-plane; avoid long dog-bones; keep the return via adjacent.
Pass criteria: smallest loop confirmed by layout review; decap loop ESL budget ≤ X.
Return path / grounding / shielding gates
G6 · Continuous return for high-speed & ref
Why: return discontinuities create mode conversion and time-varying threshold crossings.
How: avoid splits under high-speed lanes and clock paths; ensure stitching vias across plane transitions; keep connector reference consistent.
Pass criteria: no critical lane crosses plane gaps; plane transition stitching meets rule ≥ Y.
G7 · Shield bond strategy
Why: inconsistent shield bonds can amplify EMI and inject jitter through common-mode paths.
How: define 360° bond points, chassis coupling, and where “pigtail” is forbidden; keep bond inductance controlled.
Pass criteria: bond locations and method are explicit; EMI stress does not reduce margin below X.
Thermal & derating gates
G8 · Hotspot to jitter sensitivity
Why: temperature shifts CDR/PLL behavior and moves the “stable point”.
How: map thermal hotspots for clock tree + retimers/redrivers; ensure copper/airflow paths; include derating policy for worst case ambient.
Pass criteria: stress delta (temperature sweep) keeps margin change Δ ≤ X.
B) Bring-up sequence (Ref → Link → Training → Stress)
The sequence prevents “random tuning”: always establish reference quality first, then confirm the channel envelope, then validate training convergence, and only then run stress/correlation.
Step 1 · Reference sanity
Why: without a clean ref, every downstream improvement is non-deterministic.
How: measure ref at source and at key consumers; log ref-proxy vs load/temperature.
Pass criteria: ref proxy ≥ Y at all consumers; drift Δ ≤ X over T.
Step 2 · Baseline the channel
Why: distinguish loss-dominated vs jitter-dominated before choosing “boost” or “cleanup”.
How: compare a short “golden” path vs target path; record margin proxy and error counters.
Pass criteria: target path margin proxy ≥ Y or improvement lever is identified.
Step 3 · Training repeatability
Why: a “works once” link is a future field failure.
How: power-cycle and re-train N times; verify convergence stability and preset consistency.
Pass criteria: success rate ≥ Y%; margin variance ≤ X; no oscillatory preset behavior.
Step 4 · Stress + correlation logging
Why: jitter failures often appear only under temperature, load, or EMI events.
How: sweep temperature/load; log {ref proxy, margin proxy, error counters} in one timeline.
Pass criteria: errors ≤ N over T; correlation points to one dominant domain (X).
C) Production screens (presence / proxies / fast correlation)
Production cannot run full lab-grade jitter analysis. The goal is a fast proxy screen that catches missing references, unstable training, and thermal sensitivity.
P1 · Reference presence & distribution
Why: “no ref / wrong ref / weak ref” is a top hidden yield killer.
How: check ref-proxy at key consumers via test points or built-in monitor.
Pass criteria: all consumers detect ref; proxy within X band.
P2 · Training consistency screen
Why: intermittent convergence predicts field flaps.
How: run minimal retrain loop N times; record success and margin proxy trend.
Pass criteria: success rate ≥ Y%; no monotonic degradation across repeats.
P3 · Thermal quick sweep
Why: temperature can turn a passing unit into a marginal one.
How: short hot/cold soak or localized heating; re-check margin proxy and counters.
Pass criteria: margin change Δ ≤ X; errors ≤ N in T.
Diagram · Checklist pipeline (Design → EVT → DVT → PVT)
One acceptance language: Why / How / Pass (X/Y/N) Design Ref + Clock tree PI (PLL rails) Return path EVT Ref sanity Channel baseline Quick fixes DVT Training repeat Thermal sweep EMI stress PVT Fast proxies Yield screen Acceptance Acceptance gates (placeholders): jitter ≤ X · margin ≥ Y · errors ≤ N over T

H2-12. Applications & IC Selection (Logic + Bundles)

Selection goal
Not a part dump. The selection is driven by link shape and the dominant impairment: choose clean ref, insert a retimer (cleanup), or use a redriver (boost), then close the loop with a validation gate (X/Y/N/T).
Scope guard: protocol-specific tuning and register tables belong to their protocol subpages. This section stays cross-protocol and uses part numbers as examples.
A) Applications by link shape (cross-protocol)
Board short reach
Dominant impairment often shifts to reference + PI + crosstalk rather than pure loss. First lever: clean ref and isolate sensitive rails.
Board long reach (multi-connector)
Loss + discontinuities dominate; jitter can be data-dependent (ISI). First lever: decide cleanup (retimer) vs boost (redriver) after baseline comparison.
Cable / dock / external box
More variability (cable tolerance, shield bonding, EMI). If the system is “works on short, fails on long”, default toward retiming/cleanup or a carefully placed redriver, then lock validation gates.
Multi-port fanout
Port-to-port variation usually traces back to clock distribution + PI + skew. First lever: stabilize the ref tree and enforce consistency gates across ports.
High-EMI environment
Common-mode events and shield strategy can dominate “jitter-like” failures. First lever: fix return path and ensure the clock tree is isolated from noisy domains.
B) Select by purpose (with example part numbers)
1) Clock source & distribution (make ref “clean” and keep it clean)
  • Spec focus: phase-noise window, additive jitter, skew, enable behavior, supply sensitivity.
  • Validation gate: consumer-side ref proxy ≥ Y; drift Δ ≤ X over T; skew ≤ X.
  • Example parts: SiTime SiT5356 (Super-TCXO), TI LMK1C1104 (LVCMOS clock buffer), Renesas 5PB1108 (1:8 clock buffer), ADI LTC6957-1 (ultralow additive noise clock buffer).
2) Retimer (cleanup via CDR/PLL domain rebuild)
  • When: long/variable channels where eye closure is not solved by boost alone; need deterministic recovery and better BER margin.
  • Spec focus: retiming behavior, latency, power/thermal headroom, reference coupling policy.
  • Validation gate: before/after: margin ↑, errors ↓, repeatability ↑ (placeholders X/Y/N/T).
  • Example parts: TI DS160PT801 (PCIe 4.0 protocol-aware retimer), TI DS125DF410 (quad-channel retimer with CDR/DFE), TI DS250DF410 (25-Gbps 4-channel retimer), TI DS280DF810 (28-Gbps 8-channel retimer).
3) Redriver (boost without cleanup)
  • When: loss-dominated channels with adequate reference quality; need more eye opening but not full retiming.
  • Spec focus: CTLE/EQ range, noise amplification risk, placement sensitivity, channel symmetry.
  • Validation gate: eye/margin proxy ↑ while error counters do not worsen under stress (X/Y/N/T).
  • Example parts: TI TUSB1046-DCI (10-Gbps linear redriver switch for USB-C Alt-Mode), TI DS160PR810 (16-Gbps 8-channel linear redriver), TI DS80PCI810 (8-Gbps 8-channel redriver), TI SN75LVPE3101 (PCIe 3.0 x1 redriver), TI TDP1204 (HDMI 2.1 redriver), TI TDP142 (DisplayPort 1.4 redriver).
  • Jitter-cleaning example (DP dual-mode path): Parade PS8461 / PS8469 (DP mux/demux with internal retimer for jitter cleaning).
C) Decision matrix (symptom → dominant impairment → best lever → category → validation gate)
Symptom: works on short path, fails on long
Dominant impairment: loss / ISI (data-dependent jitter).
Best lever: retimer if margin collapses nonlinearly; redriver if loss-dominant and ref is clean.
Category: Retimer / Redriver.
Validation gate: margin ↑ by X; errors ≤ N over T; repeatability ≥ Y%.
Symptom: training “sometimes converges”
Dominant impairment: ref quality / policy mismatch / marginal channel.
Best lever: clean ref first; then retimer if the channel is beyond envelope; avoid “strong” static overrides without gates.
Category: Clock tree / Retimer.
Validation gate: converge rate ≥ Y%; preset variance ≤ X; no regression under temperature.
Symptom: passes in lab, fails in EMI/field
Dominant impairment: return path + shield bonding + supply modulation.
Best lever: fix return path/shield strategy; isolate clock rails; only then consider redriver/retimer changes.
Category: Layout/return + Clock tree.
Validation gate: margin drop under EMI ≤ X; error bursts ≤ N over T.
D) Engineering bundles (templates with example part numbers)
Bundle A · Multi-port clock distribution (make ref consistency the “system backbone”)
Use for: multi-port fanout, repeatability issues across ports, “same design but different ports behave differently”.
Template: SiT5356 (ref source) → Renesas 5PB1108 (fanout) → TI LMK1C1104 (local buffer per island).
Acceptance gate: consumer ref proxy ≥ Y; skew ≤ X; port-to-port margin spread ≤ X.
Bundle B · Long/variable channel cleanup (retiming-centric)
Use for: long traces / multiple connectors / external cabling where “boost” stops helping or training becomes fragile.
Template: clean ref chain (e.g., SiT5356 + low-noise distribution) + a retimer stage: DS160PT801 (PCIe protocol-aware) or DS125DF410/DS250DF410 (generic retimers where applicable).
Acceptance gate: before/after margin ↑ by X; errors ≤ N over T; retrain success ≥ Y%.
Bundle C · Loss-dominant reach extension (redriver-centric)
Use for: channels that are stable on a clean ref but need more eye opening; prefer minimal latency and BOM cost.
Template: ref consistency gates + one well-placed redriver near the dominant discontinuity: DS160PR810, DS80PCI810, SN75LVPE3101, TUSB1046-DCI, TDP1204, TDP142 (pick by interface family).
Acceptance gate: margin proxy ↑ by X without noise/crosstalk regression; errors ≤ N under stress.
Diagram · Dominant impairment → Choose lever → Validate (plus Bundles A/B/C)
Dominant impairment? (loss / ref noise / policy mismatch / return path) Clean ref Clock tree + PI Insert retimer Cleanup / re-time Use redriver Boost / CTLE Fix return Shield / GND Validate gates: margin ↑ X · errors ≤ N over T · retrain success ≥ Y% · drift Δ ≤ X Bundle A Ref → Fanout → Local buffer Consistency across ports Bundle B Clean ref + Retimer stage Long / variable channels Bundle C Ref gates + Redriver Loss-dominant extension

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H2-13. FAQs (Clock & Jitter)

FAQ intent
These FAQs close the loop for field debugging and acceptance criteria. Each answer is strictly Likely cause / Quick check / Fix / Pass criteria and stays cross-protocol.
Data structure rule: every Pass criteria includes at least two metrics: (1) link outcome (BER/errors/flaps) + (2) a causal proxy (ref/PI/jitter/margin), with placeholders (X/Y/N/T).
Ref clock spec looks great, but BER is still high — where is the first accounting check?
Likely cause: the oscillator spec is not the bottleneck; distribution/PI injection or channel ISI dominates at the receiver threshold crossing.
Quick check: compare source ref vs consumer-side ref proxy (same setup), and run a short-vs-long channel A/B to see whether errors scale with loss/ISI.
Fix: isolate the clock-rail “quiet island”, shorten/clean the ref path to consumers, then decide cleanup (retimer) vs boost (redriver) based on the A/B dominance result.
Pass criteria: BER ≤ X over T; consumer ref proxy ≥ Y with drift Δ ≤ X (same load/temperature window).
Adding a redriver made the link worse — noise amplification or over-EQ?
Likely cause: redriver EQ boosts both signal and noise/crosstalk; a “stronger” setting can increase effective jitter or shrink margin under real load.
Quick check: sweep EQ in 2–3 coarse steps and log (a) margin proxy and (b) error counters; if higher EQ worsens errors while margin proxy does not improve, noise amplification is dominating.
Fix: move the redriver closer to the dominant discontinuity, reduce EQ, tighten symmetry (diff pair balance), or switch to a retimer if the channel is beyond linear-boost limits.
Pass criteria: error counters ≤ N over T under load profile L; margin proxy ≥ Y with EQ setting locked and repeatability ≥ X%.
Retimer inserted but no improvement — is it ISI-dominant or clock-dominant?
Likely cause: the dominant impairment is not being reset: either ISI is created after the retimer placement, or clock/power coupling limits the retimer’s effective cleanup.
Quick check: measure before/after at three points: pre-retimer, post-retimer, receiver; if improvement appears post-retimer but disappears at receiver, the downstream segment is the real culprit.
Fix: relocate retimer to cut the dominant channel in half, ensure the retimer rail isolation is strong, and verify training/firmware policy is aligned with the new link topology.
Pass criteria: margin proxy improves by ≥ X after insertion and remains ≥ Y at receiver; BER ≤ X over T with retrain success ≥ Y%.
Eye looks open on the scope, but errors happen under load — what is missing?
Likely cause: measurement correlation gap: scope setup hides timebase/trigger limits, while load-dependent PSU noise injects jitter that only appears in-system.
Quick check: log a synchronized timeline: {error counters, margin proxy, ref/rail proxy, temperature, load}. If errors correlate with load steps or rail ripple spikes, the dominant domain is PI-induced jitter.
Fix: strengthen PLL/buffer rail isolation, reduce shared return/ground bounce, and re-validate with the same correlation logging rather than a single “pretty eye” snapshot.
Pass criteria: errors ≤ N over T under load profile L; rail proxy ripple ≤ X and ref proxy drift Δ ≤ X during the same window.
Only fails at cold/hot — oscillator drift, PLL bandwidth corner, or PSRR corner?
Likely cause: temperature shifts the loop behavior and sensitivity: ref stability, PLL bandwidth, and rail rejection can move the link to a marginal operating point.
Quick check: run a temperature sweep and record: (a) ref proxy, (b) margin proxy, (c) error counters. The dominant cause is the one that changes first and consistently precedes errors.
Fix: choose a more stable ref source or tighten distribution isolation, improve rail filtering near PLL/buffer, and add thermal headroom (airflow/copper) for retimers/redrivers if present.
Pass criteria: margin proxy ≥ Y from Tcold to Thot with Δ ≤ X; errors ≤ N over T at both corners.
Errors appear only when a nearby port toggles — crosstalk-induced jitter or ground bounce?
Likely cause: aggressor coupling shifts the victim threshold crossing (crosstalk-induced jitter) or shared return paths create ground bounce that modulates timing.
Quick check: toggle the aggressor in controlled patterns and compare victim margin proxy and error counters; if errors scale with aggressor activity while ref proxy is stable, coupling/return is dominant.
Fix: increase spacing, add stitching vias/return continuity, isolate sensitive clock/SerDes rails from aggressor di/dt, and re-check with the same aggressor pattern.
Pass criteria: error delta between aggressor OFF vs ON ≤ N over T; victim margin proxy drop Δ ≤ X under the aggressor worst-case pattern.
SSC enabled then compliance/margining changes — receiver tolerance or measurement mismatch?
Likely cause: SSC changes spectral distribution; a setup calibrated for non-SSC can report different “jitter” even when link robustness is unchanged.
Quick check: lock the measurement configuration (bandwidth/filters/timebase) and compare link outcome metrics (errors/BER) first; treat instrument-reported changes as secondary unless they correlate with errors.
Fix: ensure measurement settings match the intended SSC mode, validate receiver tolerance via outcome metrics, and keep SSC policy consistent across the system.
Pass criteria: BER ≤ X over T with SSC ON; margin proxy ≥ Y and measurement repeatability within Δ ≤ X (same setup).
Clock fanout added, now random link flaps — additive jitter stacking or isolation issue?
Likely cause: additive jitter from buffers stacks, and/or buffer rail/enable behavior injects noise into the ref domain.
Quick check: measure ref proxy at multiple consumers with fanout enabled vs bypassed; if consumer-side ref proxy varies by port or over time, distribution is the dominant domain.
Fix: simplify topology (short trunk + short branches), improve buffer rail isolation, and enforce skew/enable-glitch gates across ports.
Pass criteria: flap rate ≤ N over T; consumer ref proxy ≥ Y with port-to-port spread ≤ X and drift Δ ≤ X.
Long cable/dock unstable but short cable OK — decide jitter-dominant vs loss-dominant fast
Likely cause: the long path pushes the channel outside the envelope; the dominant impairment can be loss/ISI or added jitter from coupling/PI.
Quick check: keep ref constant and compare (a) margin proxy vs cable length and (b) error counters vs load/temperature; if margin collapses mainly with length, loss/ISI dominates.
Fix: loss-dominant → consider a redriver placed near the dominant discontinuity; jitter/variability-dominant → prefer a retimer and strengthen ref/PI isolation.
Pass criteria: with worst-case cable: errors ≤ N over T; margin proxy ≥ Y and does not degrade by more than Δ ≤ X under load profile L.
After an ESD event, the link becomes more fragile — ref path degradation or return-path change?
Likely cause: latent damage changes impedance/return continuity near the connector, or introduces new coupling into ref/PI domains, reducing margin without an obvious “hard failure”.
Quick check: A/B compare pre- vs post-event units (or ports) under the same stress recipe: log margin proxy + ref proxy + error counters; a consistent shift indicates physical path change.
Fix: inspect/replace connector-side components, restore 360° shielding/return continuity, and re-qualify ref distribution isolation for the affected port.
Pass criteria: post-event unit meets baseline: margin proxy ≥ Y with Δ ≤ XN over T across N retrains.
Training converges sometimes, sometimes not — reference quality or static preset mismatch?
Likely cause: convergence instability: the system oscillates between “almost OK” states due to ref/PI variability or policy mismatch between FW static settings and HW training.
Quick check: run N retrains and record success rate + chosen presets + margin proxy; if presets vary widely between runs at the same condition, the link is operating on a knife-edge.
Fix: lock down ref/PI variability first, then align static overrides with training policy; avoid pushing “strong presets” unless validated by repeatability gates.
Pass criteria: retrain success ≥ Y% over N cycles; preset variance ≤ X states; errors ≤ N over T after convergence.
Multiple retimers cascade — cleanup benefit vs latency/power/thermal side effects?
Likely cause: retimer stages do not provide “free” cleanup: power/thermal corners and reference coupling can re-introduce variability, while added latency tightens system tolerance.
Quick check: validate stage-by-stage: measure margin proxy and error counters after each insertion; monitor temperature and rail proxy at each retimer under sustained traffic.
Fix: keep the minimum number of stages, ensure each stage has strong rail isolation and thermal headroom, and place stages where they split the dominant loss/ISI effectively.
Pass criteria: each stage provides net gain: margin proxy +X vs previous; errors ≤ N over T at Thot; retimer temps ≤ X (proxy/limit).
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