Signal Integrity (SI) for High-Speed Differential Links
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Core idea
Signal Integrity is the discipline of making the differential channel a predictable system so the receiver can decide reliably. The practical approach is to control geometry, return path, and discontinuities, then close the loop with budget → simulation → measurement → sign-off.
Definition & Scope: What SI Means for High-Speed Differential Links
Signal Integrity (SI) is the engineering discipline that keeps the
receiver decision reliable by controlling the channel’s
amplitude margin, timing margin,
and noise margin under real tolerances (layout, materials, connectors, temperature, and manufacturing variation).
Scope guard
In scope (this page)
- Differential geometry: impedance, coupling, length-match, skew.
- Continuous return path: reference planes, splits, stitching strategy.
- Discontinuities: vias, pads, breakouts, connector launches.
- Termination & coupling: reflection control and placement logic.
- Loss/crosstalk budgeting: IL/RL, NEXT/FEXT, mode conversion as SI risk.
- Measurement & sign-off: what to measure first, and what “done” means.
Out of scope (link-only; do not expand here)
- Clock/Jitter root causes (PLL, phase noise, clock-tree details) → sibling page: Clock & Jitter.
- Protocol training internals (state machines, registers, vendor-specific flows) → sibling page: EQ & Training / Compliance hooks.
- EMC/ESD compliance mechanisms (radiation physics, gun setup, certification process) → sibling page: EMC / ESD.
Field symptoms → first SI suspicion (fast triage)
CRC/BER increases (throughput or temperature sensitive)
First suspicion: loss/ISI dominating margin, or crosstalk driven by adjacency / activity.
First tool: VNA (IL/RL) or eye/BER correlation.
Eye closes with ripples / over-undershoot
First suspicion: reflection from discontinuities (vias, launches, connector transitions).
First tool: TDR to locate steps and rank the worst discontinuity.
Link trains intermittently / becomes “fragile”
First suspicion: margin near zero where small variation (cable, connector batch, temperature) pushes the channel over the edge.
First tool: budget sanity check (IL/RL + key discontinuities), then correlate with a known-good cable/connector.
Works on bench, fails in product integration
First suspicion: return path discontinuity (plane splits, poor reference switching), plus new coupling paths (routing density, harness/connector transition).
First tool: layout return-path review + TDR spot checks around launches.
What this page delivers (repeatable SI workflow)
- Define the channel target: topology, max reach, and acceptance metric (threshold X).
- Stackup & impedance plan: reference planes, dielectric, and differential geometry constraints.
- Routing constraints: length-match rules, via limits, reference switching rules, coupling control.
- Budget: insertion/return loss + crosstalk + discontinuity ranking, with margin reserved.
- Model & correlate: use the simplest model that matches reality; close the loop with measurements.
- Sign-off gates: clear pass criteria (threshold X) from prototype to production.
Diagram — Channel as a System (where SI risks live)
Reading tip: treat the channel as a chain of segments and transitions.
Most “mystery” SI failures come from a few dominant discontinuities plus return-path breaks.
Mental Model: The Channel Budget (Amplitude, Timing, Noise)
A high-speed link fails when the remaining margin is smaller than the
combined variation from layout, materials, connectors/cables, temperature, and manufacturing.
Budget thinking forces every design decision to answer one question:
which margin does it protect, and how will it be measured?
1) Amplitude margin (vertical)
- What eats it: insertion loss (IL), reflection loss (RL), and crosstalk-induced effective amplitude reduction.
- What it looks like: smaller eye height, sensitivity to cable length/material, BER rising with temperature or process.
- First measurement: VNA (IL/RL) for channel segments; eye/BER for end-to-end confirmation.
- Pass criteria: eye height ≥ X and IL/RL within budget margin (threshold X).
2) Timing margin (horizontal)
- What eats it: intra-pair skew, lane-to-lane skew, and ISI (often created by loss + reflections).
- What it looks like: narrow eye width, sporadic failures near speed corners, sensitivity to small routing differences.
- First measurement: eye width / bathtub (if available), plus skew checks derived from layout constraints.
- Pass criteria: timing margin ≥ X% UI and skew ≤ X (unit by design rule).
3) Noise margin (interference)
- What eats it: NEXT/FEXT, mode conversion (diff→common), and reference disturbances that couple into the decision threshold.
- What it looks like: errors correlated with neighbor activity, board configuration, or routing density.
- First measurement: crosstalk scan (victim/aggressor), plus targeted review of coupled regions and return-path continuity.
- Pass criteria: crosstalk and mode conversion remain below threshold X with worst-case aggressor patterns.
Parameter → observable → first measurement (mapping)
Loss (IL)
Observable: eye height shrink / reach reduces
First measurement: VNA IL (Nyquist) + end-to-end eye
Pass criteria: IL ≤ X dB (budget), margin reserved ≥ X
First measurement: VNA IL (Nyquist) + end-to-end eye
Pass criteria: IL ≤ X dB (budget), margin reserved ≥ X
Reflection (RL)
Observable: ripples / overshoot / training fragility
First measurement: TDR for location + VNA RL for severity
Pass criteria: RL ≥ X dB (or reflection step ≤ X)
First measurement: TDR for location + VNA RL for severity
Pass criteria: RL ≥ X dB (or reflection step ≤ X)
Skew / mismatch
Observable: narrow eye width / lane-to-lane instability
First measurement: constraint report (ΔL) + targeted time-domain check
Pass criteria: intra-pair skew ≤ X, inter-lane skew ≤ X
First measurement: constraint report (ΔL) + targeted time-domain check
Pass criteria: intra-pair skew ≤ X, inter-lane skew ≤ X
Crosstalk / mode conversion
Observable: errors track aggressor activity / density changes
First measurement: victim/aggressor scan + coupled region audit
Pass criteria: NEXT/FEXT ≤ X, mode conversion ≤ X
First measurement: victim/aggressor scan + coupled region audit
Pass criteria: NEXT/FEXT ≤ X, mode conversion ≤ X
Diagram — Budget view (what consumes margin)
Practical rule: treat every improvement as a margin purchase. If a change cannot be mapped to
a margin (amplitude/timing/noise) and a measurement, it is likely a distraction.
Differential Pair Geometry: Impedance, Coupling, Length-Match & Skew
The goal is to turn “length match” into calculable,
checkable, and sign-off rules:
control Zdiff/Zcm, keep coupling consistent, minimize skew,
and avoid geometry changes that create local discontinuities.
Geometry knobs that move impedance and coupling
- W (trace width) and H (height to reference) primarily set the impedance baseline.
- S (pair spacing) sets differential coupling: tighter S increases coupling but also makes local geometry changes more impactful.
- Microstrip vs stripline: microstrip is more exposed to environment; stripline is more shielded but transition quality becomes critical.
- Consistency beats perfection: stable geometry along the route usually outperforms frequent tiny changes that add discontinuities.
Skew targets (what to match, and why)
Intra-pair skew (P/N within one pair)
Why it matters: directly eats timing margin by misaligning the differential edge at the receiver decision point.
Practical rule: avoid “fixing skew” by adding new vias or reference-plane switches—those often cost more than they save.
Practical rule: avoid “fixing skew” by adding new vias or reference-plane switches—those often cost more than they save.
Inter-pair skew (lane-to-lane)
Why it matters: multi-lane links rely on predictable lane alignment; excessive mismatch reduces usable margin even if each lane looks “OK” alone.
Practical rule: match lane groups by routing topology first (same layer/transition count), then trim length.
Practical rule: match lane groups by routing topology first (same layer/transition count), then trim length.
When serpentine “length tuning” can get worse
- Placed in sensitive zones: near connector launches, via fields, or AC-coupling capacitors (discontinuity-dominant regions).
- Too dense / too tight: creates a local coupling “hot spot” that behaves like a new discontinuity.
- Forces extra transitions: adding vias or reference switches to gain length often costs more margin than the skew it fixes.
Sign-off placeholders (fill with protocol/rate requirements)
- Intra-pair skew: Δt_skew < X% UI
- Length mismatch: ΔL < X mm
- Differential impedance stability: Zdiff within ±X% along the route (excluding controlled transitions).
Diagram — Cross-sections + skew view (concept)
Practical reading: focus on geometry consistency and skew control.
Avoid “tuning” that introduces new transitions or local coupling spikes.
Continuous Return Path: Reference Planes, Splits, Stitching & Ground Strategy
A differential pair still needs a continuous return path.
When the reference breaks (plane split, void, or uncontrolled reference switching), return current detours,
the loop area grows, and the channel becomes prone to mode conversion,
reflections, and “fragile” behavior under tolerance.
Common hidden failures (what to audit first)
- Crossing a plane split / void: forces return detours, increasing mode conversion risk.
- Reference-plane switching without stitching: vias move the signal layer, but return has no “near bridge”.
- Connector launch with broken ground: cutouts or gaps near the launch amplify discontinuity dominance.
Stitching principles (keep return current close)
- Via fence near transitions: provides short return paths and reduces detour loop area.
- Bridge the reference when switching planes: return should not “hunt” for a distant connection.
- Critical zones first: connector launch and AC-coupling capacitor areas deserve the strictest return-path hygiene.
Critical-zone rules (apply before length tuning)
Connector launch zone
Keep reference uninterrupted; avoid ground cutouts; add a compact via-fence to keep return current tight around the launch transition.
AC-coupling capacitor zone
Treat the capacitor placement as a return-path event; preserve reference continuity across the gap and provide nearby stitching where return wants to cross.
Sign-off placeholders (return-path hygiene)
- No differential routing crosses a plane split/void without an engineered return bridge.
- Reference switching points have nearby stitching (via-fence / bridge) and are reviewed as “discontinuity hotspots”.
- Connector and AC-cap zones pass the return-path checklist; residual risk stays below threshold X.
Diagram — Return current detour vs continuous return (concept)
Practical reading: return-path breaks behave like hidden discontinuities. Fixing return continuity often provides larger gains than aggressive length tuning.
Discontinuities & Transitions: Vias, Pads, Breakouts, Connectors
A discontinuity is a sudden change in geometry or reference that creates an
impedance step and/or return-path disruption. The engineering goal is to identify the
dominant discontinuities and remove them in the most cost-effective order.
Discontinuity checklist (channel review map)
- Vias: transition geometry, unused stub segment, anti-pad shape, and nearby return stitching.
- Pads & breakouts: BGA fanout density, pad/via field uniformity across lanes, and reference continuity.
- Inline components: AC-coupling caps, protection devices, test pads—each creates a local step if not treated as a transition.
- Connector launches: the board-to-connector-to-cable handoff is often the dominant step and a common mode-conversion hotspot.
- Plane switching: any reference change without a short return bridge behaves like a hidden discontinuity.
Via stubs, anti-pads, and backdrill (principle-level)
Stub = resonance source: an unused via segment behaves like a short transmission-line branch, producing frequency-dependent reflection.
The decision to backdrill should follow evidence: if TDR/VNA points to the via transition as a dominant step and margin is tight, backdrill becomes a high-leverage fix.
Before that, reducing via count and controlling return-path stitching usually offers better cost/performance.
- Do less first: fewer vias and fewer reference switches reduce discontinuities at the source.
- Make transitions repeatable: lane-to-lane consistency often matters more than isolated perfection.
- Backdrill when justified: apply where the stub transition is dominant and cannot be avoided architecturally.
Fix priority (highest leverage first)
- Connector launch and board-to-cable transition — a single step can dominate the entire channel response.
- Breakout region density — stacked transitions (pads/vias/reference changes) often create the “fragile link” signature.
- Via transitions on the main route — especially where unused stubs or poor return stitching exist.
- Inline components/test points — treat as engineered transitions or relocate out of the high-speed path.
Sign-off placeholders (discontinuity control)
- Dominant discontinuity identified by TDR/VNA and reduced below threshold X.
- Lane-to-lane transition pattern consistent (same via count / same reference switching pattern).
- Connector launch review passes checklist; residual step and mode conversion within target X.
Diagram — Discontinuity map along the channel (concept)
Practical reading: treat the channel as a sequence of transitions. Reduce transition count, then engineer the remaining transitions to be consistent and well-stitched.
Termination & AC Coupling: Where Reflection Is Born and How to Kill It
Termination is not “copy a reference design”. It is the engineered choice of
where reflections are absorbed,
so they do not bounce back into sensitive discontinuities and collapse usable margin.
Termination strategy (reflection-path logic)
Source termination
Controls what returns to the driver. Useful when a clean launch is needed and the main risk is re-reflection at the source.
Verify by checking that the first reflection is reduced and does not re-enter the channel with significant amplitude.
Load termination
Absorbs reflections at the far end to prevent bounce-back. Best when the receiver end is the dominant mismatch region (including connector/cable handoff).
Verify by confirming reduced return-loss and a quieter tail in the time response.
Both-end termination
Strongest reflection control at the cost of amplitude and power. Use when the channel is long or discontinuity-dense and margin is tight.
Verify by time-response flattening and reduced ringing across the full route.
AC coupling is a transition event (placement + return + symmetry)
- Placement: treat the capacitor region as part of the channel. Avoid placing it where the channel is already discontinuity-dominant.
- Return path: maintain reference continuity and provide nearby stitching so return current does not detour around the capacitor break.
- Symmetry: mismatch in component parasitics or layout asymmetry can create differential imbalance and mode conversion.
Common termination mistakes (red flags)
- Divider termination adds nodes: extra pads/vias can introduce a new discontinuity that offsets the benefit.
- Tolerance-driven imbalance: ΔR/ΔC or asymmetric placement can create differential mismatch and increase mode conversion.
- Wrong side / wrong distance: a termination far from the mismatch point may still allow reflections to bounce through sensitive regions.
Sign-off placeholders (reflection control)
- Return loss (or reflection coefficient) meets threshold: RL ≥ X (or |Γ| ≤ X).
- TDR step amplitude at the termination region ≤ X.
- Termination symmetry: ΔR/ΔC ≤ X and layout remains pair-symmetric.
Diagram — Incident/reflected waves: mismatch vs matched (concept)
Practical reading: mismatch creates reflections that bounce through discontinuities; a well-placed termination prevents re-entry and stabilizes the time response.
Loss & Crosstalk Budgeting: IL/RL/NEXT/FEXT and Mode Conversion
Budgeting turns SI into an accounting problem:
split the channel into segments, assign IL/RL/NEXT/FEXT/mode-conversion contributions, and keep a measurable margin.
The deliverable is a reusable budget template that highlights the dominant segment.
Insertion loss (IL) — frequency dependent, segmentable
- Frequency slope: IL rises with frequency; higher-frequency content is more sensitive to dielectric loss, conductor loss, and roughness.
- Segment contributions: board traces, transitions, connector launches, and cables each contribute differently; one segment often dominates.
- Practical focus: prioritize reducing the dominant IL segment before tuning secondary details.
Return loss (RL) — discontinuity-dominant and additive
RL is driven by impedance steps and their accumulation along the route.
Connector launches frequently dominate because they combine geometry change, reference complexity, and symmetry risk.
Budget RL by identifying the dominant step and reducing it below target X.
Crosstalk (NEXT/FEXT) — coupling length is the real budget knob
- NEXT: near-end coupling signature—often dominated by the nearest coupling corridor and launch regions.
- FEXT: far-end coupling signature—often dominated by long parallel routing corridors and consistent spacing over distance.
- Budget variables: coupling length, spacing, layer adjacency, and return/reference integrity (which shapes fields and coupling strength).
Mode conversion (concept-level) — why SI and EMI can degrade together
Asymmetry in geometry, reference, or components can leak differential energy into common mode.
In SI terms, this reduces effective differential margin and can worsen eye closure; in system terms, increased common-mode energy is more prone to radiation.
Track mode-conversion risk as a budget item (X) and tie it to specific asymmetry sources.
Deliverable — segment budget template (placeholders)
- Rows: segment A (Tx board), launch A, cable, launch B, segment B (Rx board).
- Columns: length, IL, RL risk, NEXT/FEXT risk, mode-conversion risk, notes (tags).
- Outcome: total + margin X, plus “dominant segment” identified for the first fix.
Diagram — Budget table + simplified IL curve (concept)
Practical reading: budget by segments, then fix the dominant segment first; treat crosstalk and mode conversion as first-class budget items, not afterthoughts.
Layout Workflow: Constraints, Routing Rules, and SI-Aware DRC
A practical SI workflow is a repeatable pipeline:
choose stackup, define constraints, route with priority zones, run SI-aware DRC, and sign off with review gates.
The goal is to make most checks machine-verifiable.
Step 0 — stackup decisions (root constraints)
- Signal layers mapped to continuous reference planes (avoid avoidable plane switching).
- Target impedance window and manufacturable geometry confirmed (placeholders X).
- Critical zones pre-identified (connector launch, breakout, AC-coupling corridor).
Step 1 — constraint set (make DRC enforceable)
- Geometry: width/spacing rules, pair symmetry rules, keepouts in critical zones.
- Matching: intra-pair mismatch ≤ X, lane-to-lane mismatch ≤ X.
- Crosstalk: parallel-corridor length limits and spacing floors (placeholders X).
- Transitions: via count limit per lane and reference switching limit (placeholders X).
Step 2 — routing priority zones (time on the dominant risks)
- Connector launch: keep symmetry, minimize local steps, ensure return continuity.
- BGA breakout: enforce consistent transition patterns and avoid “one lane worse” layouts.
- AC-coupling zone: treat as a transition and preserve local return bridging.
- Parallel corridors: minimize long adjacency and enforce corridor rules.
- General routing: follow constraints; avoid unnecessary transitions.
Step 3 — SI-aware DRC (auto-check everything possible)
Automatable: length mismatch, spacing, via count, layer changes, corridor parallelism.
Gate review: reference continuity at transitions, launch symmetry, breakout uniformity, AC-cap return strategy.
Gate review: reference continuity at transitions, launch symmetry, breakout uniformity, AC-cap return strategy.
Step 4 — review gates (sign-off checklist placeholders)
- All constraints pass; exceptions documented with risk tags.
- Critical zones pass gates (launch / breakout / AC zone) with consistent lane patterns.
- Budget table margin ≥ X and dominant segment fixed first if margin is tight.
Diagram — Layout workflow (stackup → constraints → route → DRC → review)
Practical reading: constrain early, route by priority zones, then let SI-aware DRC and review gates keep the channel consistent and repeatable.
Simulation & Correlation: IBIS-AMI, S-Params, and What to Trust
Simulation is a trust chain:
credible inputs, a model level that matches the question, and a closed loop with measurement.
Without correlation, results are trend guidance, not sign-off evidence.
Model levels — use the right ladder rung
Rule-of-thumb
Use for: early feasibility and dominant-risk screening (length/material/connector class).
Not for: locating a specific discontinuity or lane-to-lane worst case.
Minimum input: topology segments + approximate stackup + target frequency band.
Not for: locating a specific discontinuity or lane-to-lane worst case.
Minimum input: topology segments + approximate stackup + target frequency band.
S-Params
Use for: IL/RL/NEXT/FEXT alignment to the budget table; isolating dominant segments.
Not for: equalization/decision behavior without a compatible receiver model.
Minimum input: complete channel coverage including launch/connector/cable (no “missing blocks”).
Not for: equalization/decision behavior without a compatible receiver model.
Minimum input: complete channel coverage including launch/connector/cable (no “missing blocks”).
IBIS-AMI
Use for: system-level eye/BER trends with equalization and sampling effects.
Not for: optimistic results when the channel model omits launches/vias/plane breaks.
Minimum input: realistic channel S-params + correct Tx/Rx settings (placeholders X).
Not for: optimistic results when the channel model omits launches/vias/plane breaks.
Minimum input: realistic channel S-params + correct Tx/Rx settings (placeholders X).
When simulation looks great but hardware fails — the usual suspects
- Missing blocks: connector/launch, cable variants, AC-caps/ESD parasitics, package/padstack.
- Wrong boundaries: plane splits/voids not represented; return-path bridging omitted.
- Averaged lanes: one worst lane exists on hardware; model uses “typical”.
- Process & tolerance: stackup/roughness/material spread shifts IL slope and RL steps.
- Port definition mismatch: measurement plane vs simulation ports not aligned; de-embedding differs.
Minimal correlation loop (fast, reusable)
- TDR: confirm the dominant discontinuity exists in the model (location + strength).
- VNA: match IL/RL curve shape (slope + step features) to calibrate segment contributions.
- Eye/BER: validate system-level trend consistency; if mismatch remains, return to the missing-block checklist.
Diagram — Model ladder (trust increases with correlation)
Practical reading: climb the ladder only as far as needed; require a minimal measurement loop before treating simulation as sign-off evidence.
Measurement & Debug: TDR, VNA, Eye/BER and Fast Triage
Debug speed comes from choosing the first measurement correctly.
TDR is for locating discontinuities, VNA is for channel budgeting curves, and Eye/BER is for system-level verification.
Tool roles (do not mix them up)
TDR = locate
Finds where a discontinuity is and how strong it is. Best first step for “reflection-like” symptoms.
VNA = budget
Measures IL/RL/NEXT/FEXT curves to validate margin and identify the dominant segment driving the budget.
Eye/BER = verify
Confirms the system-level outcome. Use after the dominant physical root cause is narrowed down.
Fast classifier — reflection vs crosstalk vs loss/ISI
- Reflection-like: sensitive to cable/connector changes; intermittent CRC/training issues; strong dependence on insertion/removal or launch quality.
- Crosstalk-like: worsens with neighbor activity/throughput; lane-specific coupling corridors; improvements when aggressors are quiet.
- Loss/ISI-like: degrades with length; becomes stable by lowering rate; shows temperature/material sensitivity and IL slope dominance.
Deliverable — triage decision path (threshold placeholders)
The decision tree routes symptoms to the first measurement (TDR/VNA/Eye), then maps results to likely root-cause buckets.
Each branch ends with a pass/fail gate using placeholders X so it can be reused across protocols.
Diagram — Debug decision tree (symptom → first test → likely cause)
Practical reading: pick the first test based on symptom class, then route results into a root-cause bucket with reusable threshold placeholders (X).
Sign-off Gates: What “Done” Means (Prototype → Mass Production)
“SI done” means passing four gates with evidence and pass/fail criteria — not “the eye looks OK”. Each gate has Inputs, Checks, and Pass criteria (thresholds as X placeholders).
Gate 1
Layout Review (rules + hotspots)
- Inputs: stackup + impedance targets, routing constraints, hotspot map (launch/breakout/AC-cap), DRC report.
- Checks: (auto) length/skew/spacing/via-count; (manual) return-path continuity across plane changes, launch symmetry, via stubs, dense-parallel segments.
- Pass criteria (X): skew/spacing/via limits met; no uncontrolled plane-split crossings; hotspot checklist closed with review record.
Gate 2
Budget Review (IL/RL/XT margin)
- Inputs: channel segmentation list (PCB + connector + cable), IL/RL/XT assumptions, “worst lane” identification.
- Checks: dominant segment first (the segment that consumes most margin), verify that improvements move the right budget term.
- Pass criteria (X): total margin ≥ X; worst-lane margin ≥ X; assumptions frozen (connector/cable/stackup versions recorded).
Gate 3
Prototype Correlation (minimum loop closure)
- Inputs: TDR/VNA/eye or BER measurements, model inputs (stackup + vias + connector/cable).
- Checks: if “sim good, board bad”, first suspect missing/incorrect transitions (connector launch, via, plane split), not firmware knobs.
- Pass criteria (X): TDR discontinuity locations match within X; IL/RL curve shape matches within X; measurement explains failures and predicts fix direction.
Gate 4
Manufacturing Guardrails (tolerance-proof)
- Inputs: fab capability window, impedance coupon plan, connector/cable tolerance info, incoming inspection plan.
- Checks: identify which tolerance shifts hurt margin most (impedance, dielectric loss, launch RL, lane skew).
- Pass criteria (X): tolerance window still passes margin ≥ X; sampling plan defined (N boards / lot, N lanes / board) with go/no-go thresholds.
Diagram · 4-Gate SI Sign-off Checklist (evidence-driven)
Engineering Checklist + Applications + SI-Based IC Selection Logic
This chapter compresses the page into an execution-ready checklist, then maps high-speed I/O applications to SI hotspots, and finally provides SI-only silicon selection logic with example part numbers (as references, not recommendations).
A) Engineering Checklist (Design → Bring-up → Mass Production)
- Design: stackup frozen + target Zdiff/Zcm documented; constraints exported (width/space/via-count/plane-changes as X).
- Design: return-path review closed: no uncontrolled plane split/void crossings; stitching plan defined where unavoidable.
- Design: discontinuity map closed: launch/vias/pads/AC caps/connectors marked; “remove transitions first” order defined.
- Design: loss/XT budget sheet complete: segment contributions + worst lane + margin (X) + assumptions locked.
- Bring-up: triage path prepared: symptoms → first measurement (TDR/VNA/eye) → likely root-cause bucket.
- Bring-up: minimum correlation loop closed: TDR/VNA/eye trends align with model; gaps are recorded as missing-model items.
- Mass production: tolerance proof done: fab/material/connector variances still meet margin (X); sampling plan defined.
B) Applications (SI-only hotspots; no protocol deep-dive)
USB (dense Type-C routing)
- Dominant risk: launch asymmetry + near-end crosstalk in dense escape.
- First check: TDR around the connector launch; verify differential symmetry (Δ) and return continuity.
- Typical silicon knob: linear redriver/mux for channel boost when margin is loss-limited (see examples below).
PCIe (long traces / backplanes / multiple transitions)
- Dominant risk: IL slope + stacked discontinuities (vias/connector) consuming timing + amplitude margin.
- First check: VNA IL/RL against the budget; locate dominant segments before tuning firmware.
- Typical silicon knob: linear redriver for boost; retimer when re-timing/jitter clean-up is required by the margin.
HDMI (connector/cable transition dominated)
- Dominant risk: RL at launch + mode conversion across cable/connector transitions.
- First check: TDR for step + location; confirm that “fix” targets the actual reflection source.
- Typical silicon knob: TMDS retimer when the eye/jitter margin is transition-limited.
MIPI (high-density coupling / skew sensitivity)
- Dominant risk: coupling + intra/inter-lane skew under tight routing density.
- First check: geometry + spacing hotspots; confirm continuous reference through escapes and layer changes.
- Typical silicon knob: keep transitions minimal; protect SI first before adding components that add parasitics.
C) IC Selection Logic (SI perspective) + Example Part Numbers
Selection is driven by what consumes margin: loss-limited channels prefer linear redrivers; jitter/timing-limited systems may need retimers. Use examples as “search anchors”; verify speed grade, package, and channel count against the project’s budget (X).
Decision rules (direct vs redriver vs retimer)
- Direct: channel loss + reflections are inside margin (X) with comfortable worst-lane headroom.
- Redriver / linear repeater: margin is primarily loss/ISI; prefer minimal latency and protocol transparency.
- Retimer (CDR): margin is timing/jitter limited; re-timing/cleanup is required to recover the sampling window.
Example silicon (redrivers / retimers / TMDS)
- USB Type-C SS redriver/mux (10 Gbps class): TI TUSB1046-DCI, TUSB1046A-DCI.
- PCIe-class linear redrivers (multi-lane): TI DS80PCI402 (Gen3-class), DS80PCI810 (8-ch), DS160PR410 (up to PCIe 4.0), DS320PR810 (up to PCIe 5.0 class).
- Multi-rate retimer (CDR) examples: TI DS250DF410 (25 Gbps class retimer).
- HDMI TMDS retimer examples: TI TMDS171 (HDMI 1.4b class), TMDS181 (HDMI 2.0 class).
“SI side-effects” components (examples)
- ESD protection (ultra-low capacitance families): TI TPD4E05U06, Nexperia PESD5V0S1UL. Treat these as SI elements: match differential symmetry and validate RL impact.
- Rule of thumb: any “helpful” part near the channel is a potential discontinuity. Add only when the budget proves it is needed.
Diagram · SI Decision Matrix (loss/length vs complexity/margin)
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FAQs (SI Triage) — Fixed 4-Line Answers + Threshold Placeholders
Scope: field triage only. Each FAQ is strictly SI-bound and uses the same 4-line structure: Likely cause / Quick check / Fix / Pass criteria (all thresholds as X placeholders).
Length match looks OK, but BER is still high — intra-pair skew or return-path discontinuity first?
Likely cause: apparent length match hides effective skew (P/N asymmetry at transitions) or a localized return-path break causing mode conversion.
Quick check: TDR around launch/breakout + compare P/N step symmetry; flag any sharp step coincident with plane changes or component pads.
Fix: normalize the worst transition (launch/breakout/via) before adding routing compensation; restore continuous reference and symmetry through that region.
Pass criteria (X): Δtskew ≤ X_UI·UI (or ΔL ≤ X_mm); TDR P/N step mismatch ≤ X_%Z0; BER ≤ X_BER over X_bits (or X_time).
Adding serpentine to match length made it worse — local coupling or stacked discontinuities?
Likely cause: serpentine increases local coupling/impedance ripple and adds extra corners/segment boundaries, creating new reflection + crosstalk hot spots.
Quick check: mark the serpentine section as a segment and compare before/after TDR “ripple density” and near-field coupling risk (dense parallel adjacency).
Fix: replace long serpentine with distributed small adjustments; keep spacing uniform; avoid tight parallel runs; prioritize symmetry at transitions over raw length equality.
Pass criteria (X): added TDR ripple amplitude ≤ X_%Z0; incremental RL degradation ≤ X_dB at fNyq; eye width loss ≤ X_UI; BER improvement ≥ X_factor (or BER ≤ X_BER).
Simulated eye looks great, but the board eye is closed — which missing discontinuity model is most likely?
Likely cause: the model omits a dominant transition: connector launch, via stub/antipad, plane split/void, AC-coupling pad/via, or ESD/footprint parasitics.
Quick check: correlate with measurements in minimum loop: TDR to locate the strongest step; VNA IL/RL to identify unexpected slope/notches.
Fix: add the missing transition (S-params or extracted geometry) and re-run; only trust simulation after TDR/VNA trends align.
Pass criteria (X): model-vs-measure step location error ≤ X_mm; RL curve shape match within X_dB band; IL@fNyq error ≤ X_dB; eye/BER prediction direction matches measured fix outcome.
Training fails intermittently, but re-plugging fixes it — reflection-like or crosstalk-like? What is the first measurement?
Likely cause: re-plug sensitivity strongly suggests connector/launch variability (reflection + mode conversion) more than steady crosstalk.
Quick check: TDR around the connector + launch to compare “plug A vs plug B” step magnitude/shape; look for a dominant step shift.
Fix: harden launch geometry and return path; reduce transition count; enforce connector/cable version control and incoming sampling checks.
Pass criteria (X): plug-to-plug TDR step variation ≤ X_%Z0; training failure rate ≤ X_per_hour; RL@fNyq ≥ X_dB (or ≤ −X_dB per definition).
Speed drops as temperature rises — material-loss drift or connector contact drift?
Likely cause: temperature increases effective loss (IL slope) or increases launch/contact variability (RL/mode conversion) at the connector.
Quick check: VNA across temperature points: if IL slope worsens broadly → loss-drift; if RL degrades sharply or notches appear → contact/launch dominated.
Fix: for loss-drift: shorten dominant segments / improve stackup margin; for contact/launch: tighten connector control and improve launch symmetry/return.
Pass criteria (X): ΔIL@fNyq(T) ≤ X_dB across X_temp; RL drift ≤ X_dB; throughput/BER stays within X_window across X_temp.
Only one cable / one connector lot fails — VNA first or TDR first?
Likely cause: lot-specific RL/mode conversion or impedance step; the failure is segment-driven rather than board-wide routing.
Quick check: use VNA first when comparing lots (curve-to-curve IL/RL difference is the fastest discriminator); use TDR first when needing exact step location on the assembly.
Fix: lock approved cable/connector versions; add incoming sampling with go/no-go templates; update budget assumptions per lot data.
Pass criteria (X): lot-to-lot IL/RL delta ≤ X_dB; TDR step signature matches golden within X_%Z0; failure rate ≤ X_ppm in X_samples.
Stronger/closer TVS made SI worse — Cdiff mismatch or return path interruption?
Likely cause: added pad/via parasitics create a new discontinuity; asymmetry between P/N (ΔC) introduces differential imbalance and mode conversion.
Quick check: compare P/N symmetry in TDR around the TVS footprint; inspect return-path continuity near the placement (reference plane + stitching).
Fix: enforce footprint symmetry, minimize stubby branches, keep the differential path straight, and ensure a continuous reference beneath the device pads.
Pass criteria (X): ΔC/imbalance-induced TDR mismatch ≤ X_%Z0; RL penalty ≤ X_dB at fNyq; BER ≤ X_BER over X_bits; eye closure penalty ≤ X_UI / X_mV.
One lane is intermittently worse than others — breakout issue or via stub issue?
Likely cause: lane topology inconsistency (extra via/plane change/escape pattern) or lane-unique stub resonance.
Quick check: overlay the worst lane’s transition count and locations vs a good lane; then validate with lane-by-lane TDR step map.
Fix: template the lane topology (same via stack and plane transitions); if stub-dominated, remove stub (backdrill) only where it aligns with dominant steps.
Pass criteria (X): lane-to-lane IL/RL variance ≤ X_dB; lane-to-lane TDR dominant step variance ≤ X_%Z0; worst-lane BER ≤ X_BER over X_bits.
Eye height is fine but eye width is not — skew first or ISI/loss first?
Likely cause: horizontal closure indicates sampling-window shrink driven by skew or ISI from loss/dispersion; vertical margin alone is not decisive.
Quick check: if closure changes strongly with length/temperature → loss/ISI; if it tracks topology asymmetry between P/N or lanes → skew/transition asymmetry.
Fix: address the dominant bucket: reduce discontinuities/length for ISI; normalize symmetry and effective skew at transitions for skew-limited cases.
Pass criteria (X): eye width ≥ X_UI·UI; Δtskew ≤ X_UI·UI; IL@fNyq margin ≥ X_dB; BER ≤ X_BER over X_bits.
TDR shows a big step but the system still runs — how does “step size” map to a risk threshold X?
Likely cause: not every discontinuity is dominant; risk depends on step magnitude, location (launch vs mid-channel), and stacking with other transitions.
Quick check: classify the step: magnitude (ΔZ/Z0), location, and whether multiple steps align in time (stacking).
Fix: only optimize steps that dominate RL/eye degradation; remove or smooth the dominant step first, and re-check budget deltas after each change.
Pass criteria (X): dominant-step magnitude ≤ X_%Z0 at the critical location; stacked-step count ≤ X_count within X_mm window; RL@fNyq meets X_dB; BER meets X_BER.
Backdrill improved little — is the dominant problem actually the connector launch?
Likely cause: via stub was not the dominant contributor; connector launch/escape or plane transitions dominate RL/mode conversion.
Quick check: compare pre/post-backdrill IL/RL deltas; if RL/eye barely moves, locate the largest remaining TDR step (often at launch).
Fix: optimize launch first (pad/antipad/ground via fence symmetry, return continuity) and reduce transition count before further via surgery.
Pass criteria (X): RL improvement at fNyq ≥ X_dB after dominant-fix; launch-region TDR step ≤ X_%Z0; overall margin gain ≥ X_dB; BER ≤ X_BER.
Same PCB design varies a lot across fab batches — prioritize Dk/Df drift or impedance tolerance first?
Likely cause: Dk/Df and copper roughness drift changes IL slope; impedance/tolerance drift changes reflection and effective skew — both can dominate depending on the channel budget.
Quick check: VNA for IL slope spread (material-driven) and coupon/TDR for impedance spread (geometry/tolerance-driven); identify which correlates with failures.
Fix: tighten the dominant process window: material spec + approved stackup + impedance coupon plan + acceptance templates for IL/RL.
Pass criteria (X): batch-to-batch IL@fNyq spread ≤ X_dB; impedance (Zdiff) within X_ohm (or X_%); failure rate ≤ X_ppm over X_lot; worst-lane margin ≥ X_dB.
