On-chip reference only

In the simplest topology the ΔΣ ADC uses its internal reference exclusively. The device may expose a REFOUT pin to monitor temperature or provide a rough reference for other blocks, but the main VREF pins are driven from an internal bandgap and buffer loop.

• Typical use: 16-bit class converters where AVDD is already regulated, supply ripple is small and a few dB of margin on ENOB and noise floor are acceptable.
• Reference noise & PSRR: entirely dictated by the ADC’s internal design. Your job is to keep AVDD clean and follow datasheet guidance on decoupling.
• Output capability: REFOUT is not meant to drive other converters or heavy loads. Treat it as a monitoring node, not a shared precision rail.

If you are chasing every fraction of a bit or need to coordinate multiple ΔΣ channels, on-chip reference mode is often too limiting and an external reference topology becomes necessary.

External reference, unbuffered VREF pins

Here a stand-alone, low-noise reference drives the VREF pins through a simple RC network. From the reference perspective, the ΔΣ ADC’s VREF input behaves like a capacitor that is periodically charged and discharged by the modulator’s sampling actions.

• Typical use: 16–20 bit effective resolution, modest sampling rates and one or a few ΔΣ ADCs using the same rail.
• Reference noise: the reference’s integrated noise in the ADC’s passband should sit comfortably below the converter’s own noise floor; numeric budget examples follow in the next section.
• PSRR: at the switch-mode frequency of upstream regulators, target tens of dB more rejection than your system ripple budget. The combination of supply filtering and the reference’s PSRR must keep VREF ripple in the low μV range.
• Output capability: the reference must remain stable with the datasheet-recommended output capacitor and deliver the pulsed current drawn by the modulator without excessive droop or ringing.

Watch for long, inductive VREF routes, under-sized capacitors or exotic output caps that violate the reference’s stability conditions. These are common causes of noise floors that sit several dB above datasheet numbers.

External reference with a dedicated buffer

A dedicated buffer amplifier between the reference IC and the ΔΣ ADC absorbs most of the dynamic load. The buffer is sized for the ADC’s sampling pattern and for any sharing between channels, while the reference IC can focus on low noise and thermal stability.

• Typical use: 18–24 bit designs, higher sampling rates, or when you must share one precise reference across several channels without giving up ENOB.
• Reference noise: the combined noise of the reference IC and buffer, referred to the VREF rail, must still stay within the μV-level budget derived from your ENOB and noise floor targets.
• PSRR: consider the entire chain: supply → LDO → reference → buffer → VREF. Weakness in any stage shows up as ripple at the converter output.
• Output capability: the buffer’s output current, bandwidth and phase margin must handle the sum of sampling pulses and output capacitance without instability or overshoot.

This topology is the natural home for the “target impedance vs frequency” design method: you define how stiff VREF must be across frequency, then pick reference, buffer and RC values to meet that target.

Shared reference rail for multiple converters

When multiple ΔΣ ADCs, or a mix of ADCs and DACs, share the same reference rail you gain excellent matching but expose the rail to larger, sometimes simultaneous charge pulses and code-step currents.

• Typical use: multi-phase energy metering, multi-channel instrumentation and systems where absolute accuracy and channel-to-channel tracking are more important than per-channel independence.
• Reference noise & PSRR: budgets must consider the sum of all attached devices. What was acceptable for a single converter may be marginal once several modulator currents stack up.
• Output capability: the reference and its buffer must support worst-case simultaneous sampling, as well as any DAC code transitions that pull on VREF.

Techniques such as per-device RC sections, local buffers and staggered sampling phases help tame load transients. This chapter only introduces the topology; later sections focus on noise, PSRR and dynamic behaviour.

Reference noise and ENOB budget

A ΔΣ converter’s noise floor comes from the modulator, digital filter, front end and the reference rail. To keep the reference from dominating, you translate ENOB and full-scale specifications into a simple noise budget.

For a converter with full-scale voltage V_FS and ideal resolution N_bits, the nominal LSB size is:

LSB ≈ V_FS / 2^N_bits

An effective resolution of N_eff bits implies a total rms noise at the output equivalent to a few LSBs at that resolution. If you budget roughly one third of the total rms noise to the reference, then the reference noise contribution, referred to VREF and integrated over the converter passband, should be on the order of:

V_n,ref_rms ≲ (1/3) × (LSB at N_eff) × k

where k is a small factor (a few LSBs) that depends on how aggressively you want the reference contribution buried under the ADC’s own noise.

In practice you look at the integrated noise specifications of the reference IC (for example 0.1–10 Hz noise plus wideband noise to the converter’s bandwidth) and check that this total is well below the ΔΣ ADC’s input-referred noise. Typical targets are a few microvolts rms for 18–20 bit systems and sub-microvolt for very high resolution metering.

The digital filter also shapes noise: noise inside the passband of the ΔΣ filter appears directly at the output, while wideband noise outside the passband is largely suppressed. When comparing reference noise curves, pay attention to the frequency range over which you are integrating and match it to the converter’s passband, not just the modulator frequency.

PSRR chain and supply coupling

Supply ripple travels through the LDO, the reference IC and the ΔΣ converter’s own reference rejection before it appears as variation at the ADC output. A simple chain calculation keeps the numbers under control.

You can work frequency by frequency using four steps:

1. Start from the upstream ripple: for example X mVpp at the switching frequency of the DC/DC feeding your LDO.
2. Apply the LDO’s PSRR at that frequency to estimate ripple at the reference input. Convert dB to a linear attenuation factor and multiply.
3. Apply the reference IC’s PSRR at the same frequency to obtain the ripple on the VREF rail.
4. Apply the ΔΣ ADC’s reference rejection figure at the relevant tone or band to estimate the equivalent amplitude at the converter output.

As a design rule, ripple-derived noise and spurs that originate in the reference supply chain should stay clearly below the random noise budget from the previous subsection. If a single ripple tone translates into several LSBs of modulation at the converter output, that tone is likely to show up as an obvious spur in an FFT and needs further filtering or a cleaner supply.

Combining PSRR contributions is often easier in dB: you add the LDO’s PSRR, the reference PSRR and the converter’s reference rejection to get a total attenuation at a given frequency. Since real parts have frequency-dependent PSRR, it pays to do this calculation at the switching frequency, its harmonics and any other dominant interference frequencies in your system.

Dynamic loading, sampling transients and target impedance

The ΔΣ modulator does not draw a quiet DC current from VREF. Instead, it repeatedly charges and discharges internal capacitors in step with the sampling clock. From the reference’s point of view, VREF is driven by a sequence of current pulses whose shape depends on the converter architecture and configuration.

If the reference source and its buffer present too much impedance at these pulse frequencies, the VREF voltage will droop and ring. You may see small steps on a scope trace at the VREF pin, or increased idle tones and spurs in the FFT whenever the reference circuit is changed. Classic DC load regulation specifications do not capture this behaviour; you need a dynamic view.

A practical way to think about this is to define a target impedance for the VREF rail across frequency, Z_target(f), and then choose reference, buffer and capacitors to keep the actual impedance below that curve. A simple workflow looks like this:

1. Identify the critical frequency bands: DC to a few hertz (for calibration stability), the signal passband, the modulator sampling frequency and its neighbourhood, and the switching frequencies of upstream supplies.
2. For each band, set a maximum acceptable VREF variation (droop or ripple) based on your noise and spur budget. Around the modulator frequency, this is typically a small fraction of an LSB at your target resolution.
3. Estimate the magnitude of the current pulses drawn by the modulator and any other devices on VREF. Relate the allowed voltage variation to an approximate impedance via ΔV ≈ I_pulse × |Z_VREF(f)|.
4. Design the reference IC, buffer, output capacitors and RC elements so that the resulting VREF impedance stays below Z_target(f) in the critical bands. This may involve adding capacitance, choosing capacitors with suitable ESR, or adding a small series resistor to damp ringing.
5. Verify the result in the lab by observing VREF on a fast scope and by measuring FFTs with the ΔΣ ADC itself. Adjust the network if you see excessive droop or spectral artefacts linked to reference loading.

This target-impedance view does not require a full control-theory treatment. It simply forces you to quantify how stiff the reference rail must be at the frequencies where the modulator and supply ripple try to disturb it, then shape the reference and buffer network to meet that objective.

Step 1 — Choose VREF level and headroom

Start by choosing the reference voltage level: common choices are 2.5 V, 3.0 V, 4.096 V or 5 V. The decision is shaped by the ΔΣ ADC’s full-scale range, the front-end amplifier gains and how much supply headroom your power tree can provide.

Make sure the selected VREF, plus any tolerance and drift, stays inside the converter’s VREF min and max ratings under all operating conditions, and confirm that the upstream LDO or regulator still has enough dropout headroom at low line and high temperature.

Step 2 — Translate ENOB and THD+N into a noise budget

With a full-scale voltage chosen, translate your target ENOB and THD+N into a total noise budget. Using the ideal LSB size at the converter’s resolution and your effective number of bits, estimate how many LSBs of rms noise you can tolerate at the output.

Allocate a fraction of that budget to the reference rail, typically one third or less. The result is a target integrated reference noise in the converter passband, plus an approximate limit on spur levels created by supply ripple that leaks through the PSRR chain.

Step 3 — Select the reference IC type

Choose between buried zener, precision bandgap or low-power bandgap references based on noise, drift and supply constraints. Buried zener devices excel at low-frequency noise and long-term stability but need higher supply voltages and more power. Precision bandgaps cover most ΔΣ applications with good noise and moderate tempco at low supply voltages.

Ultra-low Iq bandgaps minimise current but usually have much higher noise and looser drift specifications. Use them only when the ADC resolution, bandwidth and noise budget leave plenty of margin. For brand-specific selection, refer to the dedicated reference IC pages rather than this design-rule overview.

Step 4 — Decide whether a dedicated buffer is required

Next, decide if the reference can drive the ΔΣ VREF pins directly through an RC network or if a dedicated buffer is needed. For single devices with moderate resolution and bandwidth, an external reference plus RC on unbuffered VREF pins can be acceptable when noise and loading analyses look safe.

Once you need 18–20 bit effective resolution, higher sampling rates, multiple ADCs sharing one rail or additional loads such as DACs, a dedicated buffer is usually the safer choice. It decouples the reference IC from the dynamic load and gives you more freedom to shape impedance with capacitors and RC networks.

Step 5 — Choose buffer topology and RC network

Select a buffer topology that can supply the required current pulses with ample bandwidth and phase margin. A single low-noise op amp in unity gain is often sufficient for one or two converters; heavier loading may call for a stronger amplifier or a secondary buffer stage closer to the shared rail.

Place RC networks where they are most effective. A small RC before the buffer can help filter high-frequency supply noise into the reference, while RC elements after the buffer shape the dynamic response seen by the VREF pins. Always respect the stability recommendations for both the reference IC and the buffer regarding output capacitance and ESR.

Step 6 — Design supply path and decoupling

Choose a low-noise regulator for the reference supply with adequate PSRR at the switching frequencies of any upstream DC/DC converters. Place bulk and high-frequency decoupling capacitors close to the reference IC pins, and provide local decoupling near the buffer and each ADC VREF pin.

Ensure that the return paths of these capacitors connect cleanly into the analog ground region and do not share long, narrow traces with digital currents or high-current power loops. A good supply and decoupling layout keeps the PSRR calculations from the previous section realistic.

Step 7 — Check start-up and reset conditions

Analyse the start-up sequence so that the ΔΣ ADC begins conversions only after the reference rail has reached its final value and settled. Combine the reference and buffer data for start-up time with the VREF capacitance to estimate how long it takes before VREF is within tolerance under worst-case conditions.

In firmware or hardware, delay enabling conversions until that time has passed or until a power-good indication is valid. Also consider brown-out and reset scenarios where the ADC and reference do not power down in lock-step: partial resets with an unsettled reference are a common source of hard-to-repeat measurement errors.

Step 8 — Plan timing and IO for shared references

When several ΔΣ converters or DACs share one reference rail, plan their timing so the combined load fits within your target impedance envelope. Co-phase sampling concentrates current pulses and makes spectral artefacts easier to analyse, but it demands a stiffer reference rail.

Interleaving sampling phases spreads the pulses over time and reduces instantaneous droop at the cost of a more complicated frequency picture. Use available sync pins, clock inputs or microcontroller triggers to implement the chosen strategy and verify the result by observing VREF and FFTs in the lab.

Step 9 — Combine tolerances and worst-case corners

Finally, combine initial accuracy, temperature coefficient, ageing, load regulation and layout-induced drops into a worst-case reference error and noise figure. Compare this to the error budget implied by your target ENOB, THD+N and system accuracy requirements.

The typical performance may look excellent, but the guaranteed corner must still leave margin. If worst-case drift, ripple and dynamic loading consume most of the budget, you may need better devices, a different topology or tighter layout practices before you can rely on the design for production and safety-critical applications.

Reference return, analog ground and digital ground

Treat the reference return as part of the signal path, not merely as another ground connection. Tie VREFGND and the ΔΣ ADC analog ground pins into a quiet local region, ideally on a continuous ground plane with a star point near the converter and reference devices. Avoid routing the reference return through narrow traces that also carry digital or switching currents.

Even when AGND and DGND share a common copper plane, you can keep them functionally separated by placing the reference island away from digital drivers and ensuring that high-current return loops close locally rather than beneath the reference and ADC pins.

Kelvin routing for VREF and VREFGND

For high-accuracy ΔΣ applications, route VREF and its return as a matched pair from the reference or buffer to the ADC pins. Use a relatively wide copper trace or small local plane for the main current path and two narrower sense traces that land directly at the ADC pins. This Kelvin-style connection minimises the impact of copper voltage drops and local ground shifts.

Avoid sharing the VREF or VREFGND traces with other loads or returns, and keep their path short, direct and free from unnecessary vias. Keep these traces on a layer that sits above a continuous ground plane so their impedance remains predictable and they are shielded from neighbouring fields.

Keeping distance from switching and digital noise sources

Switching regulators, gate drivers, motor stages and high-speed digital buses are strong sources of magnetic and electric field interference. Place these circuits away from the analog reference island and avoid routing VREF or sensitive sensor lines underneath their high dv/dt nodes or in parallel with fast digital traces for long distances.

When a noisy block must be nearby, use ground planes and guard traces to shield the reference area, and keep the high-current loops physically tight. Reserve a keep-out corridor so that VREF traces do not cross slots, plane splits or regions of high current density in the ground plane.

Thermal placement and copper usage

Reference ICs and precision ΔΣ converters are sensitive to temperature gradients as well as absolute temperature. Place them in a relatively quiet thermal area of the board, away from hot components such as power FETs, linear regulators dissipating several watts, transformers or braking resistors.

Use copper pours around the reference and ADC to provide gentle thermal averaging rather than sharp hot and cold zones. Avoid layouts where one side of the package sits over a heavy power plane while the other side hovers over an empty cavity; such gradients can increase drift and degrade long-term stability. Keeping the reference and ADC close together improves their thermal tracking.

Layout and thermal checklist before tape-out

Use this checklist as a final review before sending your board out:

• Reference IC and ΔΣ ADC are placed close together in a quiet analog region with a continuous ground plane underneath.
• VREF and VREFGND use short, direct routes with Kelvin-style connections to the ADC pins and do not share traces with other loads.
• Local decoupling capacitors for the reference, buffer and ADC are placed next to their pins, with returns tied into the analog ground region rather than long ground runs.
• Switching regulators, FETs, motor drivers and fast digital buses are spatially separated from the reference island, with VREF traces kept away from their high dv/dt nets.
• Ground paths for large load currents close locally and do not pass beneath the reference or ADC packages.
• No slots or splits in the ground plane run under the reference, buffer or ΔΣ ADC pins or under critical VREF routes.
• Hot components are thermally isolated from the reference and ADC; copper around the precision parts is balanced and avoids steep gradients across packages.
• Test points or measurement pads for VREF and VREFGND are available near the ADC so you can verify noise, ripple and droop in the lab.
• Any shield or guard traces around VREF and high-impedance nodes are tied cleanly to analog ground and do not create unintended loops.

When these layout and thermal details align with the earlier design steps, the reference rail seen by the ΔΣ modulator closely matches your calculations instead of being derated by board-level surprises.

Noise and FFT validation

Start with a noise and FFT measurement using the ΔΣ ADC itself as a noise analyser. Short the input to analog ground or drive it from a very quiet mid-scale source, then configure the converter with the same OSR and digital filtering settings you plan to use in the application. Capture a long record of output codes and compute an FFT.

Compare the measured noise floor against the datasheet’s typical performance. A modest increase of one or two decibels can be acceptable, but a five to ten decibel rise often points to reference rail noise or poor PSRR. Note any prominent spurs or idle tones near the switching frequency, line frequency or its harmonics, and repeat the measurement before and after changes to the reference loop so you can see the impact directly.

PSRR and ripple injection tests

Next, quantify how well the reference chain rejects ripple from the supply or from disturbances injected directly onto the VREF rail. Use a programmable supply or coupling network to superimpose a known sinusoidal ripple on the upstream regulator output or on the reference rail. Typical tests use amplitudes such as 5 mV to 20 mV peak-to-peak at frequencies related to the DC/DC switching, mains frequency and a few decade points in between.

For each test condition, measure the resulting code swing or the spur height in the FFT at the injected frequency. Convert the code variation back into an equivalent voltage at the ADC input and compare it to the injected ripple amplitude to compute effective rejection in decibels. Practical ΔΣ reference rails often target 60–80 dB or more of rejection at the key frequencies that your power tree produces.

Dynamic loading and step response at VREF

Use an oscilloscope to observe the reference rail directly at the ADC VREF pin while the modulator is running. With the converter clocked at its intended rate and output filters enabled, probe between VREF and the local analog ground using a short lead and a low-inductance connection. When multiple ΔΣ ADCs or DACs share the rail, test both single-device and worst-case loading patterns.

Look for repetitive droop when the modulator samples, as well as any ringing caused by interactions between the buffer, output capacitors, trace inductance and the switching load. In a healthy design, the droop per cycle is a small fraction of one LSB and the waveform settles smoothly within a few modulation periods. Large, slow sag or sustained ringing suggests that the reference loop is too weak or marginally stable and may cost you several bits of effective resolution.

Temperature and ageing drift

To characterise drift, measure gain and offset over temperature and, when feasible, over time. For a full qualification, sweep the assembly from the lowest to the highest specified temperature in multiple steps, allowing the board to reach equilibrium at each point and capturing a block of codes with a static input. For a simplified small-batch process, three points such as −20 °C, 25 °C and 60 °C already reveal most of the trend.

Assuming the front-end gain is stable, changes in measured full-scale gain largely reflect changes in the reference voltage. Express this as an equivalent ppm per degree and compare it to the combined tempco budget from the reference and buffer datasheets. Where long-term stability matters, keep a few samples powered at an elevated temperature for several hundred hours and re-run the static tests to estimate ageing drift.

Acceptance table for ΔΣ reference rails

Summarise the results in a simple acceptance table that ties each measurement back to its design target. This makes it easy to review designs, justify component choices and keep a traceable record for field returns or future variants.

Once the table is filled, you have a concise view of how far the real hardware is from the error and noise budgets that drove your reference design.

Required BOM fields for ΔΣ reference rails

When you request parts or submit a BOM, the reference section should describe more than “2.5 V precision reference”. The fields below make the ΔΣ requirements explicit so that alternatives can be filtered correctly.

• Nominal VREF value and tolerance. Specify the target voltage (for example 2.5 V, 4.096 V or 5 V) and the required initial accuracy band such as ±0.02 %, ±0.05 % or ±0.1 %.
• Noise density and integrated noise limits. Include limits for 0.1–10 Hz noise and for integrated noise in the relevant bandwidth, derived from your ENOB and spur budget.
• Temperature coefficient and long-term stability. Give the maximum acceptable tempco in ppm per degree and any requirement on long-term drift over thousands of hours or years of operation.
• Output current capability and recommended output capacitor range. State the expected maximum load current, the total VREF capacitance and any ESR window that must be supported.
• Package, height and temperature grade. Note whether the design can accept SOT-23, MSOP, SOIC or DFN packages, the allowed component height and whether industrial or automotive temperature ranges are mandatory.
• Buffering concept. Indicate if the reference is expected to drive the ΔΣ VREF pins directly or if you plan to use a dedicated buffer amplifier. When a buffer is involved, include key amplifier requirements such as supply voltage, output swing, noise level and stability with the chosen load.
• Compliance and special requirements. Call out AEC-Q100, functional safety, medical or metering standards if they apply, so parts without the necessary qualification can be filtered out early.

Sourcing risks and compatibility warnings

Precision references for ΔΣ applications carry a few specific risks that are easy to underestimate when looking only at static numbers.

• High-end low-noise parts have a higher EOL risk. Some very low-noise or legacy buried-zener families are refreshed or discontinued more frequently than mainstream bandgaps. Check lifecycle status and avoid locking a platform into a niche device without a second source plan.
• Startup and settling behaviour differ between vendors. Two “compatible” 2.5 V references can have very different start-up times, minimum load currents and conditions for stable operation. These differences affect ΔΣ self-calibration and cold-start performance and should be recorded and re-verified whenever a substitute is approved.
• Output capacitor requirements may not match. Each reference family defines its own allowed output capacitance and ESR range. A capacitor value chosen for one family can push another into instability. When specifying second sources, confirm that all candidates are stable with the same Cload and layout.
• Pinouts and optional pins are not identical. Devices with trim, force/sense or shutdown pins do not always share pin assignments across vendors. Any replacement must be checked against the actual footprint and schematic, not just the voltage and tolerance.

Example reference ICs for ΔΣ ADC designs

The table below lists representative reference IC families and part numbers that often pair well with ΔΣ converters. It is not a complete catalogue, but a starting point that links performance levels to typical use cases.

Submit your ΔΣ reference BOM for a shortlist

When you already know the ΔΣ ADC type and target ENOB or sample rate, you can convert the requirements above into a short BOM request. Include the converter model, desired VREF level, noise and drift targets, whether several ADCs share the rail and any automotive or safety requirements. A curated shortlist saves time and reduces the risk of picking a marginal reference.