XFET / CMOS Precision Reference
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Definition & Positioning
A CMOS/XFET precision reference is a voltage reference realized on CMOS processes that targets lower 1/f noise density, higher mid-band PSRR (vs. switching supplies), and optionally low quiescent current (Iq). In portable/battery designs—where a DC/DC converter leaves residual ripple, the ADC front end is noise-sensitive, and the power budget is tight— CMOS/XFET references typically outperform generic bandgaps on noise spectral density and PSRR at the switching band. For extreme long-term drift, a buried-Zener family may still be preferred (handled on its own page to avoid cross-talk).
Rule-A (ADC): Bound integrated noise so that
Vn,rms(0.1–10 Hz) ≤ 0.25 × LSBfullscale (e.g., 16-bit/2.5 V).
Rule-B (PSRR): Target
PSRR(fSW) ≥ 50–60 dB when the DC/DC switching band is ~300 kHz–1 MHz.
Rule-C (Iq): On a battery node, allocate reference Iq ≤
10–15% of the total standby budget.
Key Electrical Traits
Noise Spectral Density (with 1/f corner)
Understand the 1/f region vs. flat band. Typical check points are 1 Hz, 10 Hz and 1 kHz. If the corner is high, slow measurements suffer. Design action: add RC isolation and bound the effective bandwidth at the reference pin for slow-moving signals.
0.1–10 Hz Noise (integrated window)
This band dominates low-frequency drift perception. For a 16-bit, 2.5 V front end, a practical target is 2–5 µVpp. If only density points are given, use careful segmented approximation.
PSRR vs Frequency
Do not rely on 100/120 Hz alone. Align PSRR reading with the converter
fSW (and harmonics). Target: PSRR(fSW) ≥ 50–60 dB for mid-band immunity.
If a secondary LDO exists, relax slightly while verifying system-level coupling paths.
Temperature Coefficient (ppm/°C)
Conversion: ΔV[mV] = (ppm/°C × Vout[V] × ΔT[°C]) / 1000.
Example: 10 ppm/°C, 2.5 V, 60 °C span → ΔV ≈ 1.5 mV. Budget against sensor zero/FS errors and consider system temp-comp.
Long-Term Drift
Record a room-temp baseline, then re-measure after burn-in and periodic intervals (e.g., 168 h, 1k h). Expect packaging and lot dependence. Use lot tags in procurement to correlate.
Line & Load Regulation
Line regulation matters with slowly wandering DC/DC outputs; load regulation matters when the ADC front end draws sampling spikes. Check both at operating temperature corners.
Output Impedance & ESR Sensitivity
Reference output Zout varies vs. frequency. Keep output capacitor and ESR within the safe window to avoid under-damped ringing. Detailed numeric windows are given in the stability chapter.
Iq & Startup
Iq varies with VIN and temperature; startup and pre-bias compatibility can dominate duty-cycled sensor behavior. In battery nodes, keep reference standby within 10–15% of the total budget.
Temperature drift conversion:
ΔV[mV] = (ppm/°C × Vout[V] × ΔT[°C]) / 1000
Integrated noise (concept):
Vn,rms(0.1–10 Hz) = √∫0.1→10 Hz Sv(f) df
Risk: Reading only 100/120 Hz PSRR is overly optimistic for mid-band ripple.
Risk: Ignoring the 1/f region underestimates slow-measurement noise.
Risk: Missing Cout/ESR windows can induce under-damped ringing.
Integration Patterns
ADC-REF direct
Routing: Short, straight trace from reference to ADC REF+. Return REF−/AGND back to the source via Kelvin sense; avoid crossing high-current digital returns.
RC: Start with R = 10–47 Ω and C = 0.47–1 µF to limit bandwidth and supply sampling bursts locally.
Checks: Measure Vn,rms(0.1–10 Hz) ≤ 0.25 × LSB; confirm out-of-band noise near the sampling frequency does not fold into results.
LDO-REF for analog island
Routing: Reference drives the LDO FB/REF node; the LDO output feeds only the analog island. Split AGND/PGND and join at a single point.
RC & decoupling: RC limiter ahead of the reference; keep LDO Cout and ESR inside the stability window.
Checks: PSRR at fSW (and harmonics) ≥ 50–60 dB; verify no reverse coupling from LDO output back into the reference.
Sensor bias with RC isolation
Routing: Reference → bias node; Kelvin return to REF−. Place decoupling close to the sensor; keep the bias loop separate from power loops.
RC: Choose R/C from required bias bandwidth; account for duty-cycled startup/charging time constants.
Checks: Map temperature coefficient into zero/full-scale budget; confirm low-frequency noise does not degrade resolution.
Selection & Tuning
Inputs
Resolution and full-scale, DC/DC switching frequency (fSW), temperature range, standby budget for Iq, package height limits, required compliance (e.g., AEC-Q100).
Constraints
Noise limit: Vn,rms(0.1–10 Hz) ≤ α × LSB (α ≈ 0.25).
PSRR target: PSRR(fSW) ≥ 50–60 dB.
Temp drift budget: ppm/°C × ΔT × Vout.
Iq: reference ≤ 10–15% of the total standby allowance.
Component choices
Pick CMOS/XFET reference voltage and grade; choose output capacitor and ESR within the stability window; set the RC limiter from the required bandwidth and sampling profile.
Checks
Measure 0.1–10 Hz noise; read PSRR at fSW; characterize temperature drift and long-term drift; verify pre-bias/startup; re-check return paths to avoid ground-induced modulation.
Temperature drift → mV: ΔV[mV] = (ppm/°C × Vout[V] × ΔT[°C]) / 1000
ENOB impact (approx): LSB = FS / 2^N; if Vn,rms ≈ k × LSB, then Neff ≈ N − log2(√12 × k)
Required PSRR: for input ripple X mVpp and desired output Y mVpp, PSRRreq[dB] = 20·log10(X/Y)
Risk: Reading only 100/120 Hz PSRR gives an overly optimistic view—always align to fSW.
Risk: Excess RC slows startup and step response—match to sampling/wake cadence.
Risk: Ignoring Cout/ESR window can cause under-damped ringing.
Output Network & Stability Notes
Cout/ESR window
Use the datasheet’s stable region to pick a pair (Cout, ESR). Locate the ESR zero below the loop crossover to improve phase margin:
fZ(ESR) = 1 / (2π · ESR · Cout). Small local bypass (10–100 nF) handles HF spikes but should not violate the main stability window.
Loop margin (practical view)
Target phase margin PM ≈ 45–60°. Safe region → single-decay step response; risk region → under-damped ringing or oscillation. Avoid extra poles near crossover (long cables, remote bulk caps).
Load transient
First-slice droop: ΔV ≈ Istep · ESR + (Istep · Δt)/Cout, where Δt is the loop reaction time. For ADC references, minimize the ESR term; use an RC limiter to tame HF edges.
Startup & pre-bias
Control dV/dt to avoid overshoot and false trips at downstream comparators. With pre-bias rails, ensure the reference allows biased startup and the output network does not back-drive internal amplifiers.
Validation checklist
- Cold/hot startup and pre-biased startup waveforms
- ±Istep load steps at ESR/Cout boundary points
- Long-trace/remote-cap scenarios around crossover
- Phase margin estimate via step-decay or frequency sweep
CMOS/XFET vs Bandgap vs Buried-Zener
CMOS/XFET
- Noise (0.1–10 Hz): low; shallow 1/f corner
- PSRR: stronger at mid/high freq (fSW region)
- Tempco: 10–25 ppm/°C typical
- Iq: nA–µA class available
- Drift: low–medium, solid long-term
- Pkg/Cost: small, cost-effective
- Best for: portable/battery precision fronts, sensor bias
Series Bandgap
- Noise: moderate; higher LF noise than buried-Zener
- PSRR: decent at low freq; average mid-band
- Tempco: 20–50 ppm/°C typical
- Iq: tens to hundreds of µA
- Drift: medium
- Pkg/Cost: broad choice, low cost
- Best for: general analog rails, LDO refs, cost-sensitive designs
Buried-Zener
- Noise: lowest; excellent 0.1–10 Hz
- PSRR: strong at low freq; needs extra filtering at mid/high
- Tempco: 1–5 ppm/°C (select grades)
- Iq: mA-class typical
- Drift: best long-term stability
- Pkg/Cost: larger, expensive
- Best for: metrology/calibration sources
Portable/battery → choose CMOS/XFET for low Iq, better mid-band PSRR, and compact packages.
Calibration/metrology → choose buried-Zener for the lowest LF noise and drift. Series bandgap remains a versatile, low-cost middle ground.
Seven-Brand Matrix (placeholder PNs)
Note: Part numbers below are candidates for CMOS/XFET precision references. You will replace each datasheet link with the real URL (rel="nofollow", target="_blank") after verification. Rationale tags explain why each PN is shortlisted (noise, PSRR, tempco, Iq, package, AEC-Q100).
| Brand | Family / PN (datasheet) | Vout | Noise 0.1–10 Hz | nV/√Hz @1 kHz | PSRR @freq | Tempco (ppm/°C) | Iq | Package | AEC-Q100 |
|---|---|---|---|---|---|---|---|---|---|
| Texas Instruments |
REF5025 / REF5030 / REF5040 / REF5050 —
datasheet
Low LF-noise, broad voltage options; good mid-band PSRR; strong ecosystem
|
2.5 / 3.0 / 4.096 / 5.0 V | µV-class (bin-dependent) | tens of nV/√Hz | ≥50–60 dB @ fSW (device-dep.) | 10–25 (grade-dep.) | tens–hundreds µA | SOIC-8, MSOP-8 | variants exist |
|
REF6025 / REF6030 / REF6040 —
datasheet
Lower Iq CMOS/XFET variants; solid PSRR across mid-band; compact
|
2.5 / 3.0 / 4.0 V | low µV-class | low tens nV/√Hz | good @ fSW (part-dep.) | 10–25 typical | tens µA class | SOT-23, SC70 | TBD | |
|
REF7025 / REF7030 / REF7040 —
datasheet
Lower drift/aging bins; battery-friendly Iq options
|
2.5 / 3.0 / 4.0 V | very low (bin-dep.) | low tens nV/√Hz | good mid-band PSRR | ≤10–15 (grade) | low µA class | SOT-23/SC70 | TBD | |
| STMicroelectronics |
CMOS precision Vref family (candidates) —
datasheet
General-purpose precision; small SOT-23/SC70; cost-efficient options
|
2.5 / 4.096 / 5.0 V (slots) | moderate-low (target) | tens nV/√Hz (target) | adequate mid-band (target) | 20–50 typical (target) | low–tens µA (target) | SOT-23/SC70 | TBD |
| NXP |
CMOS precision Vref family (candidates) —
datasheet
Industrial temp range; pairing with NXP ADC/AFE ecosystem
|
2.5 / 3.0 / 4.096 V (slots) | moderate-low (target) | tens nV/√Hz (target) | good mid-band (target) | 20–50 typical (target) | low–tens µA (target) | SOT-23/SC70 | TBD |
| Renesas (Intersil) |
ISL21090 (XFET), ISL60002 (low-power) —
datasheet
XFET lineage; very low LF-noise and drift (21090), portable Iq (60002)
|
2.5 / 3.0 / 5.0 V (family-dep.) | ultra-low (21090) | very low nV/√Hz | good @ fSW with RC aid | ≤10 (select grades) | µA (60002) / higher (21090) | SOT-23/DFN/SOIC (var.) | variants exist |
| onsemi |
NCP/NS/LM-class CMOS precision Vref (candidates) —
datasheet
Common rails, auto/industrial variants; broad availability
|
2.5 / 3.0 / 5.0 V (slots) | moderate (family-dep.) | tens nV/√Hz (target) | adequate @ fSW (target) | 20–50 typical (target) | tens–hundreds µA (var.) | SOT-23/SC70/DFN | some variants |
| Microchip |
MCP1501 / MCP1502 / MCP1525 —
datasheet
Buffered reference options; low Iq variants; tiny packages
|
2.048 / 2.5 / 4.096 / 5.0 V (family-dep.) | low µV-class (part-dep.) | low tens nV/√Hz (typ.) | good with RC limiter (app-dep.) | ≤25 typical (bin-dep.) | low µA class (var.) | SOT-23/SC70/DFN | variants exist |
| Melexis |
Internal reference strategy (sensor ICs) —
app note
If no discrete Vref family: use internal ref + external RC/low-pass; for higher resolution, split domain with a discrete CMOS/XFET ref
|
— | IC-internal (see datasheet) | — | domain-specific | — | package-dep. | — |
rel="nofollow". After link-in, confirm fields (noise bins, PSRR test frequency, tempco grade, AEC-Q100).
Bench & System Checks
Bench (device/board)
- Integrate 0.1–10 Hz noise (low-noise preamp + FFT). Aim ≤ 0.25 × LSB for your target resolution.
- Log PSD and 1/f corner; record nV/√Hz @1 kHz for the datasheet table.
- Inject PSRR at fSW and harmonics; target ≥ 50–60 dB.
- Load steps: verify ΔV ≈ Istep·ESR + (Istep·Δt)/Cout.
- Cold/hot and pre-biased startup; check overshoot and dV/dt.
Subsystem (ADC/LDO/sensor)
- Map Vn,rms to ENOB: Neff ≈ N − log2(√12 · k), where k = Vn,rms/LSB.
- Verify no reverse coupling from LDO output back to the reference node.
- Long traces/remote decoupling: re-check phase margin with step-decay speed.
System (environment)
- Thermal drift: ΔV[mV] = (ppm/°C × Vout[V] × ΔT[°C]) / 1000. Record hysteresis.
- Long-term drift baseline: 168 h / 500 h checkpoints.
- EMI and supply coupling during charge/sleep transitions and RF activity.
Suggested acceptance lines
- Vn,rms(0.1–10 Hz) ≤ 0.25 × LSB
- PSRR(fSW) ≥ 50 dB (portable) / ≥ 60 dB (high-precision)
- Tempco bin meets target (e.g., ≤ 10–15 ppm/°C)
- Startup overshoot ≤ 0.5% Vout; pre-biased startup shows no back-drive
BOM & Procurement Notes
BOM essentials (required fields)
- Vout (exact value + tolerance bin)
- Noise targets: 0.1–10 Hz (µVrms) & nV/√Hz @1 kHz
- PSRR target @ your DCDC freq (e.g., ≥60 dB @ 500 kHz)
- Tempco ceiling (ppm/°C) & ambient range
- Iq max (active / standby)
- Package & Z-height (SOT-23/SC70/DFN)
- AEC-Q100 (Yes/grade)
- Second-source plan (pin/spec compatible)
Procurement risks & mitigations
- Package/EOL: watch PCNs; keep alt footprint if risk > medium
- Spec vs lot: request bin/grade; verify low-freq noise bin
- MOQ/lead time: allow alt-PN with same Vout & tempco
- PSRR@fSW: inject at your switching freq; attach plots
- Automotive: PPAP/IMDS on request; derate with self-heating
Submit your BOM
Pre-fill the required fields above so we can shortlist PNs within 48 hours.
Submit BOM (nofollow)Frequently Asked Questions
How do I translate ppm/°C into mV drift on 2.5 V and 5 V rails?
Use ΔV[mV] = (ppm/°C × Vout[V] × ΔT[°C]) / 1000. Example targets: 10 ppm/°C over 60 °C → 2.5 V ≈ 1.5 mV; 5 V ≈ 3.0 mV. Match the bin to your system budget and confirm with thermal cycling to capture hysteresis.
What PSRR target is “good enough” when the DC/DC is 500 kHz?
Aim ≥ 60 dB at 500 kHz±10%. If margin is thin, add RC isolation (10–100 Ω + 0.1–1 µF), shift fSW, or increase attenuation at the converter. Always bench-inject at the real switching frequency and first harmonic.
How do I bound 0.1–10 Hz noise for a 16-bit ADC front end?
Compute LSB, then target Vn,rms(0.1–10 Hz) ≤ 0.25×LSB. If margin is small, use duty-cycled sampling, chopper techniques, or increase oversampling and average. Validate with low-noise preamp + FFT and integrate over 0.1–10 Hz.
When should I add RC isolation between reference and ADC input?
Add it for SAR kickback, long traces, or weak mid-band PSRR. Start with R=10–100 Ω and C=0.1–1 µF; check settling vs sample/hold window and confirm no phase issues near the loop crossover.
How much output capacitance/ESR keeps a CMOS reference stable?
Stay within the datasheet’s stable window. Place the ESR zero below loop crossover: fZ=1/(2π·ESR·Cout). Use a small local bypass (10–100 nF) for HF spikes without violating the primary stability region.
Do I pick lowest Iq or lowest noise for battery sensors?
For duty-cycled sensing, optimize noise per sample; a slightly higher Iq may reduce averaging time and total energy. For always-on rails, prioritize Iq and filter the band of interest. Verify lifetime and SNR budgets together.
Why can a “quiet” LDO still leak ripple into the reference node?
PSRR holes at mid/high frequencies and shared ground impedance can bypass the LDO’s low-frequency silence. Use star returns, RC isolation, and route the reference as a Kelvin node away from high-di/dt loops.
How do I verify long-term drift without a year-long wait?
Establish a baseline, then run accelerated soaks (e.g., 168 h and 500 h) with periodic checkpoints. Include temperature cycling to expose hysteresis. Fit a log-time model and compare to the device’s drift grade.
When is buried-Zener still the better choice than CMOS/XFET?
When ultra-low 0.1–10 Hz noise and minimal long-term drift dominate and size/Iq are acceptable—metrology sources, calibration gear, or high-stability references. Otherwise, CMOS/XFET wins on Iq, PSRR at mid-band, and size.
Can I reuse the same reference for LDO and ADC without crosstalk?
Yes—with split branches and RC isolation. Keep load transients on the LDO branch from modulating the ADC ref. Validate with load steps on the LDO while observing ADC-side ripple and settling.
What bench setup reveals poor PSRR at mid-band frequencies?
Use a summing resistor or injection transformer to superimpose an AC tone on VIN. Sweep around fSW and measure reference ripple. Normalize to injected amplitude to extract PSRR vs frequency.
How do I prevent startup/pre-bias issues in multiplexed rails?
Control dV/dt and avoid back-drive with series R or a small diode path. Validate cold/hot and pre-biased starts; ensure the reference does not see reverse current through the output network.
