What this page solves – Line-scan imaging with ADCs

This section frames where line-scan imaging ADCs are used, which system-level limits they face, and how the rest of the page will guide line-scan camera design from architecture through IC selection.

Typical use cases for line-scan imaging

Line-scan imaging is widely used where a continuous web or long object moves past a narrow field of view and must be inspected at high speed:

• Print/web inspection – monitoring ink coverage, registration and print defects along high-speed paper or film webs.
• Battery electrode and thin-film inspection – tracking coating thickness and edge quality on moving electrode rolls or functional films.
• Semiconductor and glass surface inspection – detecting scratches, particles and stains across large, expensive panels.

System-level constraints that stress the ADC

Compared with area-scan cameras, line-scan systems push ADCs in three directions at the same time: line rate, image quality and data throughput.

• High line rate and resolution – line rate and pixels per line multiply into an aggressive pixel throughput requirement that a single-channel ADC rarely sustains without heavy multiplexing.
• Image quality: FPN, noise and dynamic range – fixed pattern noise from column mismatch, random noise and limited dynamic range translate directly into visible stripes, lost contrast and missed defects.
• Interface and processing bottlenecks – as data rate climbs, high-speed links such as LVDS and SLVS-EC plus FPGA logic, memory bandwidth and protocol handling become critical constraints.

What the rest of this page will help decide

The remaining sections walk through the line-scan ADC problem from architecture to implementation so that design choices can be traced back to measurable system needs:

• Compare sensor-integrated column-parallel ADCs with external multi-channel ADCs at the system level.
• Translate line rate, resolution and defect size into ADC requirements for resolution, ENOB, dynamic range and channel count.
• Understand front-end and timing constraints between line-scan sensor, analog chain and ADC sampling.
• Plan high-speed LVDS or SLVS-EC links between the line-scan head and FPGA or SoC.
• Build an IC selection checklist and engineering checklist specific to line-scan imaging applications.

System architectures for line-scan imaging

Line-scan cameras can either integrate ADCs inside the sensor die or route analog outputs to external multi-channel ADCs. This section compares these system-level architectures in terms of analog complexity, flexibility and interface demands.

Integrated column-parallel ADC sensors

In a column-parallel architecture, each sensor column has its own small ADC. Pixel values are converted on the sensor and sent out over digital links such as SLVS-EC, LVDS or CMOS. The board-level analog path shrinks to local decoupling and power integrity around the sensor.

• External design focuses on high-speed digital interfaces, clocking and power supply design rather than long analog traces.
• ADC performance and architecture are fixed by the sensor vendor, so upgrades require changing the sensor, not just the ADC.
• Column-to-column mismatch inside the sensor contributes to fixed pattern noise; mitigation relies on sensor features, calibration and thermal control.

External multi-channel ADCs for analog-output line sensors

Analog-output line sensors expose one or more taps that carry pixel signals as voltages. These taps are routed through driver amplifiers into multi-channel ADCs that synchronously sample all active taps and forward digital data to an FPGA or SoC.

• ADC type, resolution and sampling rate can be selected and updated independently of the sensor, enabling board reuse across projects.
• Multi-channel analog routing, bandwidth and matching become critical, especially at high line rates and when several taps share a common reference.
• Channel-to-channel gain and offset mismatch in the external ADC chain can be trimmed or digitally calibrated to reduce visible column artifacts.

Choosing between integrated and external ADC architectures

• Performance and flexibility – integrated column-parallel sensors maximise throughput and minimise analog design effort, while external ADCs offer more freedom to trade resolution, speed and cost across different camera platforms.
• Analog complexity – integrated ADC sensors favour designs that focus on clean digital links; external multi-channel ADCs reward teams comfortable with high-speed analog routing and matching.
• Lifecycle and reuse – integrated solutions tie performance to specific sensor devices, whereas external ADC boards can be reused with multiple sensors and upgraded over time.

Key performance metrics for line-scan ADCs

Line-scan imaging performance depends on how well the ADC chain supports fixed pattern noise, random noise, dynamic range and pixel throughput. This section links image quality targets to ADC metrics so that resolution, ENOB and data rate requirements can be defined.

Fixed pattern noise versus random noise

Fixed pattern noise appears as stable column-to-column variations that repeat from frame to frame. Part of it comes from the sensor analog chain, and part comes from channel-to-channel offset and gain mismatch in the ADC path. These offsets create visible vertical stripes and banding in line-scan images.

Random noise is dominated by photon statistics, sensor readout noise and ADC noise. It varies from frame to frame and is seen as grain or speckle. For low-contrast defects and dark regions, random noise competes directly with the smallest useful grey-level steps.

Relating ENOB and SNR to inspection needs

Inspection requirements can be expressed as minimum defect size and contrast relative to the local background. These targets translate into the smallest grey-level change that must stand out above the combined noise floor of the sensor and ADC chain.

The effective number of bits determines how many stable grey levels are available between the noise floor and saturation. If the required defect contrast occupies only a few codes, ENOB must be high enough that random noise and FPN do not smear the grey-level steps beyond recognition.

Dynamic range between dark and bright scenes

Dynamic range defines how far the signal can swing from the noise floor up to saturation while still providing useful grey levels. In line-scan inspection, variations in illumination, reflectivity and contamination often stretch this range beyond ideal laboratory conditions.

Setting the ADC full-scale too low causes bright regions to clip and lose detail. Setting it too high compresses dark regions into a small portion of the code space, where few effective bits remain. A practical design reserves headroom for illumination drift while ensuring that the noise floor remains several codes above zero.

Line rate, throughput and ADC capability

Line rate and pixels per line combine into the total pixel rate that the ADC system must sustain. With multiple taps or channels, this pixel rate is divided across channels, but each ADC still needs sufficient sampling bandwidth to capture a stable pixel level within its acquisition window.

As line rate and resolution increase, it becomes harder to maintain high ENOB and dynamic range at the required throughput. This is why high-performance line-scan designs often rely on column-parallel conversion, multi-channel ADCs and careful clocking and reference design to keep noise and distortion under control at speed.

Front-end and timing for line-scan ADCs

The front-end between a line sensor and its ADC must deliver stable pixel voltages within each sampling window while staying inside the ADC input range. At the same time, pixel and line timing must align with ADC acquisition so that every pixel is captured once, with enough settle time and margin.

Front-end signal chain from sensor to ADC

A typical line-scan front-end routes sensor outputs through clamp or level-shift stages, correlated double sampling and driver amplifiers before reaching the ADC input pins. Each block must preserve bandwidth, limit noise growth and keep the signal within the ADC input common-mode and full-scale ranges.

• Clamp and level shift remove reset transients and move the signal into a suitable common-mode window for the ADC or driver.
• Correlated double sampling suppresses reset-related noise and reduces low-frequency offsets before conversion.
• Driver amplifiers provide the required swing, bandwidth and impedance to charge the ADC sampling network in the available acquisition time.

Differential drive is often preferred for high-speed line-scan systems because it rejects common-mode interference and improves robustness against digital switching noise and cable coupling. Single-ended drive can be acceptable only for lower line rates and tightly controlled layouts.

CDS and black-level calibration in the chain

Correlated double sampling usually sits close to the sensor, either inside the sensor or in the first analog stages. It measures a reset level and a signal level for each pixel and subtracts them to reduce reset noise and part of the fixed pattern offset.

Black-level calibration complements CDS by adjusting residual offsets after digitisation. Dark reference pixels or known dark areas are monitored, and per-channel offsets are trimmed in the digital domain. This is an effective way to correct column offsets caused by ADC channel mismatch without disturbing the analog chain.

Pixel clock, line timing and ADC sampling instant

Pixel clock edges define when new pixel values are presented at the front-end output. The ADC must open its sampling window after the front-end has settled and before the next pixel transition. Line-valid or similar signals group these pixels into a line, while exposure timing defines how long charge is integrated before readout.

For external ADCs, acquisition time must be long enough to charge the sampling capacitors through the front-end bandwidth. With simultaneous-sampling or MxADC devices, all active channels must sample within the same pixel window to avoid phase skew between taps and the resulting image artifacts.

Line-scan specific timing pressure

Line-scan cameras must complete readout of every pixel in a line within a short time window set by line rate and conveyor speed. This constraint pushes designs toward higher per-channel sampling rates, more parallel taps or sensor-integrated conversion so that the required pixel throughput can be met without sacrificing settling, ENOB or dynamic range.

Column-parallel vs multiplexed ADC choices

Line-scan cameras can distribute pixels across conversion channels in several ways. Channel topology determines how much throughput can be sustained, how difficult the board-level design becomes and how tightly fixed pattern noise can be controlled between columns.

Channel allocation patterns in line-scan cameras

Common channel allocation patterns fall into three groups: per-column converters integrated in the sensor, per-tap converters using external multi-channel ADCs and highly multiplexed architectures that reuse a small number of ADCs across many pixels.

Per-column ADC on-sensor

In a per-column architecture, each sensor column has its own small ADC. Pixel values are converted directly on the sensor and forwarded over digital buses or high-speed serial links. This maximises parallelism and shifts most of the complexity into the sensor device.

• Throughput scales with column count, allowing high line rates without extreme per-channel sampling rates.
• Board-level analog design is minimal; focus centres on power delivery and digital interfaces.
• Fixed pattern noise and column matching depend heavily on the sensor design; external calibration has limited reach.

Because converters are integrated, ADC architecture, resolution and upgrade paths are tied to the sensor vendor and sensor generation. Thermal design around the sensor becomes important when many column ADCs operate simultaneously at high speed.

Per-tap ADC with external multi-channel converters

Analog-output sensors expose multiple taps that each carry a portion of the line. These taps feed external multi-channel ADCs, so several columns or pixels share a single converter channel while maintaining parallel sampling across taps.

• ADC type, resolution and sampling rate can be selected independently from the sensor, enabling reuse of ADC boards across camera variants.
• More channels reduce per-channel sampling rate but increase board-level analog routing complexity and power dissipation.
• Channel-to-channel offset and gain mismatch must be managed with black-level calibration and digital trimming to avoid visible column artifacts.

Per-tap architectures suit systems that need flexibility in ADC choice, want to reuse front-end boards or must support multiple operating modes with different resolutions and line rates.

High multiplexing with single or few ADCs

Highly multiplexed architectures time-share one or a few ADC channels across many sensor columns using analog multiplexers or switching networks. This approach reduces converter count and surface area but pushes per-channel sampling rate and settling requirements.

• BOM cost and board area are low, which can be attractive for low-speed or entry-level systems.
• Switching transients, limited acquisition time and mux-induced coupling make it difficult to maintain ENOB and dynamic range at high line rates.
• This topology is usually reserved for modest resolutions and slower conveyors rather than demanding industrial inspection lines.

Choosing channel count and topology

Channel count is best derived from total pixel throughput and the maximum practical sampling rate per channel. Sensor type, acceptable fixed pattern noise and power budget then steer the choice between per-column, per-tap and high-multiplexing architectures.

High-speed interfaces: SLVS-EC and LVDS for line-scan

Line-scan heads must move converted pixel data from the sensor or ADCs into an FPGA or SoC at sustained high data rates. The choice between CMOS, LVDS and SLVS-EC interfaces determines lane count, power, cable design and integration effort on the controller side.

CMOS, LVDS and SLVS-EC output options

CMOS outputs are single-ended and simple to route on a short PCB, but simultaneous switching noise and higher voltage swings limit usable data rates and distance. CMOS interfaces are usually confined to low or moderate line rates and short head-to-controller spacing.

LVDS links provide differential signalling with low swing and constant current drive. They are well suited to medium to high data rates and cable or flex connections, and are supported by most FPGA families. The trade-off is higher static power per lane and more IO pins for a given total bandwidth.

SLVS-EC uses even lower voltage swings and is optimised for high-speed serial image data. For a given throughput, SLVS-EC generally needs fewer lanes and lower power than LVDS but requires tighter signal integrity control and appropriate receiver support in the FPGA or deserializer.

Planning lane count and data rate

For a chosen interface, lane count is derived from total pixel throughput and the maximum practical per-lane rate. Effective data rate depends on pixel resolution, pixel rate per tap, the number of parallel taps and any line coding or framing overhead in the link.

When estimating lane requirements, it is important to allow margin for encoding schemes such as 8b/10b and for control symbols, start-of-line markers and diagnostic traffic. Designing links close to their theoretical limit reduces eye margin and makes the system more sensitive to cable quality, skew and jitter.

FPGA and SoC integration aspects

Integration on the controller side starts with IO standards and bank voltages. LVDS and SLVS-EC receivers must match the signalling levels used in the line-scan head, and CMOS outputs must align with the selected bank voltage for reliable logic thresholds.

High-speed serial links require clock recovery or explicit forwarded clocks. Multi-lane configurations need lane alignment and deskew in the FPGA so that pixels are reconstructed in the correct order. Placement of transceiver banks and routing of differential pairs from the connector to the FPGA package strongly influence timing and signal quality.

Typical interface choices for line-scan heads

Compact or low-speed line-scan designs often use CMOS outputs into a nearby processor, while mainstream industrial systems adopt multi-pair LVDS into FPGA IO banks. High-resolution, high line-rate heads increasingly rely on SLVS-EC lanes connected to FPGA transceivers or dedicated deserializers to carry the required pixel data throughput with manageable pin count and power.

IC selection logic and example BOM for line-scan imaging

This section turns application requirements for line-scan cameras into concrete ADC and front-end specifications, then maps those specifications to an inquiry checklist and example bills of materials for typical inspection heads.

From application parameters to ADC requirements

Line-scan camera requirements are best converted into ADC specifications through a fixed sequence: pixel throughput, required contrast, usable dynamic range and preferred interface topology.

• Step 1 – Line rate and pixel count → per-channel throughput. For a given line rate and number of pixels per line, total pixel throughput defines the minimum aggregate sampling rate. Dividing this total by the number of taps or ADC channels gives the required sampling rate per channel.
• Step 2 – Defect size and contrast → ENOB / SNR range. Minimum defect size and detectable contrast translate into how many effective gray levels are truly usable. That requirement then maps to a practical ENOB range rather than a nominal resolution figure.
• Step 3 – Illumination, optics and sensor full-well → full-scale and dynamic range. The combination of light source, optics and sensor full-well capacity sets the expected signal swing at the sensor output. ADC full-scale and dynamic range should be chosen so that highlights do not clip while low-reflectance regions still sit well above the noise floor.
• Step 4 – Interface choice → on-sensor vs external ADC. Required throughput, allowable connector pin count and FPGA IO capabilities determine whether an on-sensor digital interface is sufficient or whether external multi-channel ADCs with LVDS or SLVS-EC outputs are needed.

Line-scan ADC inquiry checklist for vendors

When contacting ADC or sensor vendors for a line-scan design, it helps to send a structured inquiry that captures both performance and integration constraints.

Structure and channels

• Number of channels / taps and maximum sampling rate per channel.
• Usable input bandwidth per channel over temperature.
• Supported input types: single-ended, pseudo-differential or fully differential.

Precision, noise and matching

• Resolution in bits and typical ENOB at the intended input frequency.
• SNR and noise density under representative operating conditions.
• Inter-channel gain and offset mismatch and any factory calibration options.
• Fixed pattern related specifications, including column-to-column uniformity.

Front-end, reference and calibration

• Full-scale input range and allowed common-mode input window.
• Reference options: internal reference, external reference input and buffer requirements.
• Available gain and offset trim per channel and resolution of digital trims.
• Built-in calibration features such as background calibration or runtime correction.

Interface, synchronisation and test

• Output formats: CMOS, LVDS, SLVS-EC and corresponding lane configurations.
• Maximum bit rate per lane and supported frame or word alignment schemes.
• Sync and trigger pins: line sync, frame sync, triggers and built-in test pattern support.

Supply, package and thermal

• Required supply rails, tolerances and sequencing constraints.
• Power per channel in typical high-throughput operating mode.
• Package type, junction-to-ambient thermal resistance and thermal derating data.
• Operating temperature range and any derating of performance at extremes.

Example BOM 1 – High-speed web inspection head

A high-speed web inspection system with high line rate and fine defect sensitivity typically uses parallel taps and multi-channel high-speed converters with LVDS or SLVS-class outputs into an FPGA.

• Multi-channel high-speed ADC. Example: an octal 14-bit, ~65 MSPS pipeline ADC such as Analog Devices AD9257 (8-channel, 14-bit, up to 65 MSPS with serial outputs), suitable for multi-tap line-scan sensors.
• Differential ADC driver. Example: a wideband fully differential amplifier such as TI THS4509 to translate sensor or CDS outputs into the ADC’s differential input range while providing the required bandwidth margin.
• Voltage reference and buffer. Example: a low-drift 2.5 V precision reference such as TI REF5025 or a precision buffered reference family such as LTC6655, configured to drive the ADC reference pins with low noise and sufficient headroom.
• Clock generator / jitter cleaner. Example: an ultra low-noise clock jitter cleaner such as TI LMK04828 or related LMK0482x devices to provide low-jitter sampling clocks for the ADC and timing references for the FPGA.
• Supporting power and protection. Line-scan specific designs usually add low-noise LDOs for analog rails and transient protection around sensor and interface connectors; detailed protection choices are handled in EMC and protection focused topics.

Example BOM 2 – Mid-speed, cost-optimised line-scan head

For moderate line rates and less aggressive throughput requirements, power and BOM cost can be reduced by using multi-channel SAR converters with lower sampling rates and simpler clock trees.

• Multi-channel SAR ADC. Example: a 14-bit, multi-channel SAR converter such as TI ADS8678 (8-channel, 14-bit, up to 500 kSPS per channel) or similar devices, used where line rate and pixel count permit lower sampling speeds.
• Precision differential driver. Example: a low-power differential ADC driver such as ADA4932-1 to interface sensor or CDS outputs to the SAR ADC inputs while preserving DC accuracy and linearity.
• Low-power reference. Example: a low-drift 2.5 V precision reference device from families such as REF50xx or LTC6655, selected for low quiescent current to match the reduced throughput and power targets.
• Simple clocking. For SAR-based mid-speed systems, a low-jitter crystal oscillator or basic clock buffer can often meet requirements, provided aperture jitter remains compatible with the target ENOB at the chosen sampling frequency.

Engineering checklist and common pitfalls for line-scan ADC systems

Before releasing a line-scan camera or inspection head to production, it is useful to walk through an analog, timing and interface checklist and understand how common image artifacts map back to the signal chain.

Analog chain checklist

• Bandwidth margin. Front-end bandwidth, including sensor output stage, CDS and driver amplifier, should comfortably exceed the pixel bandwidth, often by a factor of three to five.
• Range and common-mode alignment. Driver output swing and common-mode point must sit inside the ADC input range under all operating temperatures and process conditions.
• Channel calibration. Per-channel gain and offset should be characterised and, where supported, trimmed digitally using dark and uniform-light frames to minimise column-to-column variation.
• Reference stability. Reference voltage and its buffer must remain stable across thermal gradients and dynamic loading so that full-scale and mid-scale do not drift line by line.

Clock and timing checklist

• Pixel versus sampling phase. ADC sampling instants must lie well within the pixel’s flat portion; aperture delay and jitter should not push sampling into pixel transitions.
• Line and frame synchronisation. Line valid, frame sync and trigger signals must align with pixel capture windows inside the FPGA or SoC to avoid partial or shifted lines.
• Clock jitter budget. Sampling-clock jitter should meet the ENOB target at the highest relevant input frequency; clock trees and PCB routing must support that budget.
• Multi-channel alignment. For systems with multiple converters or taps, inter-channel skew and latency must be measured and corrected so that stitched images remain consistent.

Interface and data integrity checklist

• Impedance and skew control. SLVS-EC and LVDS differential pairs should follow controlled impedance and skew constraints from device datasheets and layout guidelines.
• Eye margin. At the intended data rates, eye diagrams on representative links should show sufficient horizontal and vertical opening over expected cable lengths and temperatures.
• CRC and counters. Frame counters, line counters and optional CRC or parity checks should be used to detect bit errors, dropped lines and misaligned data.
• Grounding and cabling. Cable shields and ground references must be continuous between head and controller to minimise common-mode noise and susceptibility to interference.

Common image artifacts and debugging hints

Typical line-scan issues can be traced back to specific parts of the chain. Grouping symptoms by their appearance helps narrow down the root causes and speeds up troubleshooting.

Column stripes or vertical banding

• Check per-channel gain and offset calibration using dark and uniform-light frames.
• Verify that sensor column ADCs or external channels share the same reference and temperature environment.
• Exercise each ADC channel with a known test signal to confirm ENOB and offset independently from the sensor.

Horizontal banding or periodic brightness shifts

• Compare banding period with line rate, exposure timing and power-supply ripple frequencies.
• Capture dark frames to separate electronic noise patterns from illumination-related variations.
• Probe supply rails and clocks across a frame period to look for coupling at the same frequency as the artifacts.

Random bit errors, snow or corrupted lines

• Evaluate different cable types and lengths and observe error counters to see how eye margin changes.
• Reduce data rate or line rate and check whether the error rate drops, indicating signal integrity margins are too low.
• Use frame counters and CRCs to log which lanes or taps exhibit errors and correlate with routing or connector paths.

Recommended topics you might also need

• Pipeline ADC
• High-Speed Mid-Res (12–14 bit)
• T/H Front-End ADC
• Parallel / LVDS
• Clocking & Jitter
• Driver & Anti-Alias Filter

FAQs – Line-scan ADC and front-end design

This FAQ groups together common line-scan ADC questions about image quality, bandwidth and line rate, interface compatibility and selection mistakes, so that scattered issues do not distract from the main system design flow.