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EMC/ESD & Protection for ADC Inputs (TVS, RC, CMC, Surge)

EMC/ESD & Protection for ADC Inputs (TVS, RC, CMC, Surge)

← Back to:Analog-to-Digital Converters (ADCs)

ADC input EMC/ESD protection is a port-side energy and return-path design problem: divert stress to chassis/PE early, then control the residual at the ADC pin. A correct protection chain is verified not only by passing ESD/EFT/surge tests, but also by proving no resets, no data corruption, and no accuracy regression.

Definition: What is an ADC input EMC/ESD protection chain?

An ADC input protection chain is a system-level boundary that keeps external electrical stress away from the ADC pin while preserving measurement performance. It is not a single TVS part—it is the combined behavior of the pin limits, the front-end network, and the high-frequency return path.

What is being protected
  • ADC pin: absolute maximum ratings and internal clamp current limits.
  • Front-end network: TVS/clamps, series impedance, RC, CMC and connector parasitics.
  • Reference/return path: the physical loop that carries ESD/EFT current back to chassis/ground.
Stress types the chain must handle
  • ESD (contact / air): very fast edges; loop inductance dominates results.
  • EFT: repetitive fast transients; common-mode injection and ground bounce are frequent failure modes.
  • Surge: higher energy, longer duration; requires energy-handling and layered protection.
  • Cable induction: conducted/radiated coupling over long leads; often common-mode heavy.
  • Miswiring: sustained overvoltage / reverse connection; requires current limiting and survivability design.
Acceptance criteria (pass/fail)
  • No damage: no permanent parameter shift after stress.
  • No reset: system remains alive; no unintended brownout/reset events.
  • No data corruption: no uncontrolled codes, latch-up, or long recovery tails.
  • No accuracy loss: noise, distortion, offset and drift remain within the measurement budget.
ADC input protection chain: signal path vs energy return path Block diagram from cable and connector to TVS, secondary clamp, RC network and ADC pin, with separate arrows for signal path and ESD/EFT energy return path to chassis/ground. Signal path Energy / return path CABLE CONNECTOR PRIMARY TVS SECONDARY CLAMP RC LIMIT ADC PIN Abs max / Iclamp CHASSIS / PE FAST RETURN Pass = survive + no reset + clean data + no accuracy loss

Principle: Protection = energy management + return-path management

Effective input protection is a controlled energy route. Fast transients (ESD/EFT) do not “flow through a schematic” — they follow the lowest-impedance loop set by parasitics and return paths. A design passes when the stress current is diverted away from sensitive circuitry, limited to safe levels, and returned through a short, intentional path.

Three ideas that decide pass/fail
  1. Divert energy: send stress current to chassis/PE/ground plane near the connector, not across the ADC domain.
  2. Limit current: add series impedance (R/L/CMC) so clamp devices stay within safe peak current and di/dt.
  3. Control return loops: ns-scale events are dominated by loop inductance; the return path determines reset risk and data corruption.
Why accuracy must be part of “protection”

Protection parts are non-ideal: junction capacitance, leakage and nonlinearity can reduce bandwidth, worsen distortion, or introduce offsets. The correct chain is the one that meets both immunity and measurement integrity after verification.

Return loop comparison: good short loop vs bad loop through the ADC domain Two side-by-side diagrams comparing a short return loop to chassis near the connector versus a long loop that crosses the analog/ADC area, causing ground bounce and data corruption. GOOD LOOP Short return to chassis BAD LOOP Return crosses ADC area CONN TVS CHASSIS / PE RETURN CONN TVS ADC AREA GROUND BOUNCE Fast events follow loops: shorter return loops reduce resets and data corruption.

Design: Component selection and side effects (core)

Each protection part must be selected as a trade: immunity benefit vs measurement cost. A practical workflow is to lock every part using the same five fields: purpose → placement → key parameters → side effects → verification.

Series resistor (R)
  • Purpose: limit clamp current, add damping, isolate sampling charge pulses.
  • Placement: near the ADC-side network; often after secondary clamp and before/within RC.
  • Key parameters: value range, pulse capability, TCR, package/derating.
  • Side effects: thermal noise, slower settling, higher source impedance → sampling error.
  • Verify: step settling tail, THD vs amplitude/frequency, noise floor (and DC offset drift where relevant).
RC network
  • Purpose: reduce spikes, limit di/dt into clamps, provide damping against cable/trace ringing.
  • Placement: capacitor close to the ADC pin; resistor defines where energy is dissipated.
  • Key parameters: C type/voltage coefficient, leakage, tolerance, RC corner vs target bandwidth/settling.
  • Side effects: bandwidth reduction, slower settling, phase lag (group delay).
  • Verify: frequency response in the band of interest, recovery after burst events, accuracy regression (noise/THD/offset).
Clamp diodes / ESD array
  • Purpose: fast response for small energy spikes; protect the ADC pin from overshoot.
  • Placement: as close as possible to the protected node (ADC-side).
  • Key parameters: junction capacitance (Cj), leakage, dynamic resistance, channel matching (for differential).
  • Side effects: Cj + nonlinearity can increase THD; leakage can create DC offset/drift.
  • Verify: THD/SFDR vs frequency and amplitude, offset vs temperature, event-to-event repeatability.
TVS diode
  • Purpose: energy “catcher” for surge and higher stress events.
  • Placement: primary TVS at the connector; secondary small TVS only when pin-level limits require it.
  • Key parameters: VRWM, VBR, VC, dynamic resistance, Cj, pulse ratings/derating.
  • Side effects: capacitance and dynamic behavior can reduce bandwidth and worsen distortion; clamp level vs rating is a real trade.
  • Verify: residual clamp at the protected node, post-surge parameter shift, THD/noise regression.
Common-mode choke (CMC)
  • Purpose: block common-mode injection on long/shielded cables and reduce conducted noise entry.
  • Placement: near the connector, before noise couples into the board domain.
  • Key parameters: impedance vs frequency, DCR, saturation current, differential-mode impact.
  • Side effects: differential bandwidth/phase impact, DCR drop/heating, saturation reduces protection margin.
  • Verify: common-mode injection test, code stability under burst noise, in-band amplitude/phase impact.
GDT / MOV (primary surge stage)
  • Purpose: handle very high surge energy for outdoor/industrial long cables.
  • Placement: at the connector with a direct, short route to chassis/PE (primary diversion).
  • Key parameters: trigger/clamp behavior, lifetime under repeated hits, surge waveform rating.
  • Side effects: higher trigger voltage and slower response; requires a secondary fast clamp stage.
  • Verify: repeated surge aging check, residual voltage at the secondary stage, post-test accuracy regression.
Layered protection: primary surge stage at connector and secondary clamp near the ADC Block diagram showing cable to connector, primary stage with GDT/MOV/big TVS routed to chassis/PE, secondary clamp stage near ADC with ESD array/small TVS, followed by series R and RC before the ADC pin. CHASSIS / PE (FAST RETURN) CABLE CONNECTOR LAYER-1 GDT / MOV / BIG TVS LAYER-2 ESD ARRAY / SMALL TVS R RC FILTER ADC PIN Rule: big energy near connector; fast clamp and shaping near the ADC.

Design: Layout and grounding (protection-specific)

For fast events, pass/fail is dominated by physical loops. Protection works when the stress current is given a short route to chassis/PE and is prevented from crossing the ADC/analog domain. The rules below apply only to the protection path.

Layout rules that matter most
  • TVS-to-connector must be very short: the clamp is only effective if the loop area is minimized.
  • Direct return to chassis/PE: route stress current to chassis/PE (or the designated high-energy return) without crossing the ADC domain.
  • Define a protected boundary: keep the “dirty interface zone” separated from the “clean ADC zone”.
  • Place CMC near the connector: block common-mode injection before it enters the board domain.
  • Place RC near the ADC pin: reduce high-frequency injection at the protected node (capacitor closest).
  • Minimize vias on the protection return: parasitic inductance increases residual overshoot during ns events.
Quick self-check

If the stress-current arrow can be drawn across the analog/ADC area, the design will likely show resets or data glitches even when the schematic “looks right”.

PCB zoning for protection: interface dirty zone vs ADC clean zone Top-view PCB diagram showing a left-side interface zone with connector, TVS and common-mode choke routed to chassis/PE, and a right-side clean ADC zone with RC near the ADC pin. A highlighted dirty current loop is shown not crossing into the ADC area. DIRTY INTERFACE ZONE CLEAN ADC ZONE CONN TVS CMC PE ADC RC NEAR PIN BOUNDARY Keep stress-current loops inside the interface zone; do not let them cross into the ADC area.

Applications: Long cables and typical port scenarios

Long cables and external ports shift the problem from “pin voltage limits” to common-mode injection, surge energy, and return-path control. The port-side goal is to keep stress-current loops inside the interface zone while maintaining measurement integrity at the ADC pin.

Scenario A — 4–20 mA / voltage input modules (long lines)
  • Threat model: EFT bursts and surge energy; ground potential differences and common-mode noise are frequent.
  • Port boundary: define a “dirty interface zone” around the connector and energy parts; keep it separated from the ADC zone.
  • Typical placement: primary energy stage at the connector → CMC near the connector → secondary clamp + R/RC near the ADC pin.
  • Verification focus: no reset, no code bursts, and accuracy regression checks after EFT/surge.
Scenario B — Remote bridge sensors (cable coupling / ESD)
  • Threat model: cable coupling and ESD; small signals are sensitive to leakage and bias errors.
  • Port boundary: shield and stress current must return to chassis/PE without flowing through the ADC reference domain.
  • Typical placement: CMC near the connector for common-mode injection + low-leakage secondary clamp near the ADC.
  • Verification focus: offset and drift before/after stress, plus noise/distortion regression in the band of interest.
Scenario C — Industrial shielded cables with chassis grounding
  • Threat model: common-mode injection dominates; data glitches and resets often come from uncontrolled return loops.
  • Port boundary: terminate stress current to chassis/PE at the interface; keep the analog/ADC zone “clean”.
  • Typical placement: TVS returns directly to chassis/PE; CMC stays in the interface zone; RC stays at the ADC pin.
  • Verification focus: burst immunity and post-event accuracy regression (noise, THD, offset).
Scenario D — External chassis ports (surge / ESD)
  • Threat model: frequent ESD contact events and higher surge exposure; aging after repeated hits is common.
  • Port boundary: primary energy diversion must happen at the connector with a short return to chassis/PE.
  • Typical placement: layer-1 energy parts at the connector + layer-2 fast clamp near the ADC pin.
  • Verification focus: reset statistics, code integrity during events, and post-test performance regression.
Long cable port: shield, chassis grounding point, and distributed protection stages Diagram of a long shielded cable from remote sensor to connector, showing shield tied to chassis at the port, primary energy stage at connector, common-mode choke near connector, and secondary clamp plus RC near the ADC pin. CHASSIS / PE (RETURN) REMOTE SENSOR SHIELDED CABLE CONN PORT Shield → chassis LAYER-1 GDT/MOV/TVS CMC CL 2 RC PIN ADC Port-side pattern: shield to chassis at entry, energy stage at connector, shaping near the ADC pin.

IC selection logic: fields → risk mapping → inquiry template

“Protection works” is not a part-number claim. Selection must connect requirements to parameters, then to side effects, and finally to verification tests. The checklist below turns datasheet fields into a risk-aware inquiry.

ADC-side fields to request (pin boundary)
  • Absolute maximum input ratings (pin voltage limits) and any clamp current limits.
  • Internal ESD/clamp structure guidance and recommended external clamp connection.
  • Allowed source impedance vs sampling performance constraints.
  • Sampling capacitance / transient input current behavior (charge pulses).
  • Input clamp requirements (if external clamping is required for specified robustness).
Protection BOM inquiry fields
  • TVS: VRWM, VC, Cj, dynamic resistance, pulse ratings (waveforms/derating).
  • ESD array: channel count, Cj, leakage, clamping behavior and matching (for differential).
  • CMC: impedance vs frequency curve, DCR, saturation current, differential-mode impact.
  • GDT/MOV: trigger/clamp behavior, surge level, lifetime/aging under repeated hits.
Risk mapping (fields → failure modes)
  • Cj → THD/bandwidth impact (especially for wideband inputs).
  • Leakage → offset and drift (especially for small-signal and bridge sensing).
  • Series R → settling limit and sampling error (SAR charge pulse sensitivity).
  • Return path → EMC behavior (resets, code bursts, long recovery tails).
Inquiry template (copy/paste)
Environment: cable length ___ m, shielded (Y/N), chassis/PE available (Y/N), target stress: ESD ___, EFT ___, surge ___.
ADC boundary: abs max input ___, clamp current limit ___, allowed source impedance ___, sampling cap/charge behavior ___.
Goal: no damage/no reset/clean data/no accuracy loss; provide recommended protection chain and placement.
Deliverables: recommended BOM with key parameters, expected side effects (Cj/leakage/settling), and suggested verification tests.
Selection flow: requirements to parameters to side effects to verification Four-step flow chart connecting EMC requirements to component parameters, mapping side effects to measurement risks, and ending with verification tests for immunity and accuracy. 1) NEEDS ESD / EFT / SURGE Cable / Shield Chassis/PE 2) FIELDS V C / Cj / Z(f) Leakage / DCR Abs max / Iclamp 3) RISKS Cj → THD/BW Leak → Offset R → Settling Return → EMC 4) TEST Reset stats Code integrity THD / Noise Offset / Drift Selection becomes robust when fields are mapped to risks and validated by tests.

Engineering checklist: ADC input EMC/ESD protection (port-side)

Use this checklist to lock the port-side protection chain as an engineered deliverable: requirements → layered placement → return-path control → accuracy side effects → post-test regression. Each item is written to be checked against a schematic, PCB, and test report.

A) Protection-level inputs (requirements intake)
  • ☐ Target levels defined: ESD (contact/air) ___ / ___, EFT ___, Surge ___.
  • ☐ Cable conditions defined: length ___ m, shielded (Y/N), chassis/PE available at port (Y/N).
  • ☐ Port exposure defined: external chassis port (Y/N), hot-plug/miswire risk (Y/N).
  • ☐ ADC pin boundary collected: abs max, clamp current limit, allowed source impedance, sampling charge behavior.
  • ☐ Deliverable evidence: a one-page requirements sheet tied to the above fields.
B) Layered protection and placement (Layer-1 / Layer-2)
  • ☐ Layer-1 energy stage is at the connector: GDT/MOV/big TVS (as required by surge energy).
  • ☐ Layer-1 return is direct to chassis/PE with a short, low-inductance path.
  • ☐ Layer-2 fast clamp is near the protected node (ADC-side): ESD array / small TVS / clamp diodes.
  • ☐ Series R and RC shaping are near the ADC pin (capacitor closest to pin).
  • ☐ CMC (if used) is in the interface zone, before common-mode noise enters the board domain.
  • ☐ Deliverable evidence: top-layer PCB screenshot with Layer-1/Layer-2/RC/CMC labeled.
C) Return-path control (what decides resets and data glitches)
  • ☐ Stress-current loop stays inside the interface (dirty) zone; it does not cross the ADC/analog reference domain.
  • ☐ TVS/GDT/MOV return routing is short/straight; minimum vias; minimum loop area.
  • ☐ Shield termination (if present) is controlled at the port to chassis/PE, not into the ADC reference plane.
  • ☐ A clear boundary exists: “dirty interface zone” vs “clean ADC zone”.
  • ☐ Deliverable evidence: annotated “signal path” vs “dirty return loop” diagram on the PCB view.
D) Accuracy side effects (Cj / leakage / R / settling)
  • ☐ Clamp capacitance (Cj) impact verified: bandwidth and THD/SFDR regression vs frequency and amplitude.
  • ☐ Clamp leakage impact verified: offset drift vs temperature and low-frequency noise regression (where relevant).
  • ☐ Series R impact verified: step/settling tail meets the sampling window and measurement error budget.
  • ☐ RC impact verified: in-band magnitude/phase (or equivalent) meets measurement requirements.
  • ☐ Deliverable evidence: “before/after protection” plots or table with pass/fail thresholds.
E) Post-test regression plan (function + accuracy)
  • ☐ No damage: no permanent parameter shift after ESD/EFT/surge exposure.
  • ☐ No reset: reset probability meets the defined threshold under the target test levels.
  • ☐ No data corruption: no burst codes, latch-up, or long recovery tails during/after events.
  • ☐ No accuracy loss: noise/distortion/offset/drift remain within the measurement budget after tests.
  • ☐ Deliverable evidence: test log + “before/after” metrics table + aging/repeat-hit note (if applicable).
Checklist overview for port-side ADC input EMC/ESD protection A visual checklist card showing five groups: Needs, Layers, Return, Accuracy, and Regression, each with check icons and minimal keywords. Engineering checklist (port-side) Needs → Layers → Return → Accuracy → Regression NEEDS ☐ IEC levels ☐ Cable / shield ☐ ADC pin limits LAYERS ☐ Layer-1 @ conn ☐ Layer-2 @ pin ☐ RC near ADC RETURN ☐ Chassis/PE ☐ Short loop ☐ No cross-zone ACCURACY ☐ Cj → THD/BW ☐ Leak → offset ☐ R → settling REGRESSION ☐ No damage ☐ No reset ☐ No corruption
Pass/fail decision tree for port-side EMC/ESD protection A small decision tree that branches on reset, code glitches, THD regression, and offset drift, pointing to the protection loop, placement, Cj, and leakage checks. TEST RESULT RESET? CODE BURST? ACCURACY HIT? Check return loop TVS → chassis/PE Check placement CMC/RC near target Split the risk Cj vs leakage THD/BW Lower Cj OFFSET/DRIFT Lower leakage PASS → SHIP EVIDENCE PACK Decision focus: return loops (resets), placement (code bursts), Cj/leakage (accuracy).

Reference BOM pool (example part numbers)

These part numbers are category representatives for inquiry and comparison. Final selection must match the port working voltage, target waveforms/levels, allowed input capacitance/leakage, and thermal/pulse derating for the chosen standard.

Layer-2 fast clamps (near ADC / protected node)
  • Nexperia PESD5V0X2UT — dual-line ESD protection diode (typical “fast clamp” representative).
  • Littelfuse SP0502BAHT — 2-channel TVS diode array (typical multi-line clamp representative).
  • Selection notes: prioritize low Cj for wideband/low-THD inputs; prioritize low leakage for small-signal/bridge inputs.
Common-mode choke (CMC) (interface zone, near connector)
  • TDK ACM2012-900-2P-T002 — 2-line common-mode filter (impedance curve representative).
  • Murata DLW5BSM351SQ2L — 2-line common-mode choke (DCR and impedance curve representative).
  • Selection notes: verify Z(f) in the problem band; check DCR/heating; check saturation margin under transients.
Layer-1 energy stage (connector side, direct to chassis/PE)
  • Bourns 2038-15-SM-RPLF — 3-electrode SMT GDT (high-energy diversion representative).
  • Vishay SMBJ5.0CA (SMBJ series) — TVS diode family representative (select the correct voltage grade for the port).
  • Selection notes: Layer-1 must prioritize surge energy handling and a short chassis/PE return; Layer-2 must control the residual at the ADC pin.
MLV/MOV representative (port-side shunt for specific cases)
  • Bourns CGA0603MLC-05E — MLV series representative (verify lifecycle/NRND status and choose current equivalent if needed).
  • Selection notes: confirm trigger/clamp behavior and aging under repeated hits; do not rely on this alone for fast pin protection.

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FAQ: ADC input EMC/ESD protection (port-side)

These FAQs focus on port-side protection only: clamps/TVS/CMC/R/RC, shield-to-chassis behavior, return-path mistakes, and post-test regression. Each answer includes a practical decision rule and a verification action.

When does TVS/ESD capacitance (Cj) start to noticeably hurt THD or bandwidth?
  • Decision rule: Cj becomes “noticeable” when it creates measurable gain loss or distortion increase in the target band compared to the unprotected baseline.
  • Why: Cj forms a frequency-dependent load; with nonlinearity, it can raise THD/SFDR for wideband inputs.
  • Actions: move high-Cj parts to Layer-1 (connector side) and keep Layer-2 clamps low-Cj near the ADC; avoid “one big TVS everywhere”.
  • Verify: A/B compare (with/without protection) for magnitude vs frequency and THD/SFDR vs frequency and amplitude.
How large can the series resistor be before a SAR ADC fails to settle?
  • Decision rule: R is too large if worst-case step/charge-pulse recovery does not settle within the acquisition window to the required accuracy.
  • Why: SAR sampling draws charge pulses; larger source impedance increases settling time and sampling error.
  • Actions: reduce R, split R (small near pin + additional upstream), or reduce C at the pin while keeping clamp current limits satisfied.
  • Verify: measure step settling tail using worst-case code transitions or a fast step stimulus; confirm error inside the acquisition window.
Should clamp diodes return to AVDD or to ground?
  • Decision rule: clamp returns must keep stress current out of sensitive rails and references; the best choice is the return node that remains “stiff” during the event.
  • Why: clamping to AVDD can inject current and lift/pollute the rail; clamping to ground can create ground bounce if the return loop is not controlled.
  • Actions: prefer a defined, low-inductance return (often chassis/PE for Layer-1, local controlled return for Layer-2); avoid routing clamp current through ADC reference grounds.
  • Verify: during ESD/EFT, monitor rail disturbance, reset statistics, and code integrity; then run post-event accuracy regression.
Should the common-mode choke (CMC) be at the connector or near the ADC?
  • Decision rule: place the CMC where common-mode noise enters—typically in the interface zone near the connector.
  • Why: CMC is most effective before the common-mode current couples into board domains and return paths.
  • Actions: keep the CMC in the dirty zone; keep RC near the ADC pin; if “only works near ADC”, re-check return-path control and zoning.
  • Verify: compare common-mode injection sensitivity with CMC moved between locations; track code bursts and recovery tails.
For long shielded cables, should the shield be grounded at one end or both ends?
  • Decision rule: the shield must provide a controlled high-frequency return at the port; uncontrolled multi-point returns can create unwanted current paths.
  • Why: a shield is a return conductor for interference; where it bonds determines whether stress current stays in the interface zone.
  • Actions: bond shield to chassis at the port with a short path; evaluate both-end bonding only when chassis potential differences and loop currents are controlled.
  • Verify: run injection/ESD tests with the intended bonding; compare data stability and reset statistics.
ESD passes but ADC data jumps—what is the most common return-path mistake?
  • Top suspects: (1) TVS return loop too large, (2) stress current crosses the clean ADC/analog zone, (3) Layer-2 clamp/RC too far from the pin.
  • Why: ns events are loop-dominated; a “correct schematic” can fail if the physical loop injects noise into reference/ground.
  • Actions: shrink TVS-to-chassis loop, enforce dirty/clean boundary, move Layer-2 and the pin capacitor closer to the ADC.
  • Verify: measure code burst rate and recovery tail during ESD events before/after layout changes.
EFT bursts reset the MCU—what port-side analog input changes help most?
  • Decision rule: treat EFT as a fast, repeated injection problem—reduce coupling into the clean zone and provide a short diversion path at the port.
  • Why: EFT is rich in high-frequency content; uncontrolled returns can disturb digital rails and reset lines through ground/plane coupling.
  • Actions: ensure Layer-1 diversion to chassis/PE at the connector; add/relocate CMC in the dirty zone; keep RC at the ADC pin to reduce injection.
  • Verify: collect reset statistics under EFT and confirm code integrity and post-test accuracy regression.
After surge tests, accuracy drifted—what parts most often age or degrade?
  • Common candidates: TVS (leakage shift), MOV/MLV (aging), series resistors (value shift), clamp arrays (leakage increase).
  • Why: passing “no damage” does not guarantee “no parameter shift”; some protectors degrade gradually after repeated hits.
  • Actions: re-check leakage and offset paths; consider splitting energy between Layer-1 and Layer-2; ensure derating for waveforms and temperature.
  • Verify: compare pre/post surge for offset, drift vs temperature, noise floor, and THD/SFDR.
How to run a regression test for “protection side effects”?
  • Minimum set: (1) magnitude response in-band, (2) THD/SFDR vs frequency, (3) offset/drift vs temperature, (4) settling tail check (if SAR).
  • Why: protection changes input loading (Cj), bias errors (leakage), and acquisition dynamics (R/RC).
  • Actions: run A/B comparisons (with/without protection) and then pre/post stress comparisons (before/after ESD/EFT/surge).
  • Verify: store results in a single table with pass/fail thresholds tied to the measurement budget.
When is a primary GDT/MOV stage needed (not just TVS/ESD arrays)?
  • Decision rule: use a Layer-1 energy stage when the port faces high surge energy (industrial/outdoor long cables, external chassis ports, higher surge targets).
  • Why: small clamps are fast but cannot absorb large energy repeatedly; Layer-1 prevents energy from reaching the ADC-side domain.
  • Actions: place Layer-1 at the connector with direct chassis/PE return; keep Layer-2 fast clamps near the ADC to control residual overshoot.
  • Verify: confirm residual clamp at the protected node and run post-surge regression for leakage/offset/THD/noise.
Why must the Layer-2 clamp and the pin RC be close to the ADC, and what is “close”?
  • Decision rule: “close” means the clamp/RC loop area is minimized and the return is controlled; performance is determined by geometry during ns events.
  • Why: if the clamp is far away, the overshoot exists at the ADC pin before the clamp conducts effectively.
  • Actions: place the clamp and the capacitor at the protected node with short traces and minimal vias; keep the dirty return loop out of the clean zone.
  • Verify: compare ESD/EFT behavior (code bursts and recovery tails) with the same parts moved closer vs farther.
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