Custom Brown-In / Brown-Out Power-Valid Window Design
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Build a measurable, glitch-tolerant Brown-In/Brown-Out power-valid window using dividers, references, and comparators—so reset/enable decisions stay correct under slow ramps, ripple, temperature drift, and leakage. The focus is not a “generic supervisor replacement,” but a verifiable threshold budget (VTH+/VTH−), controlled hysteresis/delay, and a bench test flow that matches worst-case reality.
What this page solves (Brown-In/Out as a robust power-valid window)
Brown-In/Brown-Out turns “is the supply truly valid?” into a measurable hardware decision: a defined threshold window (with hysteresis) plus timing rules (filtering/blanking/delay) that stays stable under slow ramps, ripple, and short glitches.
Why “MCU ADC only” often fails in the field
- Timing responsibility mismatch: a sampled reading cannot guarantee the earliest safe reset/disable point during a fast droop; last-gasp save windows become non-deterministic.
- Noise responsibility mismatch: ripple + ground bounce + slow ramps cause repeated threshold crossings; software debouncing adds delay but still cannot prove “no chatter.”
- State responsibility mismatch: during partial-rail start-up, the MCU domain itself may not behave consistently; using an unstable domain to decide “power-valid” is structurally fragile.
What a custom Brown-In/Out decision typically drives
RESET
Forces the system into a known-safe state. Assert quickly on Brown-Out; release only after Brown-In + stability time.
PWR_GOOD / PGOOD
Signals downstream rails, sequencers, or firmware that the supply is inside the valid window and stable enough to proceed.
EN_GATE / ENABLE
Prevents “restart oscillation” by combining hysteresis and release delay; avoids rapid on/off cycling near threshold.
FAULT_LATCH
Captures “power invalid happened” for logging or lockout logic, even if the supply later recovers.
Common failure modes → what the hardware window fixes
- Slow ramp → multi-toggling: add VTH+/VTH− separation (hysteresis) so noise cannot flip the decision repeatedly.
- Ripple/ground bounce near threshold: combine hysteresis with glitch filtering and a defined release delay.
- Start-up wobble / overshoot: use blanking (ignore interval) until reference and rails are settled.
- Fast droop: design for fast assert on Brown-Out so downstream logic has a deterministic safety boundary.
Definitions: Brown-In, Brown-Out, and the valid-power window
Reliable power-valid behavior requires defining thresholds and timing responsibilities as measurable objects: VTH+ / VTH−, hysteresis width, and when outputs are allowed to change state.
Core events (defined as behavior, not as a part number)
- Brown-In event: VDD rises past VTH+ and remains stable long enough to satisfy the chosen filter/blanking/delay rule; the system may enter “valid.”
- Brown-Out event: VDD falls past VTH−; the system must leave “valid” and typically asserts RESET quickly to avoid undefined execution.
- Hysteresis window: VHYS = VTH+ − VTH−. This is the primary anti-chatter mechanism under slow ramps and ripple.
- Optional compliance window: UV + OV boundaries can be added (undervoltage + overvoltage), but this page stays centered on power-valid and reset behavior.
Do not mix these signals: responsibility boundaries
POR (Power-On Reset)
Internal reset behavior inside a chip. Often non-configurable and not a substitute for a system-level power-valid window.
UVLO (Under-Voltage Lockout)
Protection gating for a power stage/driver. Focused on safe operation limits, not on clean sequencing of the whole system.
PGOOD / Power-Valid
A system coordination signal: “the rail is inside the valid window and stable.” Usually deasserts fast, asserts after delay.
RESET
A system state-control signal. Assert must be deterministic; release should be conditioned on Brown-In + stability time.
Naming that will be reused in later chapters
- VTH+: rising threshold (enter valid)
- VTH−: falling threshold (leave valid)
- VHYS: hysteresis width (anti-chatter margin)
- t_blank: ignore interval after start-up (optional)
- t_delay: release delay after Brown-In
- t_glitch_reject: shortest glitch that must be ignored
Topologies: comparator + divider + reference (and when custom beats a supervisor)
Start by choosing a topology that matches the system constraints (rail behavior, input common-mode comfort, and output semantics). The goal is a power-valid window that is stable under ramps/ripple and produces deterministic RESET/PG/EN behavior—without depending on a fixed supervisor threshold.
Topology selection (answer these before picking parts)
- Boundary type: undervoltage only (UV) or a compliance window (UV + OV).
- Low-rail behavior: will either comparator input operate near GND/VDD during ramp and droop without crossover surprises?
- Output semantics: is the signal a pure indicator (PGOOD) or a state-control line (RESET/EN) that must avoid restart oscillation?
- Noise reality: is the rail noisy or slow-ramping (buck ripple, long cables, inrush wobble) such that hysteresis/filtering is mandatory?
Three practical forms (same building blocks, different “comfort zones”)
A) VDD divider → compare to Vref (most common)
- Use when: a single rail needs Brown-In/Brown-Out thresholds with simple, predictable math.
- Main risks: very high divider impedance magnifies bias/leakage errors; ripple can cause chatter without VHYS/filtering.
- What gets calculated next: VTH from Vref and R ratio, then worst-case bounds from tolerances.
B) Vref divider → compare to VDD (for low-rail/common-mode comfort)
- Use when: comparator input behavior is more comfortable with VDD as the compared node under ramp/droop.
- Main risks: start-up sequencing (Vref ramp) can dominate behavior; blanking/delay rules become essential.
- What gets calculated next: the same VTH targets, but checked against input common-mode limits during transitions.
C) UV + OV window (two thresholds)
- Use when: the system must be valid only inside a compliance range (too-low and too-high are both faults).
- Main risks: boundary interaction near the limits; hysteresis and timing must be defined so the system does not “ping-pong.”
- What gets calculated next: two sets of worst-case bounds (UV and OV) and the resulting “guaranteed valid” region.
When custom beats a fixed supervisor (engineer-controlled knobs)
- Continuous thresholds: set exact Brown-In/Brown-Out points (not just fixed bins).
- Deterministic timing: define blanking and release delay for start-up wobble and ripple.
- Explicit glitch immunity: specify the shortest glitch to reject (t_glitch_reject) by design, not by hope.
- System logic composition: combine RESET/PG/EN/FAULT behaviors (including latching) while staying within measured margins.
- Power vs noise trade: choose divider impedance and reference/filtering to meet both quiescent current and chatter limits.
Threshold math: divider ratios, Vref, and tolerance → worst-case thresholds
A custom Brown-In/Brown-Out window is only as good as its worst-case thresholds. The objective is not a pretty nominal value, but a guaranteed range (VTH_lo to VTH_hi) across reference accuracy, resistor ratio error, comparator offset/drift, and divider-node bias/leakage effects.
Baseline equation (Topology A: VDD divider → Vref)
Divider node:
Vdiv = VDD · R2/(R1+R2)
Trigger condition (ideal):
Vdiv = Vref
Nominal threshold (ignoring bias/leakage):
VTH ≈ Vref · (1 + R1/R2)
Use the same structure for Brown-In and Brown-Out by assigning two effective thresholds (VTH+ and VTH−), typically via hysteresis.
Error terms that move the threshold (must be budgeted)
Reference accuracy & TC
Vref initial error and drift scale into VTH through the divider ratio. Treat as a gain-like contribution.
Comparator offset & drift (Vos)
Vos behaves like an additive threshold shift at the input. Worst-case offset matters more than typical.
Bias current × source impedance
Input bias/leakage across the divider’s Thevenin impedance creates a voltage error at Vdiv, shifting VTH. This is why “too-large resistors” can break accuracy.
Resistor ratio tolerance & TC
Ratio error changes (1 + R1/R2) directly, acting like a gain-like term. Matching/TC tracking can dominate long-term drift.
Worst-case workflow (what “deterministic” means)
- Set targets: VTH_rise (Brown-In) and VTH_fall (Brown-Out) required by the system timing and safety needs.
- Choose nominal ratio: select Vref and R1/R2 so nominal thresholds land near the targets with headroom.
- List error terms with sign: Vref accuracy/TC, Vos/drift, bias×Rth, ratio tolerance/TC.
- Combine to get bounds: compute VTH_lo and VTH_hi (for rise and fall) and identify the dominant driver.
- Add guardband: ensure the guaranteed valid region still meets firmware and power-sequencing requirements.
Engineering fields (copy-ready schema for documentation and vendor questions)
| Category | Fields | Outputs |
|---|---|---|
| Targets | VTH_rise (Brown-In), VTH_fall (Brown-Out), required hysteresis VHYS, temperature range | Guaranteed valid window (design intent) |
| Electrical | Vref (accuracy + TC), comparator Vos (max + drift), bias/leakage, R1/R2, Rth_source | VTH_lo / VTH_hi (rise and fall) |
| Tolerances | Resistor ratio tolerance + TC, reference drift, assumed leakage/contamination class | Worst-case margins to firmware timing |
| Results | Dominant error term, guardband applied, bench test plan hooks | Pass/fail criteria for VTH and timing |
Designing hysteresis (VHYS): stop chatter under slow ramps/noise without moving the window too much
Hysteresis is the primary anti-chatter mechanism when VDD ramps slowly or carries ripple/ground bounce. The design goal is a minimum VHYS large enough to prevent repeated toggling, while keeping the valid-power window inside the required margins after worst-case tolerances.
Why slow ramps chatter near the threshold
- Noise (random): input-referred noise moves the divider node across the decision point multiple times during a slow crossing.
- Ripple (deterministic): buck ripple can repeatedly cross a single threshold; VHYS separates the “enter” and “leave” boundaries.
- Ground bounce / return currents: reference and comparator ground shift during load transients, acting like a transient threshold error.
How hysteresis is implemented (positive feedback)
A feedback resistor (Rfb) from the comparator output back to the divider node creates two different effective thresholds:
VTH+ (rising/enter-valid) and VTH− (falling/leave-valid). This converts “one noisy crossing” into a stable state machine:
the output must move by at least VHYS = VTH+ − VTH− (referred to VDD) to change state.
Hysteresis must be referenced to VDD (not just the divider node) and must be included in the threshold budget so the valid window is not squeezed below requirements.
Sizing VHYS (data-driven rules)
1) Minimum VHYS to stop toggling
Budget disturbances at the divider node (or input-referred):
Vdist ≈ k·noise_rms + ripple_pk + ground_bounce_pk
and enforce:
VHYS_node ≥ Vdist
Typical engineering choice: k = 4–6 for robust coverage of random noise.
2) Convert hysteresis to the VDD side (what the system really sees)
Use the divider gain to translate node hysteresis to VDD. As a first estimate:
VHYS_VDD ≈ VHYS_node · (1 + R1/R2)
Then solve VTH+ and VTH− explicitly with the chosen Rfb and output levels (VOH/VOL).
3) Do not squeeze the valid window (worst-case constraint)
After applying tolerances (Vref, ratio error, Vos, bias/leakage), ensure the guaranteed window still meets system margins:
(VTH+_hi − VTH−_lo) ≥ margin_min
If the window is squeezed, reduce VHYS or raise the margin by adjusting targets, divider ratio, or noise sources (layout/decoupling).
Practical math hook (Topology A + Rfb): compute VTH+ and VTH−
With R1 to VDD, R2 to GND, and Rfb from output to the divider node, the divider-node voltage is:
Vdiv = (VDD/R1 + Vout/Rfb) / (1/R1 + 1/R2 + 1/Rfb)
Trigger at Vdiv = Vref, giving:
VTH(Vout) = Vref·(1 + R1/R2 + R1/Rfb) − (R1/Rfb)·Vout
- VTH+ = VTH(Vout = VOL) (rising boundary)
- VTH− = VTH(Vout = VOH) (falling boundary)
- VHYS_VDD = (R1/Rfb)·(VOH − VOL)
Glitch immunity: RC filtering, blanking, and reset delay (power ramps are not ideal)
Real rails contain short glitches and start-up wobble. Glitch immunity is designed by specifying what must be ignored (t_glitch_reject), how fast protection must respond (t_response_max), and when release is allowed (t_blank and t_delay).
Three tools (each trades something different)
Input RC (at divider / comparator input)
Rejects fast spikes by slowing the sensed node. Trade-off: adds delay and increases bias/leakage sensitivity through the node impedance.
Output delay (release-only shaping)
Delays RESET/PGOOD release without changing the thresholds. Best for start-up wobble; keep Brown-Out assertion fast.
Blanking (ignore interval after power-up)
Forces “not valid yet” for the first N ms (or until references are ready). Most effective against inrush ringing and early instability.
Define measurable criteria (design to these, then verify)
- t_glitch_reject: shortest glitch that must not change RESET/PG/EN state.
- t_response_max: maximum allowed delay to assert on a real Brown-Out (protection boundary).
- t_blank: interval after power-up during which outputs remain forced safe (ignore unstable rail).
- t_delay: time after VDD passes VTH+ (and remains valid) before releasing RESET.
Engineering hooks (turn specs into component values)
Input RC: reject a glitch by limiting node movement
For a step-like glitch of amplitude Vstep and width t_g, the filtered change is approximately:
ΔV(t_g) ≈ Vstep · (1 − e^(−t_g/τ))
To reject t_glitch_reject, require:
ΔV(t_glitch_reject) < Vmargin_to_threshold
But τ is capped by response-time requirements
A larger τ improves glitch rejection but slows detection. Enforce the protection constraint:
t_response(τ) ≤ t_response_max
Use release delay/blanking to handle start-up wobble while keeping Brown-Out assertion fast.
Recommended semantics for RESET
- Brown-Out: assert RESET fast (minimize filtering on the assert path).
- Brown-In: release RESET only after VDD > VTH+ and stable for t_delay (and after t_blank if used).
Start-up & brown-out pitfalls: reference start time, output state, and “partial-rail” behavior
H2-9 · Input conditioning & protection: clamp/RC/series-R without killing speedMost Brown-In/Brown-Out failures happen during non-ideal rails: references are not settled, inputs sit in partial-rail regions, and outputs are not yet deterministic. This section lists board-level pitfalls and converts them into simple release/blanking rules that can be verified on the bench.
Pitfall 1: Vref start/settle makes thresholds non-deterministic
- Before Vref is ready: the effective VTH can drift quickly; comparator decisions can be wrong even if the divider ratio is correct.
- Start-up wobble: soft-start, inrush, and load steps can cross VTH repeatedly while Vref accuracy is still improving.
- Rule: keep the system in a forced-safe state until Vref_ready and the blanking interval completes.
Pitfall 2: output “default state” depends on OD vs push-pull
Output type determines whether RESET/PG/EN is defined under partial rails:
- Open-drain (OD): requires a pull-up to define “high”; rise time can be slow under low Vpull or large C_load.
- Push-pull (PP): clean edges when powered, but can be unpredictable if VDD is below the output stage’s controlled region.
- Rule: define a guaranteed-safe state (RESET asserted / EN off) until the output is known-valid.
Pitfall 3: VICR crossover at low rail can invert or distort behavior
- Partial-rail region: during start-up, both Vdiv and Vref sweep from 0 V through regions where the input stage may not be linear.
- Crossover: some inputs change internal topology near the rails, causing unexpected offsets or temporary inversion.
- Rule: confirm VICR coverage across the entire ramp (0 → target) for both inputs, or enforce blanking until the inputs are inside a known-good region.
Pitfall 4: filtering and delay can slow RESET assertion on brown-out
A common failure is designing for a clean release but accidentally delaying protection:
- Brown-Out requires fast assertion: RESET should assert quickly when VDD leaves the valid window.
- Input RC side effect: a large τ can make the sensed node decay slower than VDD, delaying fault detection.
- Rule: assert fast, release slow — keep the assert path minimal; use blanking + delay for release stability.
Minimum design fields (copy-ready)
- Vref_ready: start/settle to accuracy (max)
- Comparator t_on: output becomes valid (if specified)
- VICR vs VDD: ramp coverage, crossover zone
- RESET assert: t_assert_max on brown-out
- Release policy: t_blank, t_delay
Output interfacing: RESET/PGOOD/EN, OD vs push-pull, and multi-rail OR’ing
Output wiring determines whether the Brown-In/Brown-Out decision becomes a clean system behavior or a restart loop. This section focuses on deterministic RESET/PGOOD/EN semantics, OD vs push-pull tradeoffs, and multi-rail signal combining without expanding into complex logic pages.
OD vs push-pull: decide by system wiring needs
Open-drain (OD)
- Best for: cross-voltage domains, wired-OR combining, distributed fault sources.
- Design burden: Rpull sets rise time and static power; ensure VOL at I_sink worst-case.
Push-pull (PP)
- Best for: clean edges, no pull-up, direct local logic when voltage domains match.
- Design burden: level shifting for cross-domain; confirm controlled output under low-rail start-up.
Typical connections (RESET / PGOOD / EN)
- MCU RESET: keep Brown-Out assertion fast; release only after VDD > VTH+ and stable for t_delay (and after t_blank if used).
- PGOOD (indicator): release shaping is acceptable; ensure no false-high during partial rails.
- EN (control): avoid ping-pong cycling; EN must cooperate with VHYS and delay rules so the rail cannot repeatedly restart at the boundary.
Multi-rail combining (principles only)
- Any-rail fault → assert RESET: OD wired-OR is the simplest implementation (any source pulls low).
- All-rails valid → release: release only when each rail comparator indicates valid, then apply delay (avoids boundary ping-pong).
- Wiring constraint: the combined line must meet rise-time and VOL requirements with worst-case C_load and I_sink.
Pull-up resistor sizing (minimum fields + two checks)
| Field | Meaning | Used for |
|---|---|---|
| Vpull | Pull-up domain voltage | Static current and logic-high level |
| I_sink_min | Worst-case OD sink capability | Ensure VOL under load |
| C_load | Trace + pin + wiring capacitance | Rise-time estimate |
| tr_target | Max acceptable rise time | Avoid slow “analog high” |
| VOL_target | Desired low level margin | Guarantee logic-low |
Check 1: ensure the line can be pulled low
Enforce:
Rpull ≥ (Vpull − VOL_target) / I_sink_min
Check 2: meet rise-time target
Approximate:
tr ≈ 2.2 · Rpull · C_load
and require:
tr ≤ tr_target
Verification: how to test thresholds, hysteresis, and glitch rejection on the bench
Bench verification should prove three outcomes: VTH+ / VTH− match worst-case targets, outputs do not chatter under ripple/noise, and glitches shorter than the target rejection time do not change RESET/PGOOD/EN behavior.
Test case 1 — Slow ramp (extract VTH+ and VTH−)
Stimulus
- Program a linear VDD ramp (rise and fall). Use the slowest realistic ramp to stress boundary behavior.
- Repeat 10+ cycles to capture spread (do not accept a single crossing as “the threshold”).
Observe
- Scope CH1: VDD (at DUT sense point), CH2: RESET/PGOOD/OUT.
- Capture the VDD value at the first stable transition for release and assert.
Pass / Fail
- Record VTH+ (release) and VTH− (assert) for each cycle.
- Verify both are within the designed worst-case window and keep margin to the system limits.
Test case 2 — Add ripple/noise (confirm no chatter)
Stimulus
- Hold VDD near the boundary and inject ripple (PSU transient/ripple mode or load-step ripple).
- Sweep ripple amplitude up to the expected worst-case at the comparator sense node.
Observe
- Count output toggles (or measure pulse bursts) while VDD is near threshold.
- Check whether chatter aligns with the ripple waveform (indicates insufficient hysteresis).
Pass / Fail
- For the specified ripple amplitude, output remains stable (no multi-toggling).
- Measured VHYS (VTH+ − VTH−) stays above the required noise/ripple budget.
Test case 3 — Inject glitches (verify t_glitch_reject without over-filtering)
Stimulus
- Inject short VDD dips/bumps with controlled width (sweep pulse width t).
- Use at least two amplitudes: near-boundary and worst-case transient amplitude.
Observe
- Check whether RESET/PGOOD/EN changes state or emits a narrow pulse.
- Measure the smallest pulse width that triggers an output change.
Pass / Fail
- For t < t_glitch_reject, output does not change.
- For t > t_glitch_reject, true faults still trigger (no “filtering away protection”).
Test case 4 — Temperature points (drift must match worst-case window)
Stimulus
- Repeat the slow-ramp extraction at Tmin / Troom / Tmax (or system-defined corners).
- Hold soak time until the measured VDD and board temperature stabilize.
Pass / Fail
- VTH+ / VTH− drift remains within the predicted budget (Vref TC + Vos drift + ratio TC).
- Worst temperature still keeps the valid-power window from collapsing into the system margins.
Measurement traps (avoid “measuring the probe”)
- Probe ground loop: long ground leads create fake ringing and false glitches near edges.
- Bandwidth / sampling: insufficient BW/Sa/s hides narrow pulses and shifts measured crossing points.
- OD rise-time distortion: probe capacitance increases C_load and slows tr, changing real behavior.
- Logic analyzer thresholds: ensure input threshold matches the actual logic domain and input type.
Engineering checklist (layout + components + error control)
Follow the priority order: accuracy first, then chatter/noise, then timing semantics, then robustness. Fixing them out of order usually creates rework loops and misleading bench results.
Level 1 — Threshold accuracy (window correctness)
- Divider ratio control: prioritize ratio tolerance/TC; consider matched resistor networks for stable ratios.
- Divider resistance range: too high increases leakage/bias sensitivity; too low increases static loss.
- Vref noise and filtering: reference noise directly becomes threshold noise; filter/buffer as needed.
- Leakage and contamination: flux residue and humidity create DC shifts at high-impedance nodes; clean and guard.
Level 2 — Noise / chatter immunity (make the decision stable)
- Short sense routing: keep the divider node tight and away from switch nodes and fast edges.
- Ground reference integrity: keep Vref/comparator ground quiet; avoid sharing return with large pulsed currents.
- Hysteresis sizing: VHYS must exceed ripple/noise/ground-bounce at the sense node with margin.
- RC usage boundary: do not “filter away protection”; ensure assert path remains fast.
Level 3 — Timing semantics (assert fast, release slow)
- RESET assertion: keep brown-out assertion short and deterministic; avoid large τ in the assert path.
- Release shaping: use blanking + delay to prevent false release during inrush and start-up ringing.
- OD edge control: place pull-up thoughtfully; check tr with worst-case C_load and probing capacitance.
- PP damping: if PP drives a capacitive net, add series resistance to tame ringing and overshoot.
Level 4 — Robustness (point only: limit + clamp, then re-verify accuracy)
- Limit current: use series resistance to protect the sense input against transients.
- Clamp responsibly: TVS/diodes can add leakage/capacitance; re-check VTH and tr after adding them.
- Re-run bench tests: confirm VTH+/VTH− and t_glitch after any protection change.
Minimum review fields (design + verification)
- Divider: R1/R2, R_total, ratio tolerance, ratio TC
- Vref: accuracy, noise, TC, filter values
- Comparator: Vos, drift, Ib, VICR, output type
- OD pull-up: Vpull, Rpull, C_load, tr
- Timing: t_blank, t_delay, t_assert_max
- Measured: VTH+ / VTH− / VHYS / t_glitch / Temperature
IC selection logic (fields → risk mapping → inquiry template)
Selection should be driven by threshold accuracy, ramp/noise behavior, and output-domain semantics. Use the fields below to shortlist parts, map trade-offs to risks, and ask vendors for complete conditions in one inquiry.
A) Selection fields (copy-paste list)
Power + input viability (hard gates)
- VDD range (min/nom/max, incl. start-up minimum and brown-out tail)
- VICR (input common-mode vs rails, incl. crossover behavior near GND/VDD)
- Input leakage over temperature (critical with high-impedance dividers)
- Ib (input bias current) → threshold shift with Rsource
- Reference option (external Vref vs integrated reference/threshold option)
Threshold accuracy + drift (window correctness)
- Vos / Vos drift (offset + drift) at the operating range
- Vref accuracy / TC / noise (if using internal or external reference)
- Hysteresis option (built-in / external programmable / none)
- Operating temperature (Tmin/Tmax) and allowed drift of VTH
- Package / contamination sensitivity (high-Z nodes need leakage control)
Timing + output semantics (system behavior)
- Propagation delay (at relevant overdrive) vs required assert time
- Output type (open-drain / push-pull) + voltage-domain compatibility
- Output drive (sink/source) and VOL/VOH targets under load
- Iq across temperature and supply (battery-life impact)
- ESD/EMI requirement (minimum level to meet environment; verify conditions)
B) Risk mapping (field conflicts → failure modes → actions)
Low power (Iq) vs stable decision under slow ramps
- Risk: slow ramp + ripple/noise near VTH causes multi-toggling and false resets.
- Action: prioritize hysteresis options (built-in or external-friendly), and reserve RC/blanking positions.
- Verification: run ripple + glitch tests at the slowest realistic ramp and worst temperature.
Low Vos vs speed vs VICR constraints
- Risk: “precision” parts may trade speed or lose clean behavior near rails due to VICR crossover.
- Action: treat VICR at the actual threshold node as a hard gate; keep margin from rail edges when possible.
- Verification: measure VTH+/VTH− at supply corners and confirm no output ambiguity at partial rails.
Open-drain pull-up: power vs rise-time (and false logic edges)
Enforce (OD sink strength)
Rpull ≥ (Vpull − VOL_target) / I_sink_min
Approximate (rise-time check)
tr ≈ 2.2 × Rpull × C_load
- Risk: large Rpull saves current but slows edges (EMI sensitivity, missed reset timing, false sampling).
- Action: choose Rpull from sink limit and tr target using worst-case C_load (include probe/cable).
C) Shortlist buckets (example part numbers)
These part numbers are starting points only. Always verify output type, VICR behavior, reference options, timing conditions, and leakage over temperature in the datasheet and on the bench.
Ultra-low power threshold / wake
Focus: Iq-first designs where slow ramps and leakage must still be controlled.
Example parts
TI TLV3691
Comparator with reference option (BOM-tight power-valid)
Focus: reduce external Vref complexity; validate start-up behavior and reference settling.
Example parts
TI TLV3011 (OD), TI TLV3012 (PP)
Micropower general-purpose comparators (flexible output choices)
Focus: broad availability; confirm OD/PP variant, leakage, and VICR at the threshold node.
Example parts
Microchip MCP6541 (family), Microchip MCP6546 / MCP6547 / MCP6548 / MCP6549 (family)
Fast assert path (ns-class response)
Focus: minimize brown-out assert latency; verify overdrive condition and output stage behavior at partial rails.
Example parts
TI TLV3501, TI LMV7219
Classic open-collector / open-drain wired logic
Focus: wired-OR reset lines and cross-domain pull-ups; confirm sink limits and VOL at temperature.
Example parts
onsemi LMV331 / LMV393 / LMV339
Ultra-low power + reference family (window-friendly)
Focus: integrated reference families for stable thresholds; validate reference settling and output defaults.
Example parts
ADI LTC1440 / LTC1441 / LTC1442, ADI LTC1444 / LTC1445
D) Inquiry template (short form to vendors)
Copy-paste form
System context
- Rail name / function: _______________________
- VDD_min / VDD_nom / VDD_max: _______________________
- Operating temperature (Tmin/Tmax): _______________________
- Threshold node location (near GND / mid / near VDD): _______________________
Threshold window targets
- Target VTH+ (release): _______________________
- Target VTH− (assert): _______________________
- Allowed worst-case threshold error: _______________________
- Required hysteresis (VHYS_min or no-chatter condition): _______________________
Glitch + timing requirements
- Glitch rejection target (t_glitch_reject): _______________________
- Max assert delay allowed (t_assert_max): _______________________
- Release policy (blanking / delay): _______________________
Output domain + load
- Output type needed (OD / PP): _______________________
- Pull-up voltage (if OD): _______________________
- C_load estimate (incl. wiring/probes): _______________________
- Target rise-time (tr_target): _______________________
- Wired-OR needed (Y/N): _______________________
Vendor deliverables (request explicitly)
- Worst-case Vos/drift, Ib/leakage, VICR behavior at threshold node
- Propagation delay vs overdrive at the required supply and temperature
- Output behavior during partial-rail / start-up and reference settling (if applicable)
- Recommended pull-up range for OD and expected VOL at temperature
Request a Quote
FAQs (Brown-In / Brown-Out): fast fixes with measurable checks
Each answer is intentionally short and test-driven. Use the same four-line structure to keep troubleshooting bounded and repeatable.
Why does the same comparator look “more threshold-drifty” at 1.8 V? (VICR crossover / Ib)
Symptom: VTH varies run-to-run at low VDD, especially near rails.
Check: (1) VICR coverage at the divider node, (2) Ib/leakage at low VDD, (3) divider Thevenin resistance Rth.
Threshold: If the divider node enters VICR crossover (or has very small rail headroom), or if
ΔVTH ≈ Ib × Rth × (1 + R1/R2) exceeds the allowed error, low-VDD “drift” is expected.
Fix: Reduce Rth (lower divider impedance), keep the sense node away from rail edges, or select a part with
rail-friendly VICR behavior for the actual threshold node.
Slow ramp causes multiple resets: what hysteresis (mV) is a sane starting point?
Symptom: Output chatters (multiple toggles) while VDD slowly crosses the boundary.
Check: (1) ripple_pk at the divider node, (2) noise_rms at the divider node, (3) ground bounce pk at the comparator ground.
Threshold: Start from VHYS_div ≥ ripple_pk + 3×noise_rms + bounce_pk.
If node noise is not yet measured, start with a conservative VDD-side VHYS of 30–80 mV and tighten using bench data.
Fix: Increase hysteresis first (stops repeated crossings) before adding large input RC.
Keep “assert fast / release slow” semantics intact.
Divider made very large to save power, but VTH shifted: how to estimate Ib×R error?
Symptom: Measured threshold is consistently offset from the calculated ratio-based value.
Check: (1) Ib/leakage worst-case, (2) Rth of the divider node, (3) any extra leakage path (flux/humidity) at the node.
Threshold: Use ΔVnode ≈ Ib × Rth.
Convert to VDD-side threshold shift as ΔVTH ≈ ΔVnode × (1 + R1/R2). If ΔVTH exceeds the allowed VTH error budget, the divider is too high-Z.
Fix: Lower divider impedance, use matched resistor networks for ratio stability, and apply leakage control (cleaning, guard ring, short routing).
RC filter added, but brown-out becomes slow: how to avoid delayed RESET on power-down?
Symptom: During power-down, RESET/PGOOD asserts late, or misses the intended timing window.
Check: (1) where RC sits (input node vs output delay), (2) τ = R×C vs t_assert_max, (3) discharge path of the RC node during falling VDD.
Threshold: If τ is a large fraction of t_assert_max, “assert” will be delayed.
As a rule, keep assert-path filtering small enough that true brown-out crosses VTH and forces output within the required max assert delay.
Fix: Apply delay mainly to release (blanking/delay) while keeping assert fast.
If input RC is needed, add a fast-discharge path (e.g., diode/parallel resistor) to preserve fast brown-out assertion.
Open-drain RESET: what pull-up value avoids chatter yet minimizes current?
Symptom: Edges are slow or noisy; RESET is sensitive to coupling; or pull-up wastes too much current.
Check: (1) I_sink_min and VOL_target, (2) C_load (net + wiring + probe), (3) tr_target and noise environment.
Threshold: Must satisfy BOTH:
Rpull ≥ (Vpull − VOL_target) / I_sink_min AND Rpull ≤ tr_target / (2.2×C_load).
If no overlap exists, OD is not a good match for the load/edge requirement.
Fix: Choose Rpull in the overlap, reduce C_load, or switch to push-pull / buffered stage when edge integrity is critical.
Vref starts slower than VDD: how to add blanking reliably?
Symptom: Early false release/false assert happens during start-up when Vref is not settled.
Check: (1) Vref settling time to within accuracy target, (2) start-up ringing duration at VDD/divider node, (3) output default state at partial rails.
Threshold: Set t_blank ≥ max(t_vref_settle, t_ring) + margin.
Margin should cover worst-case temperature and load conditions (use measured worst-case plus guardband).
Fix: Gate the decision during blanking, then apply a separate release delay if needed.
Do not rely on a single RC that also slows brown-out assertion.
Rippled DC-DC rail chatters near threshold: increase VHYS or add RC?
Symptom: Output toggles in sync with ripple while VDD is near the threshold window.
Check: (1) ripple_pk at the divider node, (2) dominant ripple frequency, (3) required max assert delay.
Threshold: If chatter is driven by repeated crossings from steady ripple, prefer VHYS such that VHYS_div > ripple_pk (+ margin).
If failures are short spikes (finite pulse width), size filtering/blanking to a target t_glitch_reject instead.
Fix: Use VHYS for “repeated crossings” and RC/blanking for “short pulses.”
Keep assert fast and avoid filtering away true brown-out events.
Multi-rail “all-good to release”: wired-OR / wired-AND keeps flipping polarity—how to avoid logic inversion mistakes?
Symptom: System releases when it should hold reset, or holds reset when all rails look good.
Check: (1) signal polarity naming (RESETn/PGOOD), (2) truth table for “any-fault holds reset,” (3) pull-up domain and OD wiring.
Threshold: Must satisfy: any single-rail fault forces the system to the safe state (reset asserted / enable disabled).
If the truth table violates this, the logic polarity is wrong regardless of measured voltages.
Fix: Lock conventions (active-low reset lines + “n” suffix), draw the truth table first, then wire OD lines accordingly.
Use inversion only when the truth table demands it.
Threshold drifts with temperature: is Vref TC or Vos drift usually the dominant cause?
Symptom: VTH+ / VTH− shift with temperature beyond expectation.
Check: (1) Vref TC and its filtering/noise, (2) comparator Vos drift, (3) divider ratio TC (especially unmatched resistors).
Threshold: Convert all contributors to the same domain (VDD-side threshold):
ΔVTH_total ≈ Gain_ratio×(ΔVref + ΔVos) + Ratio_TC_term. The dominant term is the largest converted contribution across Tmin/Tmax.
Fix: Improve the dominant term: better Vref/TC, lower-drift comparator, or matched resistor network for ratio TC control.
Field contamination/humidity causes divider-node leakage: how to recognize it fast on the bench?
Symptom: Threshold shifts slowly over minutes/hours, changes with touch/humidity, or varies after cleaning.
Check: (1) divider node voltage vs time at constant VDD, (2) resistance from divider node to GND/VDD under different humidity,
(3) change after IPA cleaning/drying.
Threshold: If the node shows environment-correlated DC drift (not explained by VDD or temperature), leakage is a primary suspect.
High-Z dividers amplify this; drift that scales with Rth indicates leakage sensitivity.
Fix: Clean/dry, shorten routing, add guard ring/keep-out, reduce divider impedance, and re-verify VTH+/VTH− after mitigation.
Output drives EN and the system “retries” repeatedly: how to enforce “slow release + fast shutdown”?
Symptom: Enable oscillation: enable → rail rises → trips → shuts down → repeats near the threshold window.
Check: (1) VDD trajectory vs VTH+/VTH−, (2) release delay / blanking settings, (3) whether the assert path is also delayed by filtering.
Threshold: If VDD repeatedly crosses the window edges during start-up, the control loop needs minimum on/off time or additional hysteresis.
Release must wait for stability; assert must remain within t_assert_max.
Fix: Add release delay/blanking (only), keep assert fast, and add hysteresis or a minimum off-time lockout to break the retry loop.
How to extract VTH+, VTH−, and t_delay in a single slow-ramp test (reduce test time)?
Symptom: Bench time is high because thresholds, hysteresis, and delays are tested separately.
Check: (1) ramp slope and repeatability, (2) scope/logging resolution at the DUT sense point, (3) output loading (OD pull-up + C_load).
Threshold: Logging time/voltage resolution must be finer than the allowed VTH error.
Trigger off the output edge and record the corresponding VDD value to get VTH+ (release) and VTH− (assert), plus measure t_delay from crossing to output edge.
Fix: Run one rising ramp and one falling ramp per temperature point, capture VDD-at-edge and edge timing, and store fields:
VTH+, VTH−, VHYS, t_delay, t_glitch (if pulses are injected in the same run).
