A window comparator turns a real-world signal into a clear three-state decision: below range, OK, or above range.
This page shows how to set VLOW/VHIGH, add hysteresis without warping the window, budget the errors, and verify the thresholds so alarms stay stable on real cables and noisy ramps.
What this page solves
A window comparator turns a noisy analog range into a deterministic three-state decision:
UNDER (below the low limit), WITHIN (inside the allowed window), and OVER (above the high limit).
This is the fastest way to implement compliance checks and protection gates for voltage, temperature-derived voltages, and 4–20 mA loops.
What the window gives the system
UNDER / WITHIN / OVER states mapped to actions (trip, allow, fault handling) without firmware polling.
A clean way to express “valid operating range” (not just a single threshold).
A stable decision boundary when hysteresis is used against slow ramps, noise, and long cables.
Three practical outcomes to take away
Window limits you can trust: define VLOW/VHIGH with guardband so “OK” remains valid across tolerances and temperature.
Stability without chatter: select hysteresis and input conditioning so slow/noisy signals do not multi-toggle near the limits.
Verification-ready design: measure thresholds, hysteresis, and response with repeatable bench hooks and production-friendly checks.
Scope guardrail (avoids cross-page overlap)
This page stays focused on window limits + hysteresis + accuracy/robustness. Topics like zero-crossing, one-shot timers, high-speed latched timing, and isolated chains belong to their dedicated pages.
Window Comparator fundamentals
A window comparator defines two limits—VLOW and VHIGH—and classifies the input into three states.
This behavior can be exposed as two outputs (UV/OV) or as a single “Window-OK” output, depending on how the system wants to react to faults.
Three-state decision rules (truth-table style, no big table)
VIN < VLOW → state = UNDER → UV asserted (input is below the allowed range).
VLOW ≤ VIN ≤ VHIGH → state = WITHIN → OK asserted (input is compliant).
VIN > VHIGH → state = OVER → OV asserted (input exceeds the allowed range).
Output mapping options (choose the one that matches the system logic)
Dual outputs (UV + OV): best when the system needs to distinguish “too low” vs “too high”
(e.g., open-wire vs over-voltage, under-temp vs over-temp). An OK signal can be formed as NOT(UV OR OV) if needed.
Single output (Window-OK): best when only “in-range / out-of-range” matters.
This reduces logic but hides which side of the window failed.
Window width vs hysteresis (do not mix these up)
Window width defines the allowed limits: (VHIGH − VLOW). Hysteresis defines stability by separating the switching points on rising vs falling edges.
The robust design order is: set the window limits → add hysteresis for stability → budget errors to guarantee compliance.
What to decide next (sets up the rest of this page)
Define VLOW and VHIGH from the true “allowed window” (including guardband and compliance margins).
Select hysteresis large enough to exceed noise/slow-ramp perturbations without shrinking the usable window.
Choose output mapping (UV/OV vs OK) that matches the desired fault behavior (distinguish vs simplify).
Architectures
A window comparator can be implemented in three practical ways: build the window from two comparators, use an
integrated window IC, and choose how the thresholds are anchored by the reference source.
The best choice depends on whether the system needs separate UV and OV decisions, how programmable the limits must be,
and how much absolute threshold accuracy is required across temperature.
A) Two-comparator window (most flexible)
Best for
Separate UV and OV actions (different fault handling).
Custom hysteresis for each boundary (UV and OV can differ).
Cross-domain alarms using open-drain + pull-ups (wired-OR).
Watch-outs
Threshold mismatch can come from two offsets/drifts instead of one.
Different source impedances make bias × R shift UV/OV unequally.
If OK is formed as NOT(UV OR OV), verify polarity and pull-up logic.
B) Integrated window comparator IC (fastest BOM)
Best for
Compliance windows where simplicity matters more than extreme accuracy.
Fixed or limited-range thresholds with minimal external parts.
Systems that only need OK/FAULT rather than UV vs OV separation.
Watch-outs
Threshold range, hysteresis, and output logic may be fixed or constrained.
Internal reference/noise/temperature behavior must match the application window.
Some parts hide which side failed (no separate UV/OV).
C) Threshold reference source (anchors absolute accuracy)
Absolute window accuracy is set by the reference and divider ratio, then shifted by comparator offset/drift and bias × source impedance.
Pick the reference path based on how stable the limits must remain across temperature and supply variation.
Options
Internal ref: minimum BOM; verify TC/noise are acceptable for the window.
External ref: best stability; requires clean layout and decoupling.
Threshold design starts from the real allowed range and works backward to VLOW and VHIGH.
The divider (or shunt-to-voltage scaling) maps the external signal into the comparator input range, while input bias current and source impedance
can shift the effective switching points. The goal is a window that remains valid under tolerance, temperature, and noise.
Reusable workflow (Step 0 → Step 3)
Step 0 — Define the allowed window with guardband
Translate “allowed range” into two hard limits: a low limit and a high limit.
Apply margin for protection/compliance so the OK state is not lost at corners.
Output of this step: VLOW_target and VHIGH_target.
Step 1 — Pick the comparator input domain and the reference anchor
Choose whether thresholds compare to VREF, an internal threshold, or a programmable ref.
Ensure the scaled node stays inside the usable input range across operating conditions.
Decide if separate UV/OV outputs are required (affects architecture from the prior section).
Step 2 — Back-calculate divider ratio to hit VLOW/VHIGH
Create a mapping from the external signal to the comparator input node (VIN → VNODE).
Set the divider ratio so VNODE crosses the internal compare level at VLOW_target and VHIGH_target.
Keep the mapping monotonic and testable: a slow ramp should show two clean transition points.
Bias shift: the effective threshold can move by approximately ΔVTH ≈ IBIAS × RTH (RTH = node’s Thevenin resistance).
Large R: lower power but higher bias/leakage sensitivity and more EMI pickup.
Small R: better immunity but higher static loss and heavier loading of the source.
Quick self-check (before moving to hysteresis)
Does the scaled node stay in a clean input range for the chosen comparator and supply?
Is ΔVTH from bias/leakage comfortably below the window guardband?
Is divider current acceptable for battery life and thermal budget?
Adding hysteresis
Hysteresis prevents chatter under slow ramps, noise, and long cables. The common failure mode is adding feedback in a way that
moves VLOW/VHIGH or makes the window width depend on the current state. The robust design order is:
set the window limits → set hysteresis targets → re-check worst-case limits.
Recommended workflow (keeps the window from drifting)
Freeze the target limits: start from VLOW_target and VHIGH_target without hysteresis.
Choose hysteresis targets: define ΔVhys_low and ΔVhys_high to exceed expected perturbations
(noise + ramp ripple + interference margin).
Implement with controlled positive feedback: select a feedback path so the shift is intentional and bounded.
The effective shift at the input node scales with the ratio between the feedback network and the node’s RTH.
Map back to VIN and re-check compliance: verify the worst-case switching points still leave enough “OK” window
after tolerances and drift.
Common coupling traps (why the window “gets distorted”)
Shared feedback path: one output state injects into both boundaries, shrinking or shifting the window.
State-dependent RTH: the node impedance changes with switches/leakage, changing ΔVhys unpredictably.
Unbalanced UV vs OV design: one side gets enough hysteresis, the other still chatters near its edge.
Symmetric vs asymmetric hysteresis (when to use each)
Symmetric: stable in both directions; best when input moves up and down and both edges must be equally quiet.
Asymmetric: add more margin on the edge with higher false-trigger cost (e.g., OV cut-off) while keeping compliance intact.
Rule: hysteresis must exceed disturbance, but must not consume the required OK window after tolerances.
Error budget
The window must remain correct under real-life corners. Error budgeting maps each contributor into a shift of VLOW and VHIGH,
and reveals whether the “OK” region still covers the required compliance window. The key distinction is between contributors that
shift both boundaries and those that change window width.
Error mapping (what moves the edges vs what changes the width)
Boundary shift (moves VLOW/VHIGH)
Offset + drift: adds directly to the effective threshold at each edge.
Stabilize width: use matched resistor ratios (tight tolerance, low ratio tempco mismatch).
Protect the node: guard rings/clean layout, input protection to limit leakage and contamination sensitivity.
Reference hygiene: decouple VREF, keep loop small, and prevent digital return currents through the ref path.
Output of budgeting (what matters to compliance)
Compute worst-case edges: VLOW_worst and VHIGH_worst across contributors.
Set guardband so the worst-case “OK” window still covers the required operating range.
Prefer changes that reduce dominant contributors before increasing hysteresis (hysteresis improves stability, not accuracy).
Noise / slow ramp / chatter
Chatter happens when the input changes slowly and spends a long time near the threshold. Small disturbances (input noise, cable pickup,
ground bounce, and output-coupled spikes) repeatedly push the instantaneous input across the switching point. The robust fix is a
controlled sequence: set hysteresis → filter the input → limit and clamp fast transients →
remove coupling paths.
Why slow ramps chatter (what to look for on the scope)
Long dwell near threshold: small noise becomes decisive when |dV/dt| is low.
Insufficient hysteresis: a single threshold is crossed repeatedly by ripple and pickup.
Output-coupled spikes: each output edge injects a small transient back into the input node.
Practical fix order (do this first → last)
Add hysteresis: set ΔVhys (mapped to VIN) above the local disturbance near the threshold.
Add input RC (near the pin): reduce high-frequency pickup so the threshold is not crossed by spikes.
Add series-R + clamp for fast events: limit surge/ESD current and prevent the input node from being slammed.
Eliminate coupling: shorten loops, improve returns, and prevent output edges from sharing the input return path.
RC trade-offs (filtering helps stability but adds delay)
Benefit: spike amplitude at the input node is reduced, lowering false crossings.
Cost: response slows; a real boundary violation may be detected later.
Rule: pick RC to suppress the disturbance without exceeding the allowed detection delay.
Clamp + series-R in window alarms (threshold side effects)
Leakage acts like bias: clamp/device leakage shifts VLOW/VHIGH at temperature or contamination corners.
Capacitance reshapes ramps: TVS/input capacitance with source-R can increase dwell near the edge.
Output interfacing
Window alarms often cross voltage domains and need to be combined from multiple sources. Output type selection determines whether
alarms can be wired-OR, how fast edges rise, and how much static power is consumed. The practical choice is
Open-Drain for cross-domain and multi-point alarms, and Push-Pull for clean direct drive.
Quick decision list (OD or PP)
Choose Open-Drain (OD) when
Cross-voltage domains are required (pull up to the logic voltage).
Multiple alarms must be combined (wired-OR multi-point alert).
A pull-up can be tuned for cable length and input capacitance.
Choose Push-Pull (PP) when
Clean fast edges are needed without external pull-ups.
Drive strength matters (lower susceptibility to noise on long traces).
The logic domain is fixed and wired-OR is not required.
Pull-up sizing (speed vs power vs cable length)
Static current: when OUT is low, current is Vpullup/Rpull and must stay within sink capability.
Rise speed: Rpull with total capacitance (line + input + ESD) sets the edge rate and noise susceptibility.
Power: smaller Rpull speeds edges but increases low-level dissipation and heating.
Minimal debounce / latch for window alarms
Prefer software latch: once an alarm is detected, hold the fault state until a reset or explicit clear.
Use hysteresis first: avoid adding delay circuits when the root cause is chatter near the threshold.
Keep it minimal: add RC only when the environment produces short spikes that exceed hysteresis.
Validation & measurement
A window comparator design is only complete when thresholds, hysteresis, and timing are verified on real hardware. Validation must
separate static thresholds from dynamic delay, and must avoid measurement artifacts caused by probe loading,
ground loops, and source impedance. The recommended approach is to measure rising and falling points for each boundary,
then verify response time with a controlled step.
Threshold sweep (static VLOW / VHIGH)
Goal: record four points: VLOW_rise, VLOW_fall, VHIGH_rise, VHIGH_fall.
Method: apply a slow ramp across one boundary at a time and log the output transition.
Pass rule: points must fall within the worst-case limits from the error budget.
Common error: ramp too fast measures dynamic delay instead of the true threshold.
Method: use the same ramp, capture both directions, and reference the DUT-side node.
Pass rule: ΔVhys must exceed the local disturbance near the boundary.
Common error: output coupling creates a false “extra” hysteresis unless grounding is clean.
Response timing (step input + time stamp)
Goal: measure total delay from VIN_node step to valid OUT at the logic receiver.
Method: apply a clean step that crosses the boundary by a clear margin and time-stamp VIN vs OUT.
Pass rule: delay must meet the system response limit under the real pull-up/RC/load.
Common error: OD pull-up and cable capacitance dominate OUT rise and inflate timing.
Measurement traps (avoid false conclusions)
Probe loading: probe capacitance changes the effective RC and shifts delay and crossings.
Ground loops: long ground leads inject spikes that look like extra noise or chatter.
Source impedance: the DUT node may differ from the instrument reading under load.
Pull-up artifacts: slow OUT edges shift apparent timing at the MCU threshold.
Design hooks
These hooks condense the page into reusable actions. Each hook states the inputs, the action, the output values, and the validation
method to keep threshold design, hysteresis, filtering, and timing consistent and testable.
Hook 1 — Window edges + guardband
Inputs: allowed range and worst-case error limits.
Action: back-solve VLOW/VHIGH and place guardband where risk is highest.
Action: set ΔVhys above disturbance, then ensure the OK window is not consumed.
Outputs: ΔVhys_low and ΔVhys_high (asymmetric if needed).
Validate: measure VTH+ and VTH− points and confirm chatter is eliminated.
Hook 4 — Input RC from bandwidth and delay
Inputs: allowed detection delay and expected transient spectrum.
Action: choose RC to suppress spikes without violating response time limits.
Outputs: R_in, C_in, and time constant target.
Validate: step timing at the DUT node and at the logic receiver.
Engineering checklist
This checklist turns window-comparator theory into build-ready decisions: schematic hygiene, PCB layout rules, protection details,
and production fields that close the loop. Items are ranked by priority:
P0 (must-have), P1 (strongly recommended), P2 (nice-to-have).
P0
P1
P2
Schematic
P0
Threshold + reference path is explicit
Check: VLOW/VHIGH network, reference source, and sense node naming are unambiguous.
Pass: thresholds back-calculate to the allowed window + guardband under worst-case limits.
Fix: add explicit test nodes (VIN_node / REF / OUT) and keep threshold math tied to those nodes.
P0
REF decoupling is local and quiet
Check: REF pin capacitor placement intent is clear (single short return).
Pass: REF loop does not share noisy digital return currents.
Fix: shorten REF loop, isolate return, and avoid routing fast signals nearby.
P0
Protection does not shift the window
Check: series-R + clamp/TVS leakage and capacitance impact on VIN_node is assessed.
Pass: worst-case leakage does not violate threshold accuracy targets.
Fix: lower the source impedance, move clamps to a protected node, or change clamp type.
P1
Tuning options are built-in
Check: optional footprints for hysteresis/RC/0Ω links exist to tune chatter vs delay.
Fix: add jumpers/0Ω links near the comparator input and output interface points.
P2
Test hooks are accessible
Check: VIN_node / OUT / REF pads are probe-friendly for validation and production test.
PCB layout
P0
Input symmetry + tiny loops
Check: both inputs see similar routing and parasitics; avoid long stubs and split planes.
Pass: VIN_node is short, shielded from fast edges, and returns locally.
P0
No ground-bounce injection
Check: OUT return current does not share the threshold/REF return path.
Pass: OUT edges do not create synchronous spikes at VIN_node.
Fields: ΔVhys_low, ΔVhys_high; response delay under real pull-up/load.
Bins: LOW too high, HIGH too low, HYS too small, delay too slow.
P1
Temperature corner sampling is planned
Check: at least cold/ambient/hot points capture threshold drift trends.
P2
Version tags are recorded
Check: pull-up / input RC / clamp variant IDs are traceable in logs and test reports.
Applications + IC selection logic
Window comparators are most valuable when the application is expressed as an OK window with clear fault regions.
The recipes below show common mappings (4–20 mA, NTC/voltage compliance, and brown-in/brown-out), followed by a selection flow
that converts requirements into comparator parameters and RFQ fields.
Application recipes
4–20 mA compliance window (open / short / over-range)
Map: loop current → shunt voltage → window compare at VIN_node.
Thresholds: VLOW/VHIGH derive from shunt value + reference + guardband.
Hysteresis: set ΔVhys to exceed pickup/ground bounce at the boundary.
Validate: slow sweep across each boundary; step response under real pull-up/load.
Temperature / voltage compliance window (NTC or divider)
Map: NTC/divider → VIN_node representing cold/OK/hot or undervolt/OK/overvolt.
Thresholds: compute window edges from the desired limits and the transfer curve.
Hysteresis: prevent chatter under slow ramps (warm-up, cooling, airflow).
Validate: sweep VIN_node slowly; confirm drift and hysteresis at corners.
Short, actionable answers for window-comparator edge cases (chatter, hysteresis coupling, bias/RC errors, OD pull-ups,
Vref/VICR traps, production test, and guardbanding). Each answer includes a quick test, a decision threshold, and a fix.
Why does Window-OK chatter on a slow ramp—add hysteresis first or RC first?
Symptom: OK output toggles multiple times while VIN slowly crosses VLOW or VHIGH.
Most-likely causes: input noise near threshold, insufficient hysteresis, ground-bounce coupling into the threshold node.
Quick test: hold VIN at the boundary (no ramp) and observe toggling; then add a temporary hysteresis resistor (clip lead) and compare.
Threshold: if equivalent threshold noise (VIN ripple at VIN_node) is > (ΔVhys / 3), chatter is expected.
Action:
Set hysteresis first: target ΔVhys ≥ 3×(VIN_node peak-to-peak noise) at the boundary.
If chatter remains, add input RC to limit noise bandwidth (RC placed at the comparator pin).
Then verify layout/return: OUT edge current must not share the threshold/REF return path.
Verify: slow sweep once up and once down; record VLOW_rise/fall and VHIGH_rise/fall and confirm exactly one toggle per edge.
Hysteresis was added and the window width changed—what two places should be checked first?
Symptom: VLOW/VHIGH shift depending on output state; window becomes wider/narrower than intended.
Most-likely causes: hysteresis injection point is wrong, output swing (VOL/VOH) is not what the math assumed, or divider/source impedance is too high.
Quick test: measure VTH points twice: once with OUT forced high and once forced low (or use a pull-up override for OD).
Threshold: if |VTH(OUT=H) − VTH(OUT=L)| consumes > 30% of the allowed guardband, the window is being “pulled” by the feedback path.
Action:
Check #1: feedback injection node—inject to the comparator input node that tracks the divider, not to a remote/high-impedance sense point.
Check #2: output swing assumption—use measured VOL/VOH (or OD pull-up level) in the threshold calculation.
Reduce effective source impedance (lower divider values) if bias/leakage makes the coupling nonlinear.
Verify: re-measure four points (VLOW_rise/fall, VHIGH_rise/fall) and confirm the window width remains stable across output states.
Bias current × divider resistance shifts thresholds—when does “R too large” become significant?
Symptom: measured VLOW/VHIGH differ from calculation; drift grows at temperature.
Most-likely causes: comparator input bias current, clamp/TVS leakage, or PCB contamination current flowing through high-value dividers.
Quick test: repeat threshold sweep at two temperatures; also repeat with a known lower divider resistance (temporary parallel resistor) and compare shift.
Threshold: treat it as significant when (Ibias_or_leak × R_equiv_at_input) ≥ min(0.25×guardband, 0.10×ΔVhys).
Action:
Lower divider impedance (reduce R by 5–10×) until bias/leak term falls below the budget threshold above.
Move clamps off the high-impedance node or pick lower-leakage protection parts.
Shorten/guard the threshold node; clean/coat if humidity sensitivity is observed.
Verify: VLOW/VHIGH error must stay within guardband at temperature corners; repeatability must improve after R reduction.
With OD wired-OR alarms, what goes wrong if the pull-up is too large or too small?
Symptom: alarm edges are slow, missed, noisy, or power is wasted.
Most-likely causes: pull-up too large → slow rise; pull-up too small → excessive sink current and VOL not low enough.
Quick test: measure rise time at the far end of the cable/bus; measure VOL when asserted with worst-case sink.
Threshold: use tr ≈ 2.2·Rpull·Cbus; require tr ≤ (0.2×allowed_alarm_latency). Also require VOL ≤ VIL(max) of the receiver at I_sink(max).
Action:
Set an upper bound: Rpull ≤ tr_target / (2.2·Cbus).
Set a lower bound: Rpull ≥ (Vpull − VOL_target) / I_sink(max), and check power = (Vpull² / Rpull).
If both bounds conflict, reduce bus capacitance (shorter cable, fewer nodes) or use a buffer/PP output path.
Verify: confirm rise/fall at the receiving pin across corners and with all nodes connected (wired-OR worst-case).
Can Vref noise make the window “jitter”? How to tell it from input noise?
Symptom: toggling occurs even when the sensed signal seems steady.
Most-likely causes: reference ripple/noise coupling into thresholds, or noise on VIN_node amplified by high impedance.
Quick test: keep VIN fixed and add extra REF filtering (temporary capacitor close to REF); then repeat with VIN filtering only.
Threshold: if (Vref_ripple mapped to VIN threshold) is > (ΔVhys / 3), Vref-driven jitter is plausible.
Action:
First isolate: A/B test by improving REF filtering vs input filtering; the dominant fix identifies the dominant source.
Shorten the REF loop and keep it off noisy returns; avoid sharing REF decoupling return with digital edges.
If the design uses a DAC/REF, ensure output noise/TC is compatible with the threshold error budget.
Verify: at fixed VIN near the boundary, output must remain stable; then re-check four VTH points with slow sweeps.
Thresholds near the rails look unstable—is it VICR behavior or layout ground-bounce?
Symptom: window transitions shift or become noisy when VIN is close to VDD or GND.
Most-likely causes: input common-mode range (VICR) crossover behavior, or ground-bounce coupling from OUT/switching currents.
Quick test: (1) repeat the sweep with a scope ground spring at the comparator ground pin; (2) repeat with OUT disconnected/quiet (no heavy load or long wire).
Threshold: if measured VTH changes noticeably when the measurement ground point changes, it is likely ground-bounce/return-path related (not VICR).
Action:
Rule out measurement artifacts first (ground lead loops can mimic instability).
If VICR-related, choose a comparator with guaranteed VICR coverage at the intended rails and under overdrive.
If ground-bounce-related, reroute OUT return currents and isolate threshold/REF returns from fast edge returns.
Verify: thresholds repeat within budget across rails-adjacent operation and corner loads, using DUT-side probing.
After long-cable or ESD events, thresholds drift—what is the most common leakage/damage culprit?
Symptom: VLOW/VHIGH shift permanently, or shift with humidity/temperature after a stress event.
Most-likely causes: TVS/clamp leakage increase, damaged input resistor network, or PCB surface leakage on high-impedance nodes.
Quick test: measure input-node leakage indirectly: compare VTH with the sensor disconnected (open) vs connected; also compare with clamps temporarily removed (if safe).
Threshold: if the VTH shift grows with humidity or warm temperature, leakage-driven error is likely (not pure offset drift).
Action:
Replace protection parts first (TVS/clamps are frequent leakage offenders after ESD).
Lower impedance at the threshold node and shorten exposed routing; add coating for harsh environments.
Re-check the error budget with worst-case leakage, not typical leakage.
Verify: re-run threshold sweeps across humidity/temperature; the drift slope must return to within guardband limits.
RC filtering was added and now alarms are late or inconsistent—how to choose RC without breaking the window?
Symptom: alarms respond too slowly, or thresholds shift when the signal changes quickly.
Most-likely causes: RC time constant too large vs allowed latency, or RC placed far from the comparator input causing parasitic pickup.
Quick test: inject a step at the connector and measure the step at VIN_node; compare delay at VIN_node vs OUT.
Threshold: choose τ such that 5τ ≤ allowed_alarm_latency for near-full settling at the boundary; otherwise delay dominates behavior.
Action:
Set τ from latency first: τ ≤ allowed_latency / 5.
Place the capacitor at the comparator input pin; keep the RC loop small.
Re-check bias/leak terms with the new R (RC often increases effective source impedance).
Verify: confirm response time with a step test and confirm hysteresis/thresholds with a slow sweep.
How can production quickly measure VLOW/VHIGH and hysteresis without complex instruments?
Symptom: ATE is limited; still need repeatable window thresholds and ΔVhys.
Most-likely constraints: no precision SMU/DAQ; limited time per unit.
Quick test: use a programmable ramp (DAC, PWM+RC, or stepped supply) and log the code/time at which OUT flips on rising and falling ramps.
Threshold: require four flip points: VLOW_rise/fall and VHIGH_rise/fall; compute ΔVhys_low and ΔVhys_high from the pairwise differences.
Action:
Generate a slow monotonic ramp; detect the first stable OUT transition (debounce in firmware with a short window).
Convert flip code/time to voltage using the calibrated ramp slope or DAC transfer.
Store VTH points + ΔVhys as the minimum production dataset; bin failures by which boundary is out of spec.
Verify: run a golden unit multiple times; flip-point repeatability must be within the intended test tolerance.
How to set guardband without excessive rejects?
Symptom: too many units fail window thresholds even though the system works, or too many escapes occur.
Most-likely causes: guardband not tied to a worst-case error budget; test noise included as “device error”.
Quick test: separate (A) device threshold spread and (B) measurement repeatability by repeating the same unit multiple times and comparing distributions.
Threshold: guardband should exceed worst-case uncalibrated error plus test repeatability margin; if repeatability > 30% of guardband, the test setup dominates reject rate.
Action:
Start from a worst-case budget (offset/drift + ref + R tolerance + leakage) and set guardband to cover it.
Reduce test noise first (DUT-side probing, stable ramp, debounce rule) before tightening guardband.
Bin by boundary: “LOW too high / HIGH too low / HYS too small / delay too slow” to avoid blind rejects.
Verify: compare field-return rate and production yield after changes; guardband must align with risk tolerance.
How to define reliable 4–20 mA open-wire and short limits using a window?
Symptom: false open-wire or false short alarms near 4 mA or 20 mA due to tolerance and noise.
Most-likely causes: shunt tolerance/TC, reference drift, and insufficient hysteresis around the decision points.
Quick test: sweep loop current through the shunt across the intended boundary while logging OUT; repeat across temperature corners.
Threshold: set boundaries in current space first, then convert: VTH = ITH·Rshunt (plus guardband). Ensure the guardband covers shunt+ref+offset worst-case.
Action:
Choose ILOW and IHIGH based on the system definition (open-wire below the low limit; short/over-range above the high limit).
Convert to VIN thresholds using the shunt (and divider, if present); add guardband from the error budget.
Add hysteresis sized to exceed pickup noise at the boundary so a slow current drift does not chatter.
Verify: confirm no chatter at the limits with slow ramps; confirm correct classification under worst-case temperature and supply.
Window output flips only when connected to the real cable/load—what is the fastest isolation approach?
Symptom: stable in lab, unstable in system; faults appear when cable length or load changes.
Most-likely causes: OD rise-time degradation (Rpull·Cbus), cable-induced pickup into VIN_node, or clamp leakage under real transients.
Quick test: test in three steps: (1) DUT with short cable, (2) long cable without load, (3) long cable with load—log OUT timing and VIN_node ripple.
Threshold: if tr at the receiver grows beyond (0.2×allowed latency) or VIN_node ripple grows beyond (ΔVhys/3), system coupling dominates.
Action:
Fix the output path first for OD: reduce Rpull or segment the bus; confirm receiver thresholds are met.
Then fix the input path: add/relocate RC at the comparator pin and tighten the input return path.
If transients drive clamps, re-check leakage and clamp placement so the threshold node is not distorted.
Verify: repeat the three-step test and confirm stable classification across cable/load variants.
