Typical symptoms this page explains

Scope box (ownership)

• Target absolute trip error (mV or % of threshold).
• Temperature range + a stability criterion (soak until trip point settles).
• Source impedance class (low / mid / high), since current × resistance becomes threshold error.

The core idea used throughout the page

1. Input offset voltage (max over temperature) → the DC floor of absolute trip error (avoid typical-only designs).
2. Offset drift (typ/max, dVos/dT or over-temp offset change) → endpoint worst-case across Tmin/Tmax.
3. Input bias current and its temperature behavior → converts directly to threshold error via Ibias × Rth.
4. Near-rail / common-mode endpoint notes → offset often degrades near CM limits (treat as a condition-dependent worst-case).
5. Internal hysteresis spec (if present) → defines VTH+/VTH− separation; offset shifts both thresholds together.

• Temperature range mismatch: verify the part grade covers the real Tmin/Tmax and use endpoints for worst-case.
• Common-mode test point: offset is measured at specific CM; compute the real CM at the threshold node.
• Operating mode assumptions: auto-zero / dynamic behavior can change the effective offset distribution.
• Source impedance: high Rth amplifies both bias and leakage into mV-scale threshold shifts.
• Footnotes: “guaranteed by design,” “not production tested,” or special conditions change how conservative the bound must be.
• Hysteresis tolerance: VHYS may be typical or wide-range; treat it as a separate bound (do not confuse it with accuracy).

• Vos(max, over temp) → ΔVTH_offset
• Drift / over-temp offset change → ΔVTH_temp
• Ibias(max) + Rth → ΔVTH_currents×R
• Leakage (device + board) + Rth → ΔVTH_currents×R
• VHYS (internal) → VTH+/VTH− band (stability, not accuracy)

• Part / package / grade / temperature range
• Vos: typ + max over temperature + test conditions
• Drift: dVos/dT or over-temp offset change + test conditions
• Ibias: max + temperature behavior (or curve/limits)
• Common-mode test points + near-rail notes
• Internal VHYS: typ/max + how specified
• Supply range used for key specs (VDD)
• Any “guaranteed by design / not tested” footnotes

• VTH_ideal: from divider / reference / DAC setting (treated as an input to this model).
• Rth: Thevenin resistance seen at the threshold node (the “current × resistance” amplifier).
• Worst-case rule: choose signs to maximize |ΔVTH| across temperature and conditions.

• Upper and lower trip points can have different effective bounds: ΔVTH+ and ΔVTH− need separate budgets.
• Offset behavior can change with common-mode and operating region; endpoints often dominate.
• Verification must measure both thresholds (rising vs falling, or upper vs lower) rather than inferring one from the other.

• Target: Allowed |ΔVTH| (mV or % of threshold)
• Temperature: Tmin / Tmax + stability criterion (soak until trip settles)
• Nominal: VTH_ideal (source: divider / Vref / DAC)
• Vos_wc: max over temperature (conditions recorded)
• ΔVos_temp: drift bound (dVos/dT·ΔT or over-temp change)
• Ibias_wc: max + temperature behavior
• Rth: threshold-node Thevenin resistance
• Ileak_wc: device + board leakage bound (or test-derived)
• Result: Worst-case |ΔVTH_total|
• Guardband: Margin = k · |ΔVTH_total| (k typically 1.5–3 for unmodeled effects)

• Use max bounds for absolute accuracy. Typical values belong only in expectation studies, not guardband.
• If the budget is dominated by currents × Rth, lowering impedance or buffering often beats “better offset” parts.
• Leakage often has a strong temperature and humidity dependence; treat it as a first-class error term.

• May be linear or curved; treat it as a bounded change across Tmin/Tmax.
• Worst-case commonly appears at temperature endpoints or at a curve “knee.”
• Budget term: ΔVos_temp (use endpoint bounds, not room-temperature slopes).

• Slow trend at fixed temperature (aging, package stress relaxation, moisture effects).
• Can change after repeated power cycles or thermal cycling.
• Budget term: ΔVos_time or an explicit long-term guardband bound.

• Board bending, mounting force, solder-joint stress, and thermal gradients can create step-like offset shifts.
• Especially dangerous for tight window thresholds because it looks like “random drift” unless disturbed on purpose.
• Budget term: ΔVos_stress (environment-dependent systematic error; must be verified, not assumed).

• Sweep to Tmin/Tmax and hold until the trip point settles (use a stability threshold, not a fixed time).
• Record both trip points (rising vs falling, or upper vs lower).
• Bound the error at endpoints and any visible curvature knee.

• Run a fixed-temperature time series (hours → days) and extract a conservative bound.
• Compare before/after a thermal-cycle batch to catch stress relaxation effects.
• Convert findings into a budget bound or a guardband multiplier.

• Apply deliberate perturbations: mounting force, board flex, connector motion.
• Create a controlled thermal gradient (localized heating/cooling) and look for step shifts.
• If steps appear, treat the shift as an environment-dependent systematic term and verify the bound.

Bottom line (for absolute threshold accuracy)

• Any input bias current produces a voltage error across Rth.
• Bias often increases with temperature, making the trip point appear to “drift.”
• Signature: reducing divider impedance (same ratio, lower R) reduces the error strongly.

• Moisture and flux residues create surface leakage paths at the threshold node.
• ESD diodes and TVS devices can have leakage with strong temperature dependence.
• Signature: cleaning/drying and swapping protection parts changes the trip point markedly.

• Different metals and junctions under a temperature gradient generate µV-level EMFs.
• In mV-class threshold budgets, µV-level injections can be decisive.
• Signature: localized airflow/heating causes repeatable direction-dependent shifts.

1. Rth scan: reduce divider impedance by 10× (same ratio). If the shift shrinks → currents×R dominates.
2. Clean/dry A/B: wash residues and compare dry vs humid conditions. Strong dependence → surface leakage dominates.
3. Protection A/B: remove/replace TVS/ESD parts and compare. Large change → device leakage dominates.
4. Thermal perturb: apply localized airflow/heating. Step/direction shifts → gradients/EMF/stress dominates.
5. Buffer test: add a temporary buffer or lower source impedance. Stability improvement → impedance amplifier confirmed.

• Lower Rth or buffer the threshold node to reduce currents×R terms.
• Use guard rings and keep the threshold node clean/dry to control surface leakage.
• Choose protection devices with verified leakage(T) and validate on the real board.
• Minimize thermal gradients near sensitive nodes; verify with perturbation tests.

• Cut currents×Rth first: if Ibias×Rth or leakage×Rth dominates, better Vos parts will not stabilize the trip point.
• Remove pseudo-drift before calibration: leakage, thermocouple EMF, and stress shifts can be “fit” by LUTs and then fail in the field.
• Every mitigation must map to a term: Vos_wc, ΔVos_temp, Ibias×Rth, Ileak×Rth, or VTH_ideal drift.

• Worst-case |ΔVTH_total| is bounded at Tmin/Tmax and under realistic humidity and stress.
• Upper and lower trip points remain within the budget (window symmetry is not assumed).
• Guardband covers unmodeled effects without requiring fragile multi-point fitting.

• Directly reduces Vos_wc and ΔVos_temp bounds.
• Most effective when the budget is Vos/drift-dominated (not currents×R dominated).
• Must be evaluated at the real common-mode and temperature endpoints used by the threshold node.

• Improves the effective offset distribution and can reduce temperature-dependent systematic terms.
• Requires the operating mode assumptions to match the datasheet conditions used for the stated bounds.
• Does not fix leakage/EMF/stress-induced pseudo-drift; those must be controlled at the node.

• Can achieve extremely low effective offset under the intended clocked/evaluated usage.
• Offset bounds must be verified under the real mode, temperature, and stress envelope.
• Selection should be driven by the bounded offset/drift terms only (speed topics belong elsewhere).

• Lower Rth: scale divider impedance down (same ratio) to reduce Ibias×Rth and leakage×Rth.
• Buffer the threshold node: isolate sensor/divider source impedance so node currents do not translate into VTH shift.
• Reference/DAC terms: ref TC and ref noise enter the threshold budget as VTH_ideal drift/jitter; record them as explicit terms and verify endpoints.
• Leakage control: cleanliness, guarding, and leakage(T) validation prevent pseudo-drift from dominating the budget.

Calibration corrects repeatable structured error; it does not replace Rth reduction or leakage/gradient control.

• k = 2: basic worst-case separation when the environment is controlled and the budget is conservative.
• k = 3–5: adds margin for unmodeled effects (humidity, gradients, stress) and measurement uncertainty.
• Noise_margin is a practical allowance so random variations cannot repeatedly cross both thresholds.

• Resistor-network derivations for hysteresis are not included in this section.
• Detailed hysteresis design and calculations belong on the dedicated “Adding Hysteresis” page.
• This page focuses only on how Vos and drift move VTH+ / VTH− and how to size VHYS in the budget.

• Define a project upper bound for Rth so currents×R terms cannot dominate.
• Include an A/B plan: same divider ratio, 10× lower impedance to separate Vos/drift from currents×R.
• Record expected Ibias(max,T) and any protection-device leakage(T) as explicit budget terms.

• Specify allowed divider tolerance and TC that map into VTH_ideal error.
• Use worst-case assumptions for absolute accuracy reviews (typical numbers are for context only).
• Confirm the divider/common-mode operating point matches the comparator offset/drift test conditions.

• Series R adds impedance that can amplify Ibias×R and leakage×R near the trip point.
• Capacitors can introduce temperature-dependent leakage; treat as a drift-risk term.
• For slow-ramp inputs, require controlled dVin/dt during verification (do not assume one slope).

• Ref/DAC temperature coefficient maps directly into VTH_ideal drift.
• Ref/DAC noise becomes threshold jitter margin and must be included in the guardband.
• Filter/buffer details belong elsewhere; this checklist requires the terms to be logged and verified.

• Keep the threshold node short and isolated; avoid routing near contamination and leakage-prone areas.
• Maintain symmetry for sensitive inputs so stress/thermal gradients do not create direction-dependent shifts.
• Define a cleaning plan and verify humidity sensitivity (clean/dry A/B is required).
• Control thermal gradients near the node (avoid hotspots, airflow jets, and asymmetric copper heat paths).

• Use guard rings around high-impedance nodes to control surface leakage paths.
• Separate the threshold node from protection parts with uncertain leakage(T) unless proven by test.
• Provide a consistent return path for measurement and probing to avoid accidental thermal EMF loops.

• Add dedicated test points for threshold node, reference node, and source node to avoid probing artifacts.
• Document probe points and fixture contact materials to reduce uncontrolled thermocouple EMF.

• Use max over temperature for Vos and drift in absolute accuracy reviews.
• Confirm the drift bounds cover the project temperature window and the intended common-mode point.
• Consider package/mechanical sensitivity when tight window thresholds are required (stress steps consume guardband).
• For TVS/ESD/clamps, require evidence for leakage(T) or treat it as a mandatory verification item.

• Temperature: T_set, T_meas, stability window and stability threshold.
• Time: soak start/end, stable duration.
• Common-mode / node DC: Vcm or node bias point.
• Input slope: dVin/dt (slow-ramp tests must log slope).
• Trip points: record VTH+ and VTH− separately.
• Environment: humidity, cleaning state, coating state, airflow/gradient notes.
• Result: ΔVTH_total and dominant-term classification (Vos vs currents×R vs leakage vs stress).

Minimum log fields (must not be skipped)

• Switch matrices and cables can leak current that becomes ΔVTH through Rth.
• Always run a 10× lower impedance A/B to confirm whether currents×R dominates.
• Log humidity and cleaning state; leakage is often strongly temperature-dependent.

• Mixed metals and temperature gradients at contacts create µV-level EMFs.
• Use symmetric contacts and avoid directed airflow on only one side of sensitive nodes.
• Verify by localized heating/cooling and check for direction-dependent step shifts.

• Measurement inputs can load high-impedance nodes and shift the apparent trip point.
• Use buffers or low-impedance observation points when validating tight budgets.
• Keep probing consistent; random probing changes can look like “drift.”

• Allowable |ΔVTH_total| ≤ allocated budget (including guardband).
• Within the stability window, VTH change ≤ a defined fraction of the allowed |ΔVTH|.
• Repeatability: same-point repeats remain within a defined fraction of the allowed |ΔVTH|.
• Reproducibility: cross-day and fixture swaps remain within a defined fraction of the allowed |ΔVTH|.

• Use endpoint temperature points for screening when absolute thresholds are tight.
• Increase sampling for designs with high Rth or uncertain protection-device leakage(T).
• Record VTH+ and VTH− distributions and feed the worst-case tail into guardband decisions.
• Track fixture version, cleaning state, and software versions for traceability.

Upper and lower limits remain inside the required window across Tmin/Tmax, with bounded false-trip and missed-trip risk.

• Vos_wc shifts the entire window.
• ΔVos_temp sets endpoint worst-case error.
• Divider/ref TC moves VTH_ideal across temperature.
• If Rth is high: Ibias×Rth and leakage×Rth can consume the window.

• Start with the budget: identify whether Vos/drift or currents×R dominates.
• Use worst-case bounds over temperature; treat typical specs as context only.
• Reduce Rth and control leakage paths before relying on calibration.
• Size hysteresis from the drift/offset budget (rule-of-thumb belongs to the hysteresis section).

Measure VTH+ and VTH− separately at endpoints; run humidity/cleaning A/B if the node is high impedance or exposed.

Brown-in and brown-out thresholds remain consistent across temperature and across different supply ramp slopes.

• Divider tolerance/TC and reference TC move VTH_ideal.
• Offset/drift shifts the effective crossing point at endpoints.
• High divider impedance amplifies Ibias×R and leakage×R terms.
• Uncontrolled dV/dt produces inconsistent trip points in practice.

• Lower Rth and log currents×R terms explicitly in the budget.
• Record ref/divider TC terms as part of the trip-point envelope.
• Validate using stability-based soak criteria and controlled ramp slopes.

Sweep ramp slopes and log dVin/dt; confirm endpoint VTH shift stays within the guardband.

Compliance thresholds remain stable despite cable leakage, humidity, protection components, and field contamination.

• Leakage(T) from cables, PCB surfaces, and protection parts.
• High impedance nodes convert leakage into ΔVTH via leakage×Rth.
• Contact and routing asymmetry can create direction-dependent shifts under gradients.

• Treat leakage(T) as a mandatory verified term, not a footnote.
• Use isolation/spacing and guard rings to shorten and constrain surface leakage paths.
• Lower Rth or buffer the node so currents cannot dominate the trip-point budget.
• Record cleaning/coating state as part of the compliance qualification.

Run humidity/contamination A/B tests and temperature endpoints; validate protection-device leakage impact with the real Rth.

A slow-changing input crosses the threshold band once, without chatter, double counts, or window misclassification.

• Vos/drift shifts VTH+ and VTH− as a band.
• Too-small VHYS is consumed by drift and noise margins.
• High Rth makes bias/leakage currents appear as “drift” near the crossing region.

• Size VHYS from the offset/drift budget so the band remains valid at endpoints.
• Lower Rth and control leakage paths; do not let currents×R dominate the crossing region.
• Use calibration only when coefficients remain stable and measurement uncertainty is far below the target.

Run controlled slow-ramp tests and log dVin/dt; count toggles and measure the distribution of crossing voltages.

• Vos_max (over temp): worst-case absolute trip-point shift.
• Drift_max: endpoint drift envelope (do not assume linearity).
• Ibias(T): high impedance designs convert bias current into ΔVTH.
• Input leakage / protection leakage(T): humidity and temperature can dominate window accuracy.
• Internal hysteresis tolerance: VHYS variations can be consumed by drift and noise margins.
• Test conditions: temperature range, common-mode point, and any mode assumptions must match the application.

Comparisons must be done using max over temperature values under relevant test conditions. Typical values cannot close an absolute threshold accuracy budget.

Dominant risk: Ibias×Rth and leakage×Rth.

Demand: Ibias(T) bounds, leakage(T) evidence, and a verified Rth limit.

Dominant risk: surface leakage and protection leakage(T).

Demand: leakage vs temperature, cleaning/coating guidance, and humidity A/B validation plan.

Dominant risk: endpoint drift and mode-dependent offset.

Demand: drift_max over the full range, endpoint behavior, and test-condition match (Vcm, overdrive).

Dominant risk: Vos_max and drift_max consume the window.

Demand: max specs, hysteresis tolerance, and a verification plan that logs VTH+ and VTH− separately.

Application: [precision window / brown-in-out / remote compliance / slow-ramp sensing]
Temperature range: [Tmin … Tmax]
Threshold node impedance (Rth / source impedance): [value + notes]
Target worst-case |ΔVTH_total|: [mV]
Allowed false trips / mis-trips: [qualitative or quantitative]

Required bounds (max over temperature, with test conditions):
– Vos_max over temp: [ ]
– Drift_max (or dVos/dT bounds): [ ]
– Ibias(T): [ ]
– Input leakage / protection leakage(T): [ ]
– Internal hysteresis tolerance (if any): [ ]
Test conditions: [Vcm point, overdrive, mode assumptions]

Evidence requested:
– Leakage vs temperature / humidity sensitivity guidance
– Endpoint behavior and recommended verification method (VTH+ and VTH− measured separately)
– Any package/mechanical stress notes relevant to offset stability