Single-Pair Ethernet PHY (T1L/T1S/1000BASE-T1)
← Back to: Industrial Ethernet & TSN
H2-1 · Scope & Quick Router
Lock the page boundary first, then route to the correct SPE variant by distance, topology, or data rate.
Deliverables in this section
- One-page boundary map (what this page covers vs. what it excludes).
- A 3-choice quick router: Reach / Topology / Data rate.
Primary scenarios routed by this page
Long-reach point-to-point (process automation)
Typical intent: 1 km reach, harsh EMC, field wiring, PoDL co-design constraints.
Multidrop bus (single pair, multiple nodes)
Typical intent: multidrop wiring rules, spur/stub discipline, field-service diagnostics.
Automotive single-pair gigabit (cameras / domain controllers)
Typical intent: high data rate margin, parasitics sensitivity, EMC-shaped constraints.
Stop line (scope guard)
This page covers SPE PHY hardware reality: link-budget thinking, topology rules, PoDL co-design constraints,
intrinsic-safety-friendly hooks, layout, validation, and troubleshooting.
It does not implement TSN scheduling, industrial protocol stacks, PoDL controller internals, or certification clause-by-clause.
Jump to sibling pages when the question becomes…
- PoDL standards / classes / detection / allocation: go to the dedicated PoDL page.
- Intrinsic safety regulations & certification flow: go to the Isolation / Intrinsic Safety page.
- PROFINET / EtherCAT / CIP stack & certification: go to the Industrial Ethernet Stacks pages.
Quick Router (pick one entry)
Reach (distance / long cable / 1 km)
Route to T1L thinking: link budget, return path, EMC, and PoDL co-design constraints.
Topology (multidrop bus / spurs / stubs)
Route to T1S thinking: multidrop wiring discipline and spur-control first.
Data rate (gigabit / cameras / domain controllers)
Route to 1000BASE-T1 thinking: parasitics sensitivity, EMC shaping, and validation margin.
Note: Anchors point to later sections of this page; keep reading if the exact subsection is not yet visible.
Diagram · Where this SPE PHY page sits in the Industrial Ethernet universe
Read it as: use the router (reach/topology/data rate) to stay within this page for PHY hardware + validation,
and jump out only when the topic becomes PoDL standards, certification, protocol stacks, or protection deep-dive.
H2-2 · Variant Matrix (T1L vs T1S vs 1000BASE-T1)
Select the correct SPE branch by topology first, then reach, then data rate. Avoid mixing these axes.
10BASE-T1L (long-reach, point-to-point)
- Topology: point-to-point over a single pair.
- Reach driver: long cable and harsh EMC; link budget is the primary lens.
- Power coexist: often paired with PoDL; return-path and surge routing matter.
- Typical use: process automation, remote I/O, long-run sensors.
- Key constraint: margin is consumed by impedance discontinuities, shielding/grounding, and power transients.
Risk tag:
return-path breaks and protection parasitics eat margin
10BASE-T1S (multidrop bus)
- Topology: multidrop bus with multiple nodes on one pair.
- Reach driver: wiring discipline beats “chip specs” in field reliability.
- Power coexist: can coexist, but the bus is sensitive to stubs/spurs and coupling paths.
- Typical use: distributed sensors/actuators, machine wiring simplification.
- Key constraint: spur/stub control and node attachment are the first-order stability gates.
Risk tag:
multidrop instability from unmanaged spurs/stubs
1000BASE-T1 (gigabit single pair, automotive)
- Topology: point-to-point, high data rate over a single pair.
- Reach driver: high bandwidth; parasitics sensitivity dominates.
- Power coexist: co-design exists, but signal integrity and EMC shaping become critical.
- Typical use: cameras, sensors, domain controllers.
- Key constraint: connector and protection parasitics can degrade return loss and push re-train events.
Risk tag:
high-rate margin collapse from small parasitics + EMC coupling
Three hard selection rules (engineering-first)
- Topology first: if the wiring is a multidrop bus (multiple nodes on one pair), prioritize T1S and treat spur/stub control as a non-negotiable gate.
- Reach and power: if the requirement is long cable with field wiring and possible single-line power, prioritize T1L and design using a link-budget + return-path lens (PoDL constraints are part of the PHY margin).
- Rate and parasitics: if the requirement is gigabit throughput, prioritize 1000BASE-T1 and treat connector/protection parasitics and EMC coupling as first-order risks.
Common misconceptions to avoid (scope-safe)
- Distance ≠ topology: long reach does not imply multidrop is safe; topology discipline must be validated explicitly.
- Power is not “just power”: PoDL transients and return paths can directly consume PHY margin.
- Stronger protection is not always better: TVS/CMC parasitics and mismatch can degrade return loss and stability.
- Scope looks clean ≠ link is healthy: counters and margin tests (PRBS/loopback + disturbance) are required for repeatable evidence.
Diagram · Variant matrix: pick by topology, then reach, then rate
Practical usage: pick the branch once here, then keep the rest of the page strictly within that branch’s constraints and failure modes.
H2-3 · Link Budget Thinking (Why 1 km can work)
Treat stability as margin management: every failure must map to a budget item (loss, return loss, noise/CM, EMI/return path, and environment).
Deliverables
- A budget template (loss / return loss / noise / EMI & return path / environment / remaining margin).
- A routing map from symptoms to budget items (what to measure and what knob to turn first).
Link Budget Template (fill with evidence, not guesses)
Use this structure to keep analysis and fixes within a single shared accounting model.
1) Insertion Loss (Cable attenuation)
- Symptom signature: works short cable, fails long cable; margin collapses with temperature.
- Measure: cable type/length inventory; attenuation/eye-margin proxy; compare lots and vendors.
- Knobs: cable media, connectors, equalization options, routing away from noise bundles.
- Pass criteria: loss budget within X dB and margin > X (placeholder).
2) Return Loss (Reflections from discontinuities)
- Symptom signature: intermittent errors at specific harnesses; worse after adding TVS/CMC or extra connectors.
- Measure: TDR/return-loss scan; connector and protection parasitics review; impedance steps by segment.
- Knobs: termination/coupling network, protection placement, connector choice, stub elimination.
- Pass criteria: return-loss margin within X dB across band (placeholder).
3) Noise & Common-Mode (CM injection)
- Symptom signature: differential waveform looks acceptable, but counters grow; errors correlate with motor/relay events.
- Measure: CM noise vs. error counters; correlation with power events; shield bond A/B tests.
- Knobs: return path continuity, shield termination strategy, CMC tuning, isolation boundaries.
- Pass criteria: CM noise below X and error rate stable within X (placeholder).
4) EMI & Return Path (Ground/shield current routing)
- Symptom signature: passes in bench, fails in system; more fragile after ESD/surge; sensitive to shield/ground changes.
- Measure: return-path inspection (plane cuts, via jumps); shield current path; immunity A/B configurations.
- Knobs: 360° shield bond placement, Y-cap locations, plane continuity, surge return path planning.
- Pass criteria: immunity test stable with margin > X (placeholder).
5) Environment (Temperature / humidity / aging)
- Symptom signature: worse in winter/dry air; margin shifts with temperature; “works for 10 minutes then drops”.
- Measure: log temperature, supply, error counters, ESD events; compare across lots and harness variants.
- Knobs: thermal design, component derating, connector retention, shielding/grounding robustness.
- Pass criteria: stability across temperature range with errors ≤ X (placeholder).
Remaining Margin (what is left after all deductions)
The remaining margin should be proven by validation evidence (counters + stress tests), not by “it works once”.
Keep a placeholder threshold: Margin > X.
Symptom → Budget Routing (first accounting check)
Intermittent link drop / re-train
Primary: Return loss or EMI/return path margin consumed. Secondary: environment drift.
First check: correlate counters with temperature, power events, and harness variants.
Bench OK, field fails on long cable
Primary: insertion loss + return loss combined. Secondary: common-mode injection.
First check: cable media/length inventory and TDR/return-loss scan around connectors and protection.
Waveform looks fine, counters grow
Primary: noise/CM and return path. Secondary: protection mismatch.
First check: measure CM noise, compare shield bond strategies, and look for plane cuts or long return routes.
Worse in winter / dry air
Primary: environment + ESD events consuming margin. Secondary: shield/ground leakage paths.
First check: event logs + ESD exposure correlation; verify shield termination and surge return routing robustness.
Core accounting concepts (keep it actionable)
Insertion loss (slow margin erosion)
Long cable attenuation reduces eye opening; margin decreases gradually with distance and temperature.
Return loss (time-domain uncertainty)
Discontinuities (connectors, stubs, protection parasitics) create reflections that consume margin in bursts.
Common-mode & return path (hidden budget eater)
A clean differential trace does not guarantee a clean decision if CM noise and shield/ground currents run through sensitive regions.
Diagram · Margin funnel (deductions by layer)
Interpret the funnel as accounting: each layer consumes margin. A stable 1 km design proves that the remaining margin stays > X under stress.
H2-4 · Topologies & Wiring Rules (Allowed / Risky / Forbidden)
Topology is a first-order stability gate. Classify wiring as Allowed, Risky, or Forbidden before tuning any settings.
Deliverables
- Topology allowlist: Allowed / Risky / Forbidden.
- Stub/spur limits as placeholders: X (to be filled consistently later).
Allowed
- Point-to-point long reach: one continuous pair between endpoints, minimal discontinuities.
- Controlled connector strategy: shield bond and return path planned near entry.
- Protection placed with impedance continuity: low mismatch and short return routes.
Evidence expectation: stable counters under stress with margin > X.
Risky
- Extra connectors or adapters: more impedance steps; return loss must be proven by measurement.
- Short stub node attachments (T1S): allowed only if stub length ≤ X and attachment style is consistent.
- Mixed shield bonding schemes: can create unpredictable CM paths; requires A/B evidence.
Gate rule: acceptable only with explicit validation evidence (TDR/return-loss + counters).
Forbidden
- Hidden T-branch: an unplanned branch added in the harness; creates reflections and unpredictable CM paths.
- Long stubs / long drop lines: stub length > X (placeholder) is rejected without exception.
- Return-plane cuts under the PHY front-end: forces return currents to detour and inject CM noise.
Policy: redesign the wiring/PCB first; tuning cannot compensate for forbidden structures.
Point-to-point long cable (focus points)
- Connector & shield entry: plan the shield-to-chassis bond and keep shield current out of sensitive PHY ground.
- Coupling/termination network: protect impedance continuity; treat protection parasitics as part of the channel.
- Return path continuity: avoid plane splits and long detours; keep the front-end reference stable.
Multidrop (T1S) bus: spur/stub discipline (PHY view)
- Trunk first: keep a continuous trunk; minimize impedance steps along the trunk.
- Node attachments: keep stubs short and consistent; treat every node as a potential reflection point.
- Field modifications: reject unplanned T-branches; enforce a wiring checklist for service actions.
Five common wiring traps (fast identification)
1) Hidden T-branch added in the harness
Risk: return loss spikes + unpredictable CM path. Quick check: harness inspection + TDR reflection point.
2) Long drop line (stub) at a single node
Risk: reflection timing becomes dominant. Quick check: measure stub length; compare to placeholder limit X.
3) Mixed shield bonding strategy across nodes
Risk: CM current reroutes through sensitive ground. Quick check: A/B test shield bond location and log counters.
4) Protection cluster causes mismatch
Risk: parasitic imbalance degrades return loss. Quick check: compare vendors/placements; look for ΔC and asymmetry.
5) Return-plane cut near the PHY front-end
Risk: return detour injects CM noise. Quick check: inspect plane continuity and via transitions under the front-end path.
Diagram · Topology atlas (Allowed / Risky / Forbidden)
Use the atlas as a design gate: classify wiring first, then validate with evidence (TDR/return-loss + counters) before optimizing settings.
H2-5 · PHY Front-End Co-Design (MDI, coupling, termination, ref clock)
This section provides a schematic-ready hardware skeleton: mandatory blocks, what risks each block controls, and how to validate stability with counters and stress tests.
Deliverables
- Front-end module checklist: ref clock, PHY sensitive zone, MDI network, termination / CM handling, MAC-side interface.
- Key parameter list: impedance, parasitics, mismatch, tolerance, and temperature-sensitive items.
Front-End Module Checklist (schematic-ready)
Arrange blocks left-to-right as they appear on the signal path. Each block must map to a stability risk and a validation handle.
A) Host / MAC-side interface
- Interface: MAC ↔ PHY digital bus (type as placeholder).
- Risk controlled: mis-strap / mis-config can mimic SI issues (false root cause).
- Validation handle: readback config + link training stats + error counters.
B) Reference clock (RefClk) block
- What to include: clock source (placeholder), supply decoupling, and a quiet return reference.
- Risk controlled: clock noise/jitter raises re-train probability and widens performance spread.
- Validation handle: A/B clock source or routing isolation; compare re-train rate distribution under stress.
C) PHY front-end sensitive zone (power/ground boundary)
- What to define: which currents must not cross the analog front-end reference region.
- Risk controlled: return-path detours and shield current injection create hidden CM budget loss.
- Validation handle: correlate CM noise and error counters with power/shield events.
D) MDI / coupling network (Diff path vs CM path)
- Diff path: series/coupling elements that preserve impedance continuity (placeholders).
- CM path: CMC / CM shunt path shaping and shield boundary.
- Risk controlled: DM↔CM conversion and reflection timing.
- Validation handle: TDR/return-loss scan + CM noise measurement + counter correlation.
E) Termination & impedance continuity (treated as a system)
- System view: termination + connector + cable + ESD/CMC parasitics must be evaluated together.
- Risk controlled: return-loss spikes and reflection bursts that consume margin.
- Validation handle: return-loss vs. harness variants; re-train/error counters under environmental stress.
F) Connector & shield boundary (to cable/channel)
- Boundary decision: shield bond location and the intended return path.
- Risk controlled: shield current entering the PCB reference region.
- Validation handle: A/B shield bonding and immunity tests while logging counters.
Key Parameters (organized by margin impact)
Impedance & return loss
Sensitives: impedance steps, series parasitics, component tolerance, DM asymmetry (ΔC/ΔL).
Validation: TDR/return-loss scan + harness A/B comparison + counter correlation.
Common-mode & return path
Sensitives: CM leakage of CMC, shunt locations, shield bond routing, plane cuts.
Validation: CM noise vs. counters, immunity A/B with controlled return paths.
Reference clock & coupling
Sensitives: clock jitter, supply noise coupling into ref clock, clock routing near MDI/AFE.
Validation: A/B clock source or isolation; compare re-train and error statistics under stress.
Temperature drift & aging
Sensitives: connector contact, parasitic drift of protection parts, material change.
Validation: log temperature + counters; prove margin > X across the full operating range.
Front-End Design Gate (non-negotiables)
- System termination view: termination, connector, cable, and protection parasitics are evaluated as one channel.
- Return path continuity: no reference-plane cuts under the PHY front-end and MDI region.
- Clock isolation: keep ref clock routing and supplies away from the MDI/AFE sensitive zone.
- Validation evidence: TDR/return-loss + counters under stress; pass criteria uses placeholder X.
Diagram · PHY front-end skeleton (MAC ↔ PHY ↔ MDI ↔ connector ↔ cable)
Keep the skeleton schematic-first: every block must have a risk it controls and a validation handle (TDR/return-loss + counters under stress).
H2-6 · PoDL Co-Design for SPE (how power overlay breaks PHY margin)
PoDL is covered here only as constraints on PHY reliability: coupling, return paths, transients, thermal rise, and line-loss effects that consume link margin.
Stop line (scope guard)
No PoDL classes, detection, or controller state machines here. Only PHY-facing constraints and validation entry points.
Deliverables
- PoDL co-design constraint checklist: return path, transients, thermal rise, line loss, EMI coupling.
- Troubleshooting entry points: ripple, surge/step events, CM noise, temperature rise (all mapped to budget items).
PoDL Co-Design Constraints (PHY-facing)
1) Return path control
Rule: power/surge return currents must not cross the PHY front-end reference region.
Validation: A/B shield bond and return-path routing while logging CM noise and error counters.
2) Transients (plug, load steps, start-up)
Risk: transient ground bounce and CM jumps trigger re-train/drop.
Validation: correlate counters with step events; prove stability with pass criteria ≤ X errors (placeholder).
3) Thermal rise & long-run heating
Risk: I²R line loss and temperature drift consume remaining margin.
Validation: log ΔT and counters; hold ΔT ≤ X and margin > X (placeholders).
4) Line-loss effects (power overlay)
Risk: compensation or regulation behavior can increase ripple/EMI and consume PHY margin.
Validation: accept only if re-train/error distributions stay within X under worst-case load profiles.
5) EMI coupling between power and data
Risk: larger loop area and CM injection make the link “fragile” in system.
Validation: immunity A/B tests with controlled return paths; monitor CM noise and counters continuously.
When PoDL “makes it worse”: first routing checks
Ripple increases → Noise/CM budget
First check: CM noise and counters correlation; verify return path does not run through the PHY sensitive zone.
Surge/load-step → Return path / immunity
First check: where surge return current flows; ensure short, intentional return and no plane cuts at the front-end.
Temperature rise → Environment budget
First check: ΔT over time and harness variants; prove stability across temperature with pass criteria ≤ X.
Errors correlate with load changes → Mixed budget
First check: return-loss changes (connector/protection) and CM injection (shield bond/return path) before tuning parameters.
Diagram · Data + power overlay and return-path discipline
The decisive factor is return-path discipline: keep surge/load-step return currents out of the PHY front-end sensitive area and prove stability with counter statistics.
H2-7 · Intrinsic-Safety-Friendly Design Hooks (energy control)
“Intrinsic-safety friendly” is treated as energy control in circuits: where energy is stored, how faults release it, and how the discharge path is kept within a controlled boundary.
Stop line (scope guard)
No clause-by-clause regulatory interpretation here. Only engineering hooks and verification criteria with placeholder threshold X.
Deliverables
- Intrinsic-safety co-design checklist: storage (C/L), fault injection points, and controlled discharge paths.
- Risk annotations: which capacitors / TVS / coupling parts change the system “energy profile”.
Energy-Profile Thinking (source → storage → fault → discharge → controlled boundary)
1) Identify energy sources
Include all paths that can inject energy into the channel: supply overlay, transient events, and external coupling. Treat each as a source that must be routed to a defined boundary.
2) Enumerate storage elements (C/L + parasitics)
List all components that store or reshape energy: decoupling capacitors, shunt capacitors, magnetics, and protection parts. Include parasitic C/L that can dominate in fast faults.
3) Define worst-case fault triggers
Use repeatable fault injections: open/short, plug/unplug, shield discontinuity, and transient steps. Each trigger must map to a specific discharge path and a measurable outcome.
4) Enforce controlled discharge paths
Discharge must land at a defined destination (chassis/shield/PCB ground boundary) without crossing sensitive regions. Define “allowed” and “forbidden” routes.
Intrinsic-Safety Co-Design Checklist (engineering hooks)
Storage control (C/L inventory)
- List every capacitor and inductor that can store energy (including parasitics).
- Mark which parts can change the “energy profile” during fast faults (dominant storage).
- Keep the energy boundary measurable with a verification threshold X.
Fault injection points (repeatable)
- Define injection points for open/short/plug/shield-break events.
- For each, record: discharge destination, sensitive regions to avoid, and recovery behavior.
- Require reproducibility: same injection → same measured signature.
Controlled discharge path definition
- Make the discharge path short and land it at a defined boundary point.
- Explicitly forbid discharge current from crossing the PHY front-end sensitive area.
- Validate with event logging + waveform capture + pass criteria ≤ X.
Risk Annotations (parts that change the energy profile)
Shunt capacitors (to chassis/ground)
Changes: discharge landing point and return distribution. Hook: place at the boundary point; avoid pulling return into board interiors.
TVS / protection parts
Changes: clamp path and energy dump location. Hook: keep the clamp loop short and land energy at a defined boundary.
Coupling / magnetics / CMC
Changes: CM impedance and leakage paths at high frequency. Hook: treat leakage as part of the discharge path and keep it outside sensitive regions.
Verification criteria (controlled behavior)
- Fault injection: use repeatable open/short/plug/shield-break events with documented injection points.
- Observables: waveform at boundary nodes, thermal rise, link recovery time, and error/re-train counters.
- Pass criteria: controlled discharge signature + recovery within X + counters ≤ X (placeholders).
Diagram · Energy loop and controlled boundary (source → storage → fault → discharge)
Treat every C/L and protection part as a storage/transfer element that can change fault energy. Enforce a controlled boundary and verify with repeatable injections.
H2-8 · EMC, Shielding & Grounding (common-mode and return paths)
EMC is treated as a return-loop design problem. Long cables are dominated by common-mode currents and unintended return routes—even when the differential waveform looks acceptable.
Deliverables
- Shield/ground strategy matrix: 360° bonding, Y-cap coupling, single-point vs multi-point trade-offs.
- Return-path inspection checklist: 5 must-check items for long-cable reliability.
Shielding & Grounding Strategy Matrix (engineering trade-offs)
360° shield bond at connector
- Best for: high-frequency CM control near the boundary.
- Primary risk: poor mechanical bond creates intermittent CM injection.
- Layout hook: bond at the connector boundary; keep loop short and wide.
- Verification: immunity test with counters; A/B bond quality and location.
Y-cap coupling to chassis (boundary coupling)
- Best for: shaping CM impedance without forcing DC ground loops.
- Primary risk: placement away from boundary pulls return into the board.
- Layout hook: place at the boundary point; keep return away from sensitive zones.
- Verification: CM noise vs counters; confirm improvement is stable across environments.
Single-point vs multi-point bonding (controlled trade)
- Best for: managing low-frequency loops vs high-frequency CM currents.
- Primary risk: unintended return routes near the PHY front-end.
- Layout hook: define explicit boundary nodes and forbid crossings.
- Verification: A/B grounding topology; correlate CM current and re-train rates.
Return-Path Inspection Checklist (5 must-check items)
- Connector boundary: shield bond is short, wide, and near the boundary (no long pigtails).
- Sensitive zone protection: shield/chassis currents do not flow through PHY front-end reference regions.
- Plane continuity: no return-plane cuts under the MDI/front-end routing region.
- Boundary capacitors: chassis/shield coupling parts are placed at the boundary point, not inside the board.
- Power vs signal returns: PoDL/surge returns are layered and controlled; no accidental mixed loops.
Why “differential looks fine” but the link still drops
- Hidden CM budget loss: common-mode injection shifts decision margins and training stability.
- Return detours: unintended loops increase CM voltage at the front-end.
- Proof method: toggle the suspected loop/bond and correlate CM noise + counters + re-train events.
Diagram · Shield/return-path cross-section (connector → chassis → PCB ground → sensitive zone)
The stable solution is the one with a defined boundary: shield currents close at the chassis bond point and never detour through PCB planes near the front-end.
H2-9 · Protection Co-Design (ESD/Surge/TVS/CMC)
Protection must be treated as part of the channel. Immunity improves only when protection parts preserve impedance continuity, control return paths, and avoid converting common-mode events into front-end stress.
Deliverables
- Checklist: how protection parts consume link budget (Cdiff, mismatch, parasitics, leakage, drift).
- Placement rules: near connector vs near PHY (decision criteria).
Protection Parts That Consume Budget (what to audit)
Cdiff and mismatch (ΔC / ΔL)
Differential capacitance is only the starting point. The failure trigger is often mismatch between the two lines, which increases mode conversion and worsens return loss.
Parasitics and stub creation
Pads, vias, and routing detours around protection parts create impedance steps and micro-stubs that amplify reflections on long cables.
Leakage and drift (temp / aging)
Leakage and parameter drift can move the “quiet” operating point and reduce margin over time—especially when the return path is not tightly controlled.
CM leakage paths (CMC/TVS interaction)
A protection stack can unintentionally provide a CM path into the PCB reference region. The result is “differential looks fine” but re-train/drop statistics degrade.
Placement Rules (connector vs PHY)
Near connector: best for ESD/Surge capture
- Goal: clamp energy at the boundary and keep high-current loops short.
- Rule: TVS loop is tight; return lands at the defined boundary point (chassis/shield/ground policy).
- Risk: poor symmetry or via stubs create mismatch and reflections.
Near PHY: best for protecting the front-end pins
- Goal: reduce the distance from protection to sensitive pins when connector-side capture is insufficient.
- Rule: do not create a long “unprotected corridor” from connector to PHY.
- Risk: protection parts inside the board can inject CM currents into the sensitive region.
Decision criterion (use one sentence per design review)
Place clamps where they shorten the high-current loop and avoid crossing the PHY sensitive zone, while keeping the diff channel impedance continuous and symmetric.
Engineering Control Points
TVS: “low capacitance” is not enough
- Control: symmetry (ΔC) and routing parity on the two lines.
- Control: short clamp loop with a defined landing point.
- Proof: return-loss / reflection signature stays stable; error counters ≤ X (placeholder).
CMC: CM suppression can create DM side effects
- Control: minimize DM leakage and keep the diff pair symmetric through the part.
- Control: avoid extra stubs (via pairs and pad escapes).
- Proof: CM improves without increasing re-train / CRC statistics beyond X (placeholder).
Surge return in PoDL scenarios (co-design only)
- Control: define the surge return route and keep it out of the PHY front-end reference region.
- Control: clamp currents close to the boundary to avoid board-wide current spread.
- Proof: during surge-like events, the link recovers and counters remain within X (placeholder).
Diagram · Protection placement map (Connector → TVS → CMC → MDI → PHY)
Protection succeeds only when clamp currents land at a defined boundary and the diff channel remains symmetric through the entire protection stack.
H2-10 · Layout & PCB Implementation (keep the margin)
Layout rules are written as an inspection checklist. The objective is to preserve return-path continuity, avoid CM injection into sensitive regions, and prevent protection parts from turning into impedance discontinuities.
Deliverables
- Layout Do/Don’t list: plane continuity, vias, isolation, sensitive distances, and connector/protection priority.
- “Three screenshots” acceptance steps: quick, repeatable verification.
Layout Do / Don’t (audit-ready)
DO
- Keep reference planes continuous under MDI/front-end routing (no plane cuts).
- Route diff pairs as a “channel corridor”: consistent geometry and symmetry through parts and pads.
- Use via pairs symmetrically and minimize via count; keep stubs controlled.
- Place connector + clamp as a boundary set: clamp loops short; return lands at the defined boundary point.
- Define a clean zone around the PHY front-end: keep switching currents and noisy clocks away.
DON’T
- Do not break the return path with plane splits or slots under the MDI corridor.
- Do not create asymmetry (different pads/vias/branches) on the two lines of the pair.
- Do not route protection return currents through the PHY sensitive region.
- Do not place clamps deep in the board if it forces long high-current loops across the PCB.
- Do not place noisy power/clock routing adjacent to the MDI/front-end region.
“Three screenshots” acceptance steps (quick verification)
Screenshot #1 · MDI corridor + plane continuity
Capture top layer routing plus the reference plane view. Pass if the pair stays symmetric and the plane under the corridor is continuous (no cuts/slots).
Screenshot #2 · Connector + protection stack + clamp loops
Capture connector, TVS/CMC/MDI parts, and their return paths. Pass if clamp loops are short and land at the boundary point without crossing the sensitive region.
Screenshot #3 · Noise isolation (clock/power vs sensitive zone)
Capture PHY front-end region and nearby clock/power routing. Pass if switching loops and clock routes are outside the defined clean zone and do not share return paths with the front-end.
Placement priority (to preserve margin)
- Boundary first: connector + shield/bond policy define where currents must close.
- Clamp loop second: TVS return is short and lands at the boundary point.
- Channel corridor third: CMC/MDI elements stay symmetric and avoid stubs.
- Sensitive zone last: PHY front-end is protected by clean reference and isolation from noisy loops.
Diagram · Layout zone heatmap (priority and keep-out)
The margin is preserved when the MDI corridor stays symmetric on a continuous reference plane and noisy power/clock loops remain outside the PHY clean zone.
