123 Main Street, New York, NY 10001

Submit Your BOM

USB PHY (2.0/3.x/4): Electrical, SSC & Jitter Design

USB PHY (2.0/3.x/4): Electrical, SSC & Jitter Design

← Back to: USB / PCIe / HDMI / MIPI — High-Speed I/O Index

USB PHY is the electrical “truth layer” that turns digital bits into compliant signals across real channels. This page shows how to plan and validate margin (channel loss, refclk/jitter/SSC, power noise, and port protection) so links stay stable from design to production.

H2-1 · Definition & Scope of USB PHY (2.0/3.x/4)

What this chapter clarifies
  • What a USB PHY is responsible for at the electrical boundary (waveform, clocking, channel tolerance).
  • What problems belong to this page (PHY/SI/jitter/SSC/bring-up) and what must be handled by sibling pages.
  • Where discrete PHYs appear in real systems (SoC/bridge externalization, compliance-driven integration).
Card A · What a PHY does (electrical responsibilities)
A USB PHY converts controller-side digital signaling into channel-side electrical waveforms that survive real traces, connectors, and cables, then converts those waveforms back into clean digital decisions at the receiver.
Engineering view (measurable objects)
  • Transmit waveform synthesis: edge shape / amplitude / pre-emphasis, plus how SSC is injected.
  • Receive waveform recovery: EQ (CTLE/DFE class), sampling margin, and clock recovery stability.
  • Clock discipline: reference quality → PLL/CDR → jitter at the sampling point (RMS/pp, templates).
  • Impedance discipline: termination accuracy, differential symmetry, continuous return path.
  • Manufacturability: repeatable test modes (loopback/PRBS), stable margins across temp/voltage/process.
Primary observables (typical)
  • Eye opening: height/width (reference plane defined), plus margin vs. limits (X).
  • Jitter: total / random / deterministic components (template-based), pass margin (Y).
  • Channel budget: insertion/return loss + crosstalk (NEXT/FEXT) against a target (Z).
Card B · Scope / Out-of-scope (no-overlap boundary)
In scope (this page)
  • USB 2.0 HS/FS/LS electrical behaviors: termination concepts, edge/EMI trade, measurement artifacts.
  • USB 3.x / USB4 electrical planning: channel loss vs EQ, reference clock quality, SSC/jitter templates.
  • Bring-up and pass criteria: loopback/PRBS, eye/jitter measurement reference planes, repeatable acceptance checks.
Out of scope (handled by sibling pages)
  • Controller logic: enumeration, classes (UASP/MSC/CDC), OTG/role state machines.
  • Type-C routing: orientation flip, SBU handling, Alt-Mode switch/mux policies.
  • Retimer/redriver selection: system-level reach extension and equalization tuning strategies.
Card C · Where discrete PHYs appear (system triggers)
Discrete PHYs commonly appear when the analog boundary must be strengthened, isolated, or made more testable than the SoC’s native capability.
  • Analog strength gap: native PHY does not meet channel reach, jitter, or compliance margin.
  • Integration constraints: package/escape routing makes native signals too fragile at the connector boundary.
  • Clock cleanliness needs: refclk distribution and SSC/jitter template compliance requires tighter control.
  • Testability needs: deterministic PRBS/loopback hooks are required for bring-up and production screens.
Diagram · System placement map (PHY boundary)
System placement map — USB PHY electrical boundary SoC / Controller Digital logic Discrete USB PHY Tx / Rx • PLL • CAL Connector Port-side Cable Channel USB2 D+ / D− (HS) USB3/4 Diff pairs (SS / SSP) Refclk SSC template Low-C ESD
Reading guide: treat this page as the electrical boundary between controller logic and the real channel. Anything that depends on waveform integrity, clock cleanliness, or pass/fail measurements belongs here.

H2-2 · Rate Families & Physical Channels (HS / SS / SSP)

Why rate families matter
Every debug and every pass criterion must start with two labels: rate family and physical channel. The dominant failure mechanism shifts as speed increases—edge/termination issues dominate at HS, while channel loss and clock/jitter dominate at SS/SSP.
Card A · Rate ladder (structure, not a number dump)
Think in terms of first-order constraints that become dominant as speed increases:
  • HS (USB2): edge shape, termination/return path, and port-side parasitics (ESD/C). Primary tool: time-domain waveform sanity.
  • SS (USB3.x): insertion loss + discontinuities + crosstalk drive eye closure; EQ becomes the main knob. Primary tool: channel budget + eye at a defined reference plane.
  • SSP (USB4-class): low-jitter reference and template compliance become decisive; thermal and supply noise consume margin quickly. Primary tool: jitter/template + margin stability over conditions.
Pass-criteria framing (placeholders)
  • HS: stable waveform against masks, no systematic edge distortion under worst-case loading (X).
  • SS: eye opening and BER margin meet target across the intended channel budget (Y).
  • SSP: jitter/template margin remains positive across voltage/temperature and reference clock variations (Z).
Card B · Channel taxonomy (channel = measurement contract)
  • USB2 channel: D+/D− behaves like an edge/termination problem; parasitic C and return discontinuities show up directly in time-domain shape.
  • USB3/4 channel: differential pairs behave like a loss/discontinuity/jitter-budget problem; define the reference plane (near-end / connector) before comparing results.
  • Lane symmetry rule: treat mismatch as a measurable penalty (skew/amplitude imbalance) that reduces eye margin and complicates EQ.
Dominant risks (by family)
  • HS: reflection from impedance breaks + parasitic C near the port.
  • SS: insertion loss + crosstalk + discontinuities (vias/connectors).
  • SSP: jitter template margin + refclk cleanliness + noise/thermal drift.
Card C · Typical symptoms (physical-layer first checks)
Symptoms are mapped to a first physical-layer check (no controller-state details).
  • HS links but behaves “fragile”: first check port-side parasitic C symmetry (ESD/connector) and return path continuity.
  • SS stable on short setup, fails on real channel: first check insertion-loss budget and locate the biggest discontinuity (via/connector/cable transition).
  • SSP fails only with temperature/load: first check refclk cleanliness and PLL/supply noise coupling; confirm template margin at the defined plane.
Debug discipline
  • Always label results with family + channel + reference plane + conditions (cable, temperature, rails).
  • Separate variables in this order: refclk → power noise → channel loss/discontinuities → EQ.
Diagram · Rate family → channel type → dominant risk
Rate-to-channel map — family, channel, and dominant risk Rate family Channel type Dominant risk HS USB2 D+ / D− Reflection Parasitic C SS Diff pairs (USB3.x) Insertion loss Crosstalk SSP Diff pairs (USB4) Jitter template Refclk Use this map to tag every measurement: family + channel + dominant risk + reference plane

H2-3 · PHY Architecture Blocks (Tx/Rx/PLL/Calibration)

What this chapter establishes
  • A module-level map of the PHY signal chain so later topics (clock/jitter, EQ, SI, tests) anchor to a specific block.
  • A consistent vocabulary for knobs and observables: PLL / CDR / CTLE / DFE / TERM / CAL.
  • A “cause → measurement point → pass criteria” mindset (numbers kept as placeholders X/Y/Z).
Card A · Tx path blocks (DRIVER / PRE-EMP / SLEW)
The transmit path synthesizes channel-ready waveforms. At higher rates, the dominant job is to counter insertion loss without creating excessive ringing or common-mode radiation.
Knobs (conceptual)
  • Swing: amplitude headroom vs. EMI and device stress.
  • Pre-emphasis: high-frequency boost to counter channel loss (avoid over-boost that amplifies noise).
  • Slew control: edge rate trade-off (faster is not always better).
Observables
  • Near-end eye: height/width at a defined reference plane (X).
  • Ringing: overshoot/undershoot magnitude and decay time (Y).
  • Common-mode behavior: sensitivity to return-path discontinuities and asymmetry (Z).
Typical signatures
  • Short channel OK, long channel fails: insufficient high-frequency energy at the receiver; pre-emphasis may be under-set or the channel discontinuity is dominant.
  • EMI fails while link “works”: edge rate too fast or return path broken, converting differential energy into common-mode radiation.
Card B · Rx path blocks (CTLE / DFE / DECISION / CDR)
The receive path recovers decisions from a degraded waveform. At SS/SSP rates, channel loss and jitter tolerance determine whether the sampling point remains inside the eye.
Block roles
  • CTLE: linear equalization to reshape frequency response and recover eye height.
  • DFE: post-cursor correction to reduce ISI when loss/discontinuities dominate.
  • CDR: sampling clock recovery; sets jitter tolerance and lock robustness.
Observables
  • Eye at Rx: margin at the defined plane after EQ (X).
  • Jitter tolerance: template-based pass margin (Y).
  • Error rate: stable BER/FER over a time window under worst-case conditions (Z).
Typical signatures
  • Errors correlate with temperature/load: CDR/PLL sensitivity to supply noise or thermal drift consumes margin.
  • Scope looks OK but link unstable: measurement plane/fixture masks the true Rx sampling margin; validate reference plane and test method.
Card C · PLL / Refclk / SSC insertion (clock-to-margin chain)
Reference clock quality propagates through PLL/SSC and appears as sampling jitter. This chain must be treated as a measurable contract: refclk → PLL/SSC → jitter template → eye margin.
Key ideas
  • Refclk cleanliness: integrated jitter / spurs map into sampling uncertainty (X).
  • SSC purpose: spread spectral energy to reduce EMI peaks; verify against jitter templates (Y).
  • Coupling paths: PLL rails and ground integrity can translate power noise into jitter (Z).
Card D · Calibration (TERM / OFFSET / GAIN / TEMP)
Calibration makes analog behavior repeatable across process/voltage/temperature. When calibration is weak or unstable, issues often appear as intermittent link failures rather than a clear “calibration error”.
Calibration targets
  • TERM: effective termination accuracy and symmetry.
  • OFFSET/GAIN: decision threshold stability and amplitude headroom.
  • TEMP drift: margin stability after warm-up and across ambient changes.
Typical signatures
  • Cold-start is worse than warm-restart: insufficient settle/cal window or marginal TERM calibration.
  • Works briefly, then degrades: thermal drift consumes margin; calibration policy is not tracking conditions.
Diagram · PHY internal block diagram (module anchors)
USB PHY internal blocks — PLL/SSC, Tx, Rx, CDR/EQ, TERM, CAL REFCLK PLL SSC TX DRIVER CHANNEL TRACE/CABLE RX CTLE/DFE CDR SAMPLING DIG I/F PCS/LOGIC TERM MATCH CAL OFFSET/GAIN/TEMP TEST PRBS/LOOP
Practical use: map each symptom to a block, then validate at the nearest measurable node (Tx tap, channel plane, Rx sampling).

H2-4 · USB 2.0 PHY Deep Dive (HS/FS/LS electrical essentials)

What this chapter focuses on
  • USB2 PHY problems are often dominated by edge / termination / return path, not “software logic”.
  • Port-side parasitics (ESD/connector/cable) can distort waveform margins even when a bench setup looks clean.
  • Measurement method (probe/fixture/reference plane) must be treated as part of the system.
Card A · Line states & termination concept (electrical, not protocol steps)
USB2 signaling integrity depends on how line states are realized electrically: pull-up/pull-down behavior, effective termination, and stable thresholds at the measurement plane.
What to validate
  • Pull behavior: correct direction and strength, stable against noise and leakage (X).
  • Effective termination: no large impedance breaks at port-side devices (Y).
  • Reference plane: compare results only after defining TP (near PHY vs near connector) (Z).
Card B · Edge-rate vs EMI trade (faster is not always better)
Faster edges increase high-frequency energy and make discontinuities more visible. A well-controlled edge rate often yields a more robust system and cleaner EMI performance.
Practical checks
  • Ringing control: reduce overshoot and shorten decay time without collapsing eye margin (X).
  • Return continuity: avoid reference-plane splits under the pair; check via return paths (Y).
  • Port parasitics: confirm ESD/connector capacitance symmetry (Z).
Card C · Common bring-up mistakes (ground bounce / return / ESD C / fixtures)
Many USB2 “intermittent” issues trace back to physical effects that are easy to miss in a lab setup. The fastest path is to start with a physical-layer first check.
  • Fragile behavior after adding ESD: check parasitic C symmetry and placement order (connector → ESD → route).
  • Works on bench, fails in chassis: check shield/ground bonding and cable coupling paths (return integrity).
  • Scope “looks fine” but errors persist: check probe ground lead/fixture bandwidth and TP definition.
  • Random resets during activity: check ground bounce and local rail noise coupling into the PHY thresholds.
Pass criteria framing (placeholders)
  • Waveform margins remain within target mask/limits (X) at the defined TP.
  • No systematic ringing beyond the allowed envelope (Y) across cable/fixture variants.
  • Behavior remains stable across temperature and supply variations (Z) without hidden measurement artifacts.
Diagram · USB2 electrical states + test point (TP) map
USB2 states and test points — electrical view Line states (electrical) IDLE PU / PD DRIVE EDGE RECEIVE THRESH Test points (TP) and port parasitics USB2 PHY DRIVER/RX Connector PORT D+ D− TP (PHY) TP (PORT) ESD Cpar PU PD RETURN PATH: keep continuous reference under D+/D−
Practical use: compare TP(PORT) and TP(PHY) to separate port parasitics from PHY behavior, then validate edge/ringing margins against placeholders X/Y/Z.

H2-5 · USB 3.x PHY (SS) — Channel loss, EQ knobs, measurement view

What this chapter resolves
  • At SuperSpeed, the dominant chain is loss / reflections / crosstalk → eye closure → EQ + jitter margin.
  • Build a channel-budget view first, then map stability to Tx boost / Rx CTLE / DFE knobs.
  • Separate real margin from measurement artifacts by controlling reference plane + fixture.
Card A · Loss budget thinking (IL / RL / XT roles)
Treat the channel as a sum of segments. Each segment consumes margin through one dominant mechanism: IL (energy loss), RL (reflections), or XT (aggressor coupling). Avoid stacking “small problems” until the eye collapses.
How to frame the budget (no standards values)
  • Insertion loss (IL): sets received amplitude and eye height; drives how aggressive EQ must be (X).
  • Return loss (RL): sets reflection strength; increases deterministic jitter / ISI and narrows the eye (Y).
  • Crosstalk (XT): sets noise-floor lift; reduces SNR and creates bursty errors under activity (Z).
Fast checks (dominant segment search)
  • Change cable length/type: strong sensitivity implies IL-driven eye height collapse (X).
  • Touch only one discontinuity (connector/via cluster): strong improvement implies RL-driven reflections (Y).
  • Toggle nearby aggressors (lanes/power switching): correlation implies XT-driven noise (Z).
Card B · Equalization knobs (Tx boost / Rx CTLE / DFE)
Equalization trades one limitation for another. The goal is not maximum boost, but stable sampling margin across cables, temperature, and activity. Keep knobs at a conceptual level to avoid vendor-specific overlap.
Knobs and typical side-effects
  • Tx boost: compensates IL; too much can amplify noise and increase EMI sensitivity (X).
  • Rx CTLE: restores frequency balance; limited against strong discrete reflections (Y).
  • DFE: reduces post-cursor ISI; unstable convergence can create intermittent error bursts (Z).
Pass criteria framing (placeholders)
  • Eye margin remains above target (X) at the defined measurement plane.
  • Error rate stays stable within target (Y) over time window (Z) under worst-case activity.
  • No “works only with one cable/fixture” dependence after EQ tuning.
Card C · Measurement artifacts (plane / probe / fixture / de-embed)
A clean-looking eye is not a guarantee of stable receiver sampling. Control the measurement plane and fixture so the displayed eye represents the actual receive condition.
Fast disambiguation checklist
  • Plane mismatch: compare TP(NEAR) vs TP(FAR); improvement only at NEAR implies port/cable dominates (X).
  • Fixture RL: swap adapter/fixture; strong change implies the fixture is adding reflections (Y).
  • Probe/trigger bias: validate bandwidth, grounding, and acquisition settings; avoid “pretty eye” settings (Z).
  • De-embed risk: model mismatch can artificially open the eye; cross-check with raw captures.
Diagram · Channel budget schematic (segment tags: LOSS / REFLECT / XTALK)
Channel budget schematic — LOSS / REFLECT / XTALK per segment Channel = segments (each consumes margin) CONN PORT TRACE PCB VIA TRANS CABLE LOSS EP RX TP (NEAR) TP (FAR) REFLECT XTALK REFLECT LOSS MARGIN Budget method: identify dominant segment first, then tune EQ and validate at TP(FAR) Keep plane/fixture consistent to avoid “pretty eye, unstable link” traps

H2-6 · USB4 PHY (SSP) — Low-jitter refs & link-robust electrical planning

What this chapter plans and verifies
  • At higher speeds, refclk cleanliness + jitter templates often become the deciding margin.
  • Focus on planning + acceptance criteria, not tunneling/protocol strategy.
  • Define a clear boundary: boosting can fight loss, retiming protects sampling/jitter margin.
Card A · Refclk quality & distribution (ppm / phase noise / jitter placeholders)
Treat refclk as an input contract. What matters is the effective quality at the PHY pins after distribution (buffers, routing, coupling, and rail noise).
Acceptance framing
  • Frequency accuracy: ppm budget placeholder (X) across temperature and aging.
  • Jitter cleanliness: integrated jitter placeholder (Y) and spur control (Z).
  • Distribution integrity: rail/ground coupling does not convert noise into phase modulation.
Card B · Retiming vs boosting boundary (when PHY margin is not enough)
Boosting primarily compensates channel loss. Retiming protects sampling by breaking jitter accumulation and restoring a clean timing reference. Use a measurable decision rule rather than a subjective “works sometimes” heuristic.
Decision rule (placeholders)
  • If errors scale mainly with channel length/type, prioritize EQ/boosting (X).
  • If errors scale mainly with refclk / rail noise / temperature drift, sampling jitter margin is likely dominant (Y).
  • If both dominate, fix the largest budget consumer first, then re-validate templates at the far plane (Z).
Card C · Thermal drift & margin (how high-speed margin gets consumed)
High-speed systems fail at boundaries. Margin must be verified after thermal equilibrium and across ambient changes. Drift can silently shrink eye/jitter margin even when initial bring-up looks clean.
Verification framing
  • Measure margin at steady-state temperature (not only cold-start) (X).
  • Repeat tests over time to capture warm-up drift and long-run stability (Y).
  • Track pass criteria as a function of temperature/supply to avoid “works for 5 minutes” failures (Z).
Diagram · Refclk → PHY → channel margin chain (jitter-to-eye linkage)
Refclk to margin chain — REFCLK → DIST → PLL/SSC/CDR → JITTER → EYE → TEMPLATE Clock quality becomes sampling margin REFCLK SRC DIST BUF/ROUTE PHY PLL/SSC/CDR JITTER SAMPLE EYE MARGIN TEMPLATE JTOL / MASK PASS X/Y/Z NOISE SPUR Verify refclk quality at PHY pins and re-check margin after thermal equilibrium

H2-7 · SSC & Jitter Templates — How to think, measure, and debug

What this chapter standardizes
  • Explain what SSC is, why it exists (EMI), and what it costs (apparent jitter / margin consumption).
  • Unify template / window / bandwidth / reference plane so results are comparable across teams and tools.
  • Provide a debug split to separate refclk, channel, EQ, and power-noise influences.
Card A · SSC purpose & knobs (depth / rate concepts)
SSC intentionally spreads spectral energy to reduce narrowband peaks. It is not a “link optimizer” by itself. The trade is that frequency modulation shows up as additional components in time-domain jitter metrics, depending on the measurement window and bandwidth.
Concept knobs (no standard numbers)
  • DEPTH: how much energy is spread (peak reduction strength) (X).
  • RATE: how fast the modulation sweeps (where energy lands in frequency) (Y).
  • SPREAD mode: down-spread / center-spread impacts where the peak moves (Z).
Fast sanity checks
  • Compare EMI peak behavior with SSC OFF/ON at identical cable + plane conditions.
  • Ensure the same measurement window before comparing “jitter got worse/better.”
  • Record refclk source + distribution path so SSC impact is not mixed with clock pollution.
Card B · Jitter taxonomy (RJ / DJ / TJ; phase-noise → jitter)
“Jitter” is not a single number. It is a composition of components and a function of measurement bandwidth, time window, and reference plane. Without fixed conditions, results cannot be compared.
Engineering definitions
  • RJ: noise-like uncertainty; strongly depends on bandwidth and integration limits (X).
  • DJ: deterministic patterns (ISI/reflection/periodic spurs); often correlated with structure (Y).
  • TJ: total jitter under a defined probability and window; only meaningful with fixed settings (Z).
  • Phase noise → jitter: integrated jitter changes when integration bounds change (BW / offsets).
Common false calls
  • Different BW or filter settings produce different RJ/TJ numbers.
  • Different WINDOW lengths change observed SSC-related modulation components.
  • Different reference planes hide discontinuities; “good eye” at NEAR plane can fail at FAR plane.
Card C · Debug playbook (isolate refclk vs channel vs EQ vs power-noise)
Debug starts by isolating the dominant source. Avoid blind EQ tuning until the source class is confirmed. Use controlled perturbations and keep measurement conditions fixed.
Isolation sequence (fast, repeatable)
  1. Refclk split: swap clock source/distribution path; if jitter shifts strongly, clock dominates (X).
  2. Power split: correlate spurs with rail noise and load steps; if locked, rail coupling dominates (Y).
  3. Channel split: change cable/connector segment; strong sensitivity implies IL/RL/XT dominance (Z).
  4. EQ split: tune only after the above; verify stability at FAR plane and across temperature.
Pass criteria framing (placeholders)
  • Template compliance at the defined plane with fixed BW/WINDOW settings (X).
  • Jitter metrics stable within target band (Y) over observation time (Z).
  • No hidden dependence on trigger/filter/fixture changes.
Diagram · SSC + jitter measurement concept (frequency vs time, minimal labels)
SSC + jitter measurement concept — frequency vs time Same system, different settings → different jitter numbers FREQUENCY PEAK SPREAD SSC TIME WINDOW BW REFCLK SPUR RJ DJ TJ

H2-8 · Board & Package SI — Return path, impedance, via strategy, symmetry

What this chapter makes executable
  • Prioritize return-path continuity over superficial length-match focus.
  • Control impedance transitions at vias, pads, and connectors to reduce reflections.
  • Reduce crosstalk through spacing, layer stack, and stable reference planes.
Card A · Routing rules that matter (return path > length-match)
The biggest stability losses typically come from broken return paths and asymmetry, not small length mismatch. Keep the electromagnetic environment symmetric and the reference plane continuous.
Do-first checklist
  • Return path continuity: avoid reference-plane gaps/cuts under the pair (X).
  • Symmetry: keep both lines seeing the same planes/clearances and transitions (Y).
  • Impedance discipline: avoid sudden width/spacing changes; keep transitions consistent (Z).
Card B · Via / connector discontinuities (reduce and verify)
Discontinuities create reflections that consume eye width and increase deterministic jitter. Reduce them structurally, then verify by locating reflection points rather than relying only on a final eye diagram.
Reduce
  • Minimize via count and keep transitions compact; avoid long stubs where possible (X).
  • Control pad/antipad geometry and keep transitions symmetric between P and N (Y).
  • Keep connector launches consistent; avoid “one-off” escape geometries (Z).
Verify
  • Use impedance/time-location tools (e.g., TDR-like views) to find dominant reflection points (X).
  • Compare before/after changes at the same reference plane and fixture conditions (Y).
  • Confirm improvements translate to far-plane margin rather than only near-plane cosmetics (Z).
Card C · Crosstalk control (spacing / stack-up / reference planes)
Crosstalk is a geometry and field-coupling problem. Prevention through layout and stack-up is far more effective than trying to recover margin after the fact.
Layout actions
  • Keep long parallelism short; separate from other high-swing aggressors (X).
  • Prefer stable reference planes; avoid “floating” segments without a clear return path (Y).
  • Use stack-up choices that keep coupling controlled and symmetric around the differential pair (Z).
Diagram · Return path continuity (GOOD vs BAD, gap forces detour and increases CM)
Return path continuity — GOOD vs BAD GOOD BAD DIFF REFERENCE PLANE RETURN Z0 SYM DIFF GAP RETURN CM REFERENCE PLANE

H2-9 · Power, Noise, and Calibration — Why “clean rails” show up as “link issues”

What this chapter clarifies
  • Power/ground/reference noise couples into PHY timing and thresholds, then appears as jitter/eye degradation and link instability.
  • Coupling paths are made explicit so measurement and debugging can target the correct block (PLL / Tx / Rx / refclk).
  • Calibration and drift (temperature / lot / aging) are treated as margin consumers with repeatable acceptance framing.
Card A · Noise coupling paths (rail → PLL → Tx/Rx)
“Clean rails” is not a DC statement. The dominant risk is frequency-specific ripple, transient ground bounce, and reference contamination that modulates phase and sampling decisions.
Coupling classes (block view)
  • Rail ripple → PLL/VCO: phase modulation increases jitter and eats timing margin (X).
  • Rail ripple → Tx driver: swing/edge variation reduces eye height and worsens crossings (Y).
  • Ground bounce → Rx threshold: decision point drifts; burst errors can appear “random” (Z).
  • Refclk contamination: spurs and modulation leak into template/accounting (BW/WINDOW dependent).
Fast correlation checks
  • Does BER/link flap align with load steps or power-state transitions?
  • Do spurs in jitter/phase-noise align with a rail switching frequency or its harmonics?
  • Does a clock-source swap produce a large shift under identical channel conditions?
Card B · Decoupling strategy for PHY blocks (principles + verification)
Decoupling effectiveness is dominated by loop area and return-path quality, not only capacitor value. The goal is to confine noise currents locally and prevent cross-injection between PLL/analog/Rx/Tx domains.
Principles (block-level)
  • Partition rails: keep PLL/analog rails isolated from noisy digital aggressors (X).
  • Minimize loop: cap–via–pin paths should be short and symmetric (Y).
  • Cover frequency bands: ensure impedance is controlled across LF/MF/HF ranges (Z).
Verification (repeatable)
  • Load-step test: observe rail droop/ringing at the PHY neighborhood plane (X).
  • Spur tracing: map spurs to a switching source; validate removal reduces jitter/BER (Y).
  • Placement A/B: moving a cap can prove loop dominance more than changing value (Z).
Card C · Calibration / trim strategy (temperature / lot / aging)
Calibration offsets drift with temperature and time. Link robustness depends on when calibration runs, what it trims, and whether post-calibration margin is verified at the correct reference plane.
What to treat as margin consumers
  • Termination & impedance trims: drift changes reflections and eye opening (X).
  • Offset / gain trims: decision thresholds shift, raising burst error probability (Y).
  • EQ / DFE convergence seeds: wrong initial state reduces robustness across corners (Z).
Pass criteria framing (placeholders)
  • Across temperature window (X), jitter/BER remains within targets (Y) for observation time (Z).
  • No sensitivity to rail switching states beyond the defined limits (X) under fixed BW/WINDOW settings.
  • Post-calibration retest confirms far-plane margin rather than near-plane cosmetics.
Diagram · Noise injection paths (PMIC/rail ripple → PLL → jitter → eye → BER/link)
Noise injection paths — from rails to link instability PMIC RAIL PLL VCO JITTER EYE BER LINK SPUR BOUNCE COUPLING RAIL RIPPLE → PHASE MOD → JITTER THRESHOLD SHIFT → BURST ERR MARGIN LOSS EYE CLOSE → LINK FLAP VERIFY LOOP LOAD STEP TEMP SWEEP PLANE FIXED PASS

H2-10 · EMC/ESD at the Port — Low-C symmetry, placement, and failure modes

What this chapter enforces
  • Port protection must preserve differential integrity: low capacitance and symmetry are hard requirements.
  • Placement order defines both ESD effectiveness and SI impact: connector-side devices form the first boundary.
  • Post-ESD “passes once, fails later” is treated as a degradation class with a focused checklist.
Card A · Low-C & symmetry rule (why small pF differences matter)
At high speed, a protection array behaves like a shunt load. Small capacitance changes shift impedance and the high-frequency energy balance. Asymmetry between P/N converts differential energy into common-mode, worsening EMI and consuming eye margin.
Fast sanity checks
  • Cdiff match: keep effective P/N loading balanced within target (X).
  • Symmetric geometry: pad/escape and return path should mirror for P and N (Y).
  • Common-mode awareness: any mismatch can raise CM and break margin (Z).
Card B · Placement order (connector → TVS → (CMC) → AC caps → PHY)
Place the ESD clamp closest to the connector to minimize discharge loop area. Treat common-mode chokes as a conditional tool: they can help EMI but also introduce discontinuities and asymmetry if used incorrectly.
Rule set (topology discipline)
  • CONN → TVS: shortest ESD path to chassis/ground, minimal loop (X).
  • (CMC) optional: validate with A/B measurement; avoid creating RL steps (Y).
  • AC/series elements: keep pairing and symmetry; avoid uneven loading (Z).
  • To PHY: keep the rest of the channel clean and reference-plane continuous.
Card C · Post-ESD degradation checklist (“passes once, becomes fragile later”)
A system can pass an ESD event yet degrade afterward. The failure mode can be parameter drift in the protection path, connector micro-damage, or return-path looseness that raises common-mode and consumes margin over time.
Degradation triage
  • Before/after compare: IL/RL or far-plane eye/template under identical fixtures (X).
  • Leakage / C drift: re-check port arrays for leakage and effective capacitance shift (Y).
  • Grounding integrity: confirm 360° shield bond and chassis return continuity (Z).
  • CMC suspicion: bypass or relocate to see if it is a sensitivity amplifier.
Diagram · Connector-side protection topology (CONN / TVS / (CMC) / AC / PHY, low-C symmetry emphasis)
Connector-side protection topology — preserve low-C symmetry CONN TVS CMC AC PHY LOW-C SYM EMI RISK ESD PATH CHASSIS ORDER CONN → TVS → (CMC) → AC → PHY Keep P/N loading symmetric Validate CMC by A/B margin

H2-11 · Engineering Checklist (Design → Bring-up → Production)

Convert PHY risks into gates with auditable artifacts. Each gate uses the same contract: Input → Action → Output → Pass criteria (threshold placeholders X/Y/Z).

Budget-first Measurement contract Production reproducibility
Design Gate · prevent non-reversible PHY failures
DG-1 · Channel budget pack (IL/RL/XT map)
Input: link topology (connector → protection → vias → traces → cable → far-end).
Action: tag each segment with dominant risk (LOSS / REFLECT / XT) and lock reference planes.
Output: one-page “budget map” with segment labels + measurement reference plane definition.
Pass criteria: margin ≥ X; critical discontinuities ≤ Y.
DG-2 · Return-path integrity (continuous reference)
Input: stackup + plane splits + via transitions along SS/SSP pairs.
Action: verify continuous reference under the diff pair; ensure via transition has a defined return path.
Output: annotated layout screenshots (OK/NG) for each critical transition.
Pass criteria: no plane gaps under critical segments; symmetry deviation ≤ X.
DG-3 · Port protection order & symmetry (connector-side)
Input: connector/ESD/CMC/AC-cap placement and routing snapshot.
Action: enforce “low-C + symmetry + shortest ESD path”; lock the order (CONN → TVS → (CMC) → PHY).
Output: port-area layout with distance markers and pair-to-pair symmetry checks.
Pass criteria: TVS distance ≤ X mm; pair mismatch (ΔC/Δlen) ≤ Y.
DG-4 · Refclk readiness (noise domain separation)
Input: refclk source, distribution, and supply rails for PLL/analog blocks.
Action: reserve refclk probe points; separate analog/digital noise domains where applicable.
Output: refclk tree diagram + probe-point plan + measurement bandwidth/window definition.
Pass criteria: agreed jitter/phase-noise contract; measurable at the defined plane.
DG-5 · Test hooks (avoid “unmeasurable” systems)
Input: bring-up plan (PRBS/loopback/eye/jitter) and fixture assumptions.
Action: add access points or headers where needed; define the de-embed method upfront.
Output: measurement plan (plane + fixture + settings) stored with board revision.
Pass criteria: 100% of required signals/planes are accessible and repeatable.
Bring-up Gate · make results reproducible and explainable
BG-1 · Baseline script (version-locked)
Input: board rev, FW, cable, temperature, power profile.
Action: run the same training/stability sequence; log timestamps and counters.
Output: baseline log bundle (config + results + screenshots).
Pass criteria: success rate ≥ X% over N runs; no unexplained resets.
BG-2 · Isolation ladder (internal → external → full)
Input: available loopback points and PRBS modes.
Action: verify PHY-internal stability first, then extend step-by-step to the connector/cable.
Output: BER/error logs per step with identical time windows.
Pass criteria: internal BER ≤ X; full-path BER ≤ Y; error signature matches topology.
BG-3 · Eye/Jitter measurement contract
Input: instrument BW, time window, trigger, reference plane, fixture/de-embed method.
Action: freeze settings; capture “settings screenshot + result screenshot” as a pair.
Output: a reproducible measurement packet for comparisons across boards/labs.
Pass criteria: template meets X; margin trend stable across runs.
BG-4 · Power-noise correlation (rail → jitter → errors)
Input: PLL/analog rails probe points and load-step stimulus plan.
Action: align rail ripple and error timestamps; test at worst-case load edges.
Output: correlation plots/screenshots with the same time base.
Pass criteria: correlation coefficient ≤ X; mitigation improves BER by ≥ Y.
BG-5 · Thermal corner sweep
Input: cold/hot targets and soak time definition.
Action: re-run baseline + isolation ladder at each corner.
Output: corner comparison table (eye/jitter/BER/lock time).
Pass criteria: worst corner still meets templates; drift ≤ X.
Production Gate · keep fixtures stable and failures classifiable
PG-1 · Fixture equivalence (A vs B)
Input: fixture versions, cable batches, calibration records.
Action: cross-test the same golden unit across fixtures and shifts.
Output: equivalence report with deltas and limits.
Pass criteria: fixture-to-fixture delta ≤ X; drift per week ≤ Y.
PG-2 · Sampling matrix (stress coverage)
Input: sampling rate, corner conditions (temperature / cable / plug cycles).
Action: define minimum stress coverage; tighten sampling on excursions.
Output: sampling logs + exception triggers.
Pass criteria: coverage ≥ X; excursion handling executed within Y hours.
PG-3 · Golden unit and limits
Input: golden board definition and limit tables.
Action: daily/shift checks; freeze limits per board rev.
Output: limit verification logs and trend chart snapshots.
Pass criteria: trend within X; out-of-family triggers stop-and-review.
PG-4 · RMA taxonomy (map back to gates)
Input: symptoms, reproduction conditions, port history (ESD/plug cycles).
Action: classify by domain: REFCLK / CHANNEL / PORT / POWER / CAL / DAMAGE.
Output: RMA classification form and evidence links (logs/waveforms).
Pass criteria: classification coverage ≥ X%; gate-level corrective action identified.
Diagram · Gate flow (Design → Bring-up → Production)
Three gates, each with auditable blocks. Use this as a review checklist and an RMA backtrace map.
Gate flow diagram (Design → Bring-up → Production) Input → Action → Output → Pass Thresholds: X / Y / Z DESIGN GATE BRING-UP GATE PRODUCTION GATE BUDGET (IL/RL/XT) RETURN PATH PORT ORDER / SYM REFCLK READY TEST HOOKS BASELINE SCRIPT ISOLATION LADDER EYE / JITTER CONTRACT POWER CORRELATION THERMAL SWEEP FIXTURE EQUIVALENCE SAMPLING MATRIX GOLDEN + LIMITS RMA TAXONOMY TRACEABILITY Store artifacts per gate (logs, settings, screenshots) to enable fast debug and RMA backtrace.

H2-12 · Applications & IC Selection (with part numbers)

Selection stays at the PHY/electrical boundary: rate family, refclk needs, channel conditions, test hooks, and connector-side robustness. Representative material numbers are listed for fast BOM bootstrap.

Note: “Retimer/Redriver/Switch/MUX” details belong to their dedicated pages; here they appear only as boundary markers and reference parts when PHY margin is not enough.
Use-case buckets (PHY viewpoint)
Bucket A · External USB2 PHY for SoC/MCU (ULPI)
When: SoC lacks HS PHY or needs ULPI flexibility/OTG features.
Dominant risks: refclk integrity, ULPI timing, VBUS/ESD coupling.
Must-have: ULPI compliance, stable refclk/PLL behavior, clear bring-up hooks.
Bucket B · External USB3 PHY (PIPE) between controller and connector
When: controller/SoC exposes PIPE and needs a discrete SS PHY front-end.
Dominant risks: channel loss/discontinuities, equalization limits, measurement plane mismatch.
Must-have: PIPE compatibility, adaptive EQ, repeatable eye/jitter measurement plan.
Bucket C · Dock/Hub upstream (high port density)
When: compact boards with dense SS routing and shared clocks/rails.
Dominant risks: crosstalk, thermal drift, rail noise showing up as jitter/BER.
Must-have: robust refclk distribution and production fixture stability.
Bucket D · Long reach / harsh EMI (PHY margin not enough)
When: long traces/cables or degraded environments reduce eye margin.
Dominant risks: loss + reflection + noise coupling; post-ESD fragility.
Must-have: explicit boundary check: boost-only vs re-timing requirement.
Selection matrix (dimensions → checks → pass)
Rate family: USB2 (HS) / USB3 (SS) / higher-speed planning (SSP-class).
Quick check: identify the physical channel(s) and dominant risks (LOSS/REFLECT/XT).
Pass criteria: channel plan supports required family with margin ≥ X.
Refclk needs: define source, distribution, and measurement contract (BW/window/plane).
Quick check: reserve probe points; verify noise-domain separation for PLL rails.
Pass criteria: jitter/phase-noise contract met at the defined plane.
EQ/training support: ensure adaptive EQ visibility (settings/logs) and repeatable test hooks.
Quick check: isolation ladder is feasible (internal → external → full).
Pass criteria: stable BER/eye/jitter results repeat across labs/fixtures (≤ X delta).
Port robustness: low-C + symmetry; correct placement order; post-ESD degradation checks.
Quick check: TVS/CMC order and pair symmetry (ΔC/Δlen).
Pass criteria: after ESD/plug cycles, margin does not collapse beyond X%.
Reference BOM bundles (material numbers)
These are bootstrap examples for fast schematic start. Final selection must pass H2-11 gates.
Bundle 1 · USB2 ULPI PHY (external HS transceiver)
  • ULPI PHY (TI): TUSB1210 (USB 2.0 ULPI PHY transceiver)
  • ULPI PHY (Microchip): USB3300 (USB 2.0 ULPI PHY with OTG support)
  • ULPI PHY (Microchip): USB3320 (multi-frequency USB 2.0 ULPI transceiver)
  • ULPI PHY (NXP, legacy): ISP1504 (USB 2.0 OTG ULPI transceiver; legacy option)
Bring-up hook: lock ULPI clock/PLL behavior first (internal), then extend to connector with fixed fixtures.
Bundle 2 · USB3 discrete PHY (PIPE front-end)
  • USB 3.0 PHY (TI): TUSB1310 (USB 3.0 PHY transceiver with PIPE/ULPI interfaces)
  • USB 3.0 PHY (TI): TUSB1310A (not recommended for new designs; legacy reference)
Caution: confirm lifecycle status and controller PIPE compatibility before committing.
Bundle 3 · Connector-side ESD/TVS (low-C, matched pairs)
  • Quad USB3 ESD (TI): TPD4EUSB30 (quad low-capacitance ESD protection for USB 3.0)
  • Dual USB3 ESD (TI): TPD2EUSB30A (low-capacitance protection for high-speed differential I/O)
  • 4-line TVS array (Semtech): RCLAMP0524P (ultra-low capacitance TVS array family)
Placement rule: keep protection close to connector; enforce pair symmetry (ΔC/Δlen) and shortest ESD return path.
Bundle 4 · Low-jitter reference clock (refclk)
  • Differential oscillator (SiTime): SiT9120 (LVDS/LVPECL differential oscillator family; low RMS phase jitter)
  • Programmable clock generator (Renesas): 5P49V5901 (VersaClock 5 programmable clock generator)
Validation: define jitter/phase-noise integration band + measurement plane, then store settings as part of the bring-up contract.
Bundle 5 · Boundary marker: re-timing reference part (PHY margin insufficient)
  • Multi-rate retimer (TI): DS280DF810 (8-channel multi-rate retimer; reference when channel loss exceeds boost capability)
Use here: only to decide the boundary (boost-only vs re-timing). Full retimer selection belongs to the dedicated retimer page.
Diagram · Selection decision tree (PHY viewpoint)
Short-path decisions: rate family → channel condition → re-timing boundary → refclk → package/power → test hooks.
Selection decision tree (USB PHY) RATE FAMILY USB2 (HS) / USB3 (SS) / SSP-class CHANNEL LOSS / REFLECT / XT tags RETIME? Boost-only vs Re-timing boundary REFCLK Source / distribution / meas. contract OUTPUT PHY class + must-have hooks PACKAGE / POWER thermal density + routing TEST HOOKS PRBS / loopback / eye/jitter Decision tree output must map to H2-11 gates (artifacts + pass criteria).

Request a Quote

Accepted Formats

pdf, csv, xls, xlsx, zip

Attachment

Drag & drop files here or use the button below.

H2-13 · FAQs (Field Debug Long-Tail)

Each answer follows the same data-oriented structure: Likely cause / Quick check / Fix / Pass criteria. Pass criteria uses numeric placeholders X/Y/Z with explicit metric + window + repeats.

Pass criteria template (data fields)
  • Metric: BER / error bursts / jitter margin / delta across fixtures
  • Window: Y seconds/minutes, same reference plane + same fixture
  • Repeats: Z runs (same conditions), report worst-case
  • Thresholds: X = limit, plus any secondary constraint (e.g., delta ≤ X)
1) Eye looks open, but BER is bad — what’s the first measurement sanity check?
Likely cause: Reference plane / de-embed mismatch, or inconsistent instrument settings.
Quick check: Freeze BW/window/trigger + confirm plane; capture “settings + result” as a paired record.
Fix: Standardize a measurement contract and retest using the same fixture and plane definition.
Pass criteria: BER ≤ X over Y seconds, repeated Z runs; lab/fixture delta ≤ X% using the same plane.
2) Jitter template fails, but phase-noise plot looks “fine” — what definition mismatch is most common?
Likely cause: Different integration band / SSC state / RJ-DJ-TJ accounting mismatch.
Quick check: Verify integration limits and SSC on/off; measure the same clock node at the same plane.
Fix: Align jitter taxonomy + template window; rerun with locked settings and saved screenshots.
Pass criteria: Template margin ≥ X (units per contract) over Y window; repeatability within ±X across Z runs.
3) Enabling SSC makes the link flaky — what should be isolated first?
Likely cause: Refclk distribution sensitivity or excessive SSC depth/rate consuming PLL/CDR margin.
Quick check: A/B test SSC off vs on under identical topology; compare lock time + BER + error bursts.
Fix: Clean up refclk path/rails or tune SSC parameters to match the agreed template.
Pass criteria: With SSC enabled, error bursts ≤ X per hour for Y hours; jitter margin ≥ X across Z repeats.
4) Works on the bench, fails in the final chassis — what’s the first PHY-level topology check?
Likely cause: Added discontinuities (connector/cable/shield bond), return-path breaks, extra loss/XT.
Quick check: Compare segment-by-segment budget map bench vs chassis; validate reference plane consistency.
Fix: Remove/relocate the worst discontinuity (via/connector/plane gap) or restore continuous return.
Pass criteria: Worst-case margin improves by ≥ X; BER ≤ X over Y minutes, repeated Z runs in chassis.
5) Short cable is stable, long cable is unstable — boost-only or re-timing boundary?
Likely cause: Channel loss/reflections exceed EQ capability; remaining eye margin collapses at length.
Quick check: Build a LOSS/REFLECT/XT budget and correlate failures with the worst segment.
Fix: Tune Tx/Rx EQ within allowed range; if still failing, move to re-timing at the boundary.
Pass criteria: At max length, BER ≤ X over Y minutes; tuning stays within limits; repeat Z runs with consistent margin ≥ X.
6) Only one Type-C orientation is unstable — what PHY-side root cause is most likely?
Likely cause: Flip path asymmetry (MUX/route/ESD) creating Δloss/ΔC or return-path differences.
Quick check: Compare both orientations at the same plane; record eye/jitter delta with fixed settings.
Fix: Enforce symmetry in routing and protection placement across both flip paths.
Pass criteria: Orientation A vs B delta ≤ X%; both meet BER ≤ X over Y minutes, repeated Z runs.
7) CRC spikes when other loads switch — SI issue or power-noise coupling?
Likely cause: Rail ripple/ground bounce couples into PLL/CDR and appears as jitter/error bursts.
Quick check: Time-align rail ripple and error counters; run a controlled load-step stimulus.
Fix: Strengthen PHY rail decoupling/isolation and confirm noise-domain separation.
Pass criteria: Burst rate reduces by ≥ X%; rail ripple at node ≤ X (same probe method), across Z repeats.
8) Runs for 5–10 minutes then drops — thermal drift or calibration drift?
Likely cause: Thermal drift reduces CDR/PLL margin, or trims drift with temperature/aging.
Quick check: Repeat baseline at cold/room/hot; compare lock time, BER, and eye/jitter trend.
Fix: Improve thermal path (copper/airflow) and validate calibration stability across corners.
Pass criteria: Worst-corner BER ≤ X over Y minutes; drift of key metric ≤ X across Z corners.
9) USB2 HS works, but emissions get worse after “faster edges” — what knob to touch first?
Likely cause: Edge-rate too aggressive increases EMI without improving functional margin.
Quick check: Compare rise/fall trend vs stability; confirm return-path quality near connector.
Fix: Use slew control / damping to balance EMI and margin (minimal change first).
Pass criteria: EMI improves by ≥ X dB while dropouts ≤ X per Y hours, across Z runs.
10) Adding a common-mode choke improved EMI but reduced margin — what should be verified first?
Likely cause: Added discontinuity or imbalance changes differential IL/RL and consumes eye margin.
Quick check: Compare RL/IL around the CMC location; check symmetry and placement order.
Fix: Select a more suitable CMC or adjust placement/routing to minimize discontinuity.
Pass criteria: RL/IL returns within X of baseline; BER ≤ X over Y minutes, repeated Z runs.
11) ESD test passes once, but later the link becomes “more fragile” — fastest degradation check?
Likely cause: TVS/connector damage or parameter drift (capacitance/leakage) reduces margin.
Quick check: Pre/post compare with same fixture and plane; look for TDR/eye signature shift.
Fix: Replace suspect port components and tighten ESD return path + placement symmetry.
Pass criteria: Post-ESD margin drop ≤ X%; no new bursts over Y minutes at the same stress, repeated Z times.
12) Production yield drifts over time — what is the first PHY-related check?
Likely cause: Fixture/cable drift or measurement contract drift, not true silicon variability.
Quick check: Run a golden unit across fixtures/shifts; compare deltas with the same settings packet.
Fix: Recalibrate fixtures, lock the contract, and enforce equivalence checks on a schedule.
Pass criteria: Fixture delta ≤ X; yield returns within X% of baseline for Y lots; verified by Z golden runs.
icnavigator

ICNavigator helps engineers find verified ICs, alternatives, and fast quotes.

Explore
Categories
  • Power Management
  • MCU
  • Automotive ICs
  • Sensors
  • Interface & Transceivers
  • Analog Front-End
Get in Touch
  • Email: hello@icnavigator.com
  • WeChat/WhatsApp: +86-xxxx

© 2025 ICNavigator. All rights reserved.