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Battery Protector / Pack Switch — Safety Matrix, IC Selection & Validation

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This page focuses on pack-level protection and switching for Li-ion/LFP battery packs: OVP/UVP/OTP, OCP/short, reverse polarity, backfeed prevention, and shipping mode with low standby current. It excludes Charger PMICs, cell-monitoring BMS/AFE, and board-level eFuse/Hot-Swap (linked as sibling pages).

Low Iq dV/dt & Precharge Dual-FET CHG/DSG AEC-Q100 Options
Battery Protector / Pack Switch overview Battery pack cells feeding a pack-switch block (CHG/DSG) towards a system rail, with a safety matrix card. Safety OVPUVPOTP OCPShortReverse Backfeed Battery Pack Pack Switch CHG DSG System Rail (SYS)
Overview: pack-level protections and switching path to the system rail.

Scope Pack-level protections (OV/UV/OC/short/OTP), reverse & backfeed protection, shipping mode, dV/dt & precharge. Out of scope Charger PMICs, cell AFE/BMS, board-level Hot-Swap/eFuse.

Use Cases & Safety Goals

Design guardrails for real situations: Shipping mode, Pack wake-up, Reverse polarity, and Backfeed prevention.

Shipping Mode (Ultra-low Standby)

Goal: keep pack quiescent current in the µA range while outputs are safely off. Allow controlled wake-up via charger plug-in, system signal, or momentary push-button.

Shipping mode with wake triggers CHG/DSG off, low Iq; wake via charger, system, or push-button. Battery Pack Pack Switch System Push-button Charger plug-in
Keep outputs off; define clear wake triggers and debounce.
  • Standby Iq budget <= target µA; leakage audit across pack switch, sense, LEDs.
  • Wake policy: single/dual trigger, debounce time, safe precharge before enable.

Pack Wake-up (Controlled Ramp)

Avoid inrush spikes and brown-out resets when leaving shipping mode. Use dV/dt control and a precharge path so the system rail rises smoothly before switching fully on.

Precharge and soft-start A small precharge path charges system capacitance; dV/dt controls the main turn-on. Pack Switch System Vsys ramp
Precharge first, then soft-start the main path with defined dV/dt.
  • Size precharge (R/C) for worst-case cable inductance and Csys.
  • Scope peak inrush and Vgs/Vds; verify no brown-out on downstream MCU.

Reverse Polarity (User Mis-plug)

Protect against accidental reversal at the pack or system connector. Use an ideal-diode path or back-to-back FETs with fast detection and a safe turn-off policy.

Reverse polarity protection Ideal-diode or back-to-back FETs isolate reverse connections. Back-to-Back FETs System Reverse plug → isolate
Detect and isolate fast; choose ideal-diode or back-to-back FETs per losses and cost.
  • Define detection threshold & debounce; avoid false trips during hot-plug transients.
  • Thermal budget vs. conduction loss: RDS(on), copper spread, θJA.

Backfeed Prevention (Ports & Multi-sources)

Stop unintended reverse current into the pack or into external ports (e.g., USB-C). Coordinate the ideal-diode and pack switch so only the intended path conducts.

Backfeed prevention Ideal-diode path enforces direction; monitor port states to block reverse flow. Ideal-Diode Pack Switch
Enforce one-way power flow; verify reverse-current spec across all ports.
  • Set reverse current limit; validate under low-V pack and high-V external sources.
  • Define fault policy: cutoff vs. retry vs. latch; log events for diagnostics.

Protections Matrix

Pack-level protections mapped to a practical flow: Trigger → Debounce → Action → Recovery. Focus on OVP/UVP/OTP, OCP/Short, Reverse Polarity, and Backfeed.

Battery protection matrix Cards for OVP, UVP, OCP, Short, OTP, Reverse, and Backfeed with action flow: retry, latch, or off. OVP Vpack > V_OVP Latch / Off UVP Vpack < V_UVP Delay → Off OCP I > I_OCP (avg) Limit → Off Short µs detect Fast Off · Latch OTP Tj / PCB Over Thermal Retry Reverse Polarity check Isolate Backfeed Reverse I Ideal-Diode + Off Action Flow Debounce: t_min / Rc Action: Off / Limit / Latch Recovery: Hys / Delay / Event
Map each protection to detection, debounce, action, and recovery. Validate under worst-case loads and hot-plug.

OVP — Over-Voltage

Trigger: Vpack > VOVP(th) (include temp & tolerance). Action: Off or Latch.

  • Sense at battery side; define hysteresis & min on/off time.
  • Scope charger overshoot; avoid false trip on wake.
LatchHysteresis

UVP — Under-Voltage

Trigger: Vpack < VUVP(th); allow rebound. Action: Delayed Off.

  • Add debounce; choose wake via charger or system event.
  • Log event for cycle-life analysis.
DelayWake-by-Chg

OCP — Over-Current

Trigger: I > IOCP (avg/filtered). Action: Limit → Off.

  • Kelvin sense; pick Rsense for signal-to-noise & loss.
  • Thermal drift & tolerance stack-up.
KelvinLimit

Short-Circuit

Trigger: µs-scale detection (Vds/Vsys drop). Action: Fast Off, often Latch.

  • Comparator RC & hysteresis; gate discharge path.
  • Validate with worst-case cable inductance.
µs CutoffLatch

OTP — Over-Temperature

Trigger: Tj/PCB over limit (on-die + NTC). Action: Derate → Off → Thermal Retry.

  • Spread copper; design for θJA/θJC and airflow.
  • Place sensor near hotspot (FET/driver).
NTCRetry

Reverse Polarity

Detect mis-plug at pack/system connector. Action: Isolate via back-to-back FETs or ideal-diode.

  • Fast decision; avoid damage to measurement front-end.
  • Check conduction loss vs. protection strength.
IsolateIdeal-Diode

Backfeed

Multi-sources/ports may reverse-feed the pack. Action: Enforce direction + cutoff.

  • Set Irev limit and verify with high-V external sources.
  • Define cutoff vs. retry vs. latch policy.
Reverse IPolicy

Pack Switch Topologies

Choose among high-side / low-side, single / back-to-back FETs, and ideal-diode assisted paths. Compare losses, measurement, reverse ability, and startup behavior.

Pack switch topologies Low/High-side single FET, back-to-back FETs, and high-side with ideal-diode path. Low-Side Single + Simple drive – Ground reference shifts Low-Side B2B + Blocks reverse – Ground still an issue High-Side Single + Easy measurement – Needs bootstrap High-Side B2B + Blocks reverse & stable GND – Cost/drive complexity High-Side + Ideal-Diode + One-way, great for ports – Coordinate switchover Startup & Thermal Notes • Precharge R/C from C_sys, ramp target, and time. • dV/dt to limit inrush; verify MCU brownout. • SOA not linearly additive in parallel FETs. • Symmetric gate/trace for current sharing. • I²R + θ_JA + copper spread + airflow.
Compare losses, measurement reference, reverse ability, and startup needs (precharge & dV/dt).

Low-Side Single FET

Pros Simple gate drive, low loss. Cons Ground reference shifts; reverse/backfeed needs extra path.

  • Check sense accuracy vs. ground lift.
  • EMI: minimize gate loop; keep return tight.

Low-Side Back-to-Back FETs

Pros Blocks reverse cleanly. Cons Higher loss; ground still floating issues.

  • Size Rds(on) ×2; thermal sharing matters.
  • Define reverse-current detection & policy.

High-Side Single FET

Pros Stable measurement reference. Cons Needs bootstrap/charge pump.

  • Confirm Vgs margin across pack voltage.
  • Consider ideal-diode assist for ports.

High-Side Back-to-Back FETs

Pros Reverse block + stable ground. Cons Cost & drive complexity ↑.

  • Symmetric routing; matched gate resistors.
  • Verify Vds, Vgs under surge events.

High-Side + Ideal-Diode Path

Pros One-way flow for ports/multi-sources. Cons Manage switchover chatter.

  • Coordinate thresholds to avoid oscillation.
  • Thermal: diode drop vs. FET conduction.

Thresholds & Sizing

Set OVP/UVP and OCP/Short thresholds, choose FETs for VDSS/RDS(on)/Qg, verify SOA/thermal, and control startup via dV/dt & precharge.

Sizing quick map Left: voltage thresholds & tolerance; center: Rsense & OCP/SC; right: FET/Vdss/Rds & SOA; bottom: precharge and dV/dt. Voltage Thresholds OVP = Vmax × (1 + margin) UVP = Vmin + Δrebound Hysteresis H ≈ k · σnoise Stack-up: divider error, offset, tempco Rsense & OCP / Short Rs = Vfs / IOCP ; P = Irms2·Rs fc = 1/(2π RfCf) (noise vs. response) Short: µs comparator + fast gate discharge FET & SOA VDSS ≥ Vpack,max + V̂surge Pcond = Irms2·RDS(on)(T) Qg vs. gate current → rise time/EMI/heat Parallel not linear; match gates & routing Precharge & dV/dt Rpre ≈ (Vin − Vpre) / Ilimit ; t ≈ −RpreCsys·ln(1 − Vpre/Vin) dV/dt ≤ Iinrush,max / Csys Scope: Iinrush, VGS, VDS, Vsys (worst cable inductance) Vsys ramp
Quick rules and checks to size thresholds, Rsense, FETs, thermal/SOA, and startup behavior.

Voltage Thresholds

Choose OVP/UVP with margin/hysteresis; include divider tolerance, offset, and tempco.

  • OVP near charge ceiling; UVP above rebound level.
  • Set min on/off time; place RC close to comparator.

Current Limits & Short

Size Rsense for SNR and power; filter bandwidth vs. response; µs short cut-off.

  • Kelvin routing; derate at temperature.
  • Gate discharge path must be low impedance.

FET & Thermal

VDSS surge margin; RDS(on)(T) for loss; Qg vs. gate current for EMI/heat.

  • Parallel with matched gates; symmetric copper.
  • SOA vs. surge width; airflow & θJA.

System Signals & State Machine

Define PG/FLT/EN/WAKE and a predictable path: Shipping → Wake → Normal → Fault.

Battery pack state machine Shipping, Wake (precharge & soft-start), Normal (PG high), Fault with recovery; PG/FLT/EN timing bars. Shipping Wake Precharge + dV/dt Normal Protections active Fault OV/UV/SC/OTP/Reverse/Backfeed Timing EN/WAKE PG FLT Recovery policy: Off / Auto-Retry / Latch PG debounce 5–20 ms · FLT clear 50–200 ms · Button debounce 30–100 ms
Define signals and predictable transitions. Record PG/FLT/EN/Vsys and verify debounce windows.

Signals: PG / FLT / EN / WAKE

Open-drain outputs with pull-ups matched to MCU IO levels. Debounce and ESD at connectors.

  • PG: asserts after Vsys stable for tPG; use as downstream enable.
  • FLT: any protection → low; clear by timeout/reset/cool-down.
  • EN/WAKE: charger-in / system / push-button; 30–100 ms debounce.

States & Transitions

Ship → Wake → Normal; any protection can force Fault; recovery per policy.

  • Ship: µA-level Iq; CHG/DSG off.
  • Wake: precharge Csys + dV/dt soft-start; raise PG after stable.
  • Normal: matrix active; log events.
  • Fault: Off/Retry/Latch; clearly defined exit.

EMC: keep signal returns short; isolate from gate-drive loop; add TVS where needed.

Layout & Safety

PCB guidelines for Kelvin sensing, minimal gate loop, power path symmetry, and creepage/clearance around the pack switch. Reduce false trips and ensure safety compliance.

Layout & safety highlights Left: Kelvin and sense RC; Center: minimal gate loop with per-FET Rg; Right: creepage/clearance with TVS return path, Do/Don’t. Kelvin & Sense • Rsense true Kelvin to IC pins • RC filter at IC side • Avoid crossing high dI/dt zones Gate Loop (Min Area) • Independent Rg per FET (parallel/B2B) • Tight gate-source return loop • Fast discharge path for turn-off Creepage & ESD • Slots or clearances at HV gaps • TVS near connector, short return • Keep signals away from gate node ✔ Short TVS return ✘ Long return through signal ground Power Path Symmetry & Copper/VIAs • Symmetric routing for parallel FETs (gate/drain/source) • Multi-via arrays at hot nodes; check current density vs. rise • Mark creepage distances on silkscreen for QA
Kelvin to IC pins, tight gate loop with per-FET Rg, symmetric power path, and explicit clearances.

Sense & Kelvin

True Kelvin lines; RC at IC side; keep away from high dI/dt regions.

  • Divider to local reference ground.
  • TVS where cables/ports enter.

Gate Loop

Independent Rg per FET; fast discharge path; minimal gate-source loop area.

  • Inner-layer or short outer-layer gate trace.
  • Miller clamp/RC as needed.

Creepage & Clearance

Slots/keep-out at HV gaps; label distances; keep connectors away from board edge.

  • Moisture/contamination margin by IEC category.
  • Conformal coating notes if required.

Validation Playbook

Bench procedures for worst-case loads, inrush/surge, ESD immunity, and traceable records before release.

Validation workflow Flow: Bench setup → Worst-case loads → Inrush/Surge & ESD → Protection exercises → Data capture. Bench Setup Worst-Case Loads Inrush/Surge & ESD Protection Exercises Data Capture Checklist • Waveforms: I_inrush, V_GS, V_DS, V_sys, PG/FLT timing • Conditions: cable length/awg, ambient, case temp • Pass/Fail: inrush < spec; no brownout; protection acts as set • Attach thermal image with hotspot coordinates
Follow a repeatable flow and capture the same proof set on every build.

Bench Setup

Program supply & load; real cable length/awg; scope with current & differential probes.

  • Log ambient, unit ID, HW/FW versions.
  • Probe points for Iinrush, VGS, VDS, Vsys.

Worst-Case Loads

Cold start + hot-plug; max Csys and longest cable; high/low temperature repeats.

  • Dynamic load steps; reverse/port backfeed scenarios.
  • Monitor PG stability and fault logs.

Inrush & Surge

Precharge first; dV/dt soft-start; verify peaks and no brownout resets.

  • Peak Iinrush < spec; VGS/VDS within limits.
  • Adjust Rpre and Rg as needed.

ESD/Immunity

IEC 61000-4-2 points; EFT/Surge where applicable; device recovers automatically or via controlled reset.

  • No permanent damage; faults logged correctly.
  • PG/FLT behavior matches the policy.

Pass if: inrush within spec, no brownout, protections act per settings, PG stable, and thermal hotspot within limits. Fail if: false/ missed trips, PG chatter beyond limit, permanent ESD damage, or thermal exceedance.

IC Selection — 7 Brands

Browse by function buckets with quick specs and procurement cues. Replace “Series / Notes” with official PNs and datasheet values during publishing.

IC card legend Symbols for back-to-back FET, ideal-diode, latch, auto-retry, and low Iq shipping. B2B FET Blocks reverse current Ideal-Diode One-way path Latch / Auto-Retry Fault action policy Low Iq / Shipping µA standby, wake options
Tag meaning used across all IC cards below.
Pack Protector Pack Switch B2B FET Ideal-Diode AEC-Q100 Low Iq Pin-to-Pin
TI — protectors & high-side drivers with shipping/wake options.

Series · Pack Protector

OVP/UVP/OTP/OCP/Short with Latch/Retry policies.

DriverHS / B2B
Iq (Ship/Norm)µA / low
PkgQFN / SOT-23
Notes: shipping mode + charger wake.
Pack ProtectorLatchAuto-RetryLow Iq

Series · Pack Switch Driver

High-side gate driver for single/B2B FET; dV/dt & precharge friendly.

DriverHS / Single or B2B
VpackWide
PkgQFN / MSOP
Notes: good with ideal-diode path.
Pack SwitchB2B FETPrecharge

Series · Low Iq & Ship

Ultra-low standby with button/charger wake and PG/FLT lines.

Iq (Ship)µA
SignalsPG / FLT / EN
PkgSOT-23 / QFN
Low IqWakePG/FLT
ST — robust protectors and ideal-diode controllers.

Series · Pack Protector

Complete matrix with programmable thresholds.

ActionOff / Latch / Retry
SenseKelvin-friendly
PkgQFN
Pack ProtectorLatch

Series · Ideal-Diode Controller

Backfeed stop for ports/multi-source, pairs with pack switch.

DirectionOne-way
CoordinationWith HS driver
PkgMSOP/QFN
Ideal-DiodeBackfeed
NXP — automotive-focused pack switches & signals.

Series · Automotive Pack Switch

High-side B2B with PG/FLT and wake integration.

GradeAEC-Q100
DriverHS / B2B
PkgQFN
AEC-Q100PG/FLT

Series · Low Iq & Wake

Shipping µA, charger/button wake, debounce built-in.

IqµA class
WakeChg / Button
PkgSOT / QFN
Low IqWake
Renesas — protectors with flexible action policies.

Series · Pack Protector

OV/UV/OCP/Short/OTP with configurable debounce.

PolicyOff/Latch/Retry
SensingRsense + filters
PkgQFN
Pack ProtectorRetry
onsemi — efficient FET drivers and ideal-diode paths.

Series · High-Side Driver

Single/B2B FET drive; good for smooth dV/dt.

TopologyHS single/B2B
AssistPrecharge ready
PkgDFN/QFN
Pack SwitchB2B FET

Series · Ideal-Diode

Backfeed prevention; pairs with port power mux.

UsePorts & OR
Coord.HS driver
PkgSOIC/DFN
Ideal-DiodeBackfeed
Microchip — simple protectors, small packages.

Series · Compact Protector

Small-outline pack protector for space-limited designs.

PkgSOT-23 / DFN
IqLow
SignalsPG/FLT
Small PackagePin-to-Pin
Melexis — automotive signals & protection helpers.

Series · Auto Helper

Signal conditioning / diagnostics around PG/FLT.

GradeAEC-Q100
RoleDiag / Logging
PkgSOIC/QFN
AEC-Q100PG/FLT

Tip: Use buckets + tags to shortlist, then verify thresholds, Iq, driver type, and action policies against your #sizing outcomes.

FAQs

Concise, actionable answers. Each points back to relevant sections for deeper guidance.

What standby Iq is “safe” for shipping mode, and where does leakage usually hide?
Target µA-range with outputs off. Audit leakage from divider chains, indicator LEDs, sense amps, and gate drivers. Verify quiescent current at temperature corners and after long storage. Provide a clear wake path (charger, button, or system). See: Use Cases, State.
How do I avoid inrush spikes and brownout during wake-up?
Precharge Csys to a safe Vpre, then soft-start the main path with controlled dV/dt (gate resistor or driver setting). Measure Iinrush, VGS/VDS, and Vsys. Tune Rpre and Rg if peaks or resets occur. See: Sizing, State.
How should I set OVP/UVP thresholds and hysteresis to prevent chatter?
Place OVP near the charge ceiling with margin; UVP above rebound voltage. Add hysteresis tied to noise σ and a minimum on/off time. Keep the RC near the comparator and use true Kelvin sensing. See: Protections, Sizing.
OCP vs. Short-Circuit: when to use limit, off, or latch?
For steady OCP, limit or delayed off protects thermal margins; for shorts, use µs-scale cutoff and often latch to prevent oscillation. Ensure fast gate discharge and validate with worst cable inductance. See: Protections.
Do I need both reverse-polarity protection and an ideal-diode path?
Use back-to-back FETs for reverse isolation at the pack; add an ideal-diode path when ports/multi-sources could backfeed. Coordinate thresholds to avoid chatter during switchover. See: Topologies, Protections.
How do I set a safe reverse-current limit for backfeed scenarios?
Define Irev from connector/port specs and pack chemistry limits. Enforce direction with ideal-diode, and cut off via the pack switch if reverse exceeds the set window. Log the event for diagnostics. See: Protections.
What matters most when choosing FETs: VDSS, RDS(on), or Qg?
All three: keep VDSS above pack + surge, pick RDS(on)(T) for losses, and size Qg vs. available gate current to balance EMI and heat. For parallel/back-to-back, use matched gates and symmetric copper. See: Sizing, Topologies.
Why isn’t SOA additive when FETs are paralleled?
Thermal and dynamic sharing are imperfect; one device often takes more stress. Use matched FETs, identical Rg, tight layout symmetry, and confirm with surge-width testing against datasheet SOA curves. See: Sizing.
What are common layout mistakes for Kelvin sensing and the gate loop?
Pulling sense from power pads, running Kelvin lines across high dI/dt zones, sharing gate resistors between FETs, and long gate-source return loops. Keep loops tight and RC filters near the IC. See: Layout & Safety.
How should I plan creepage/clearance around the pack switch?
Mark distances on silkscreen, use slots at HV gaps, retreat connectors from board edge, and allow moisture/contamination margin per IEC category. Add conformal coating notes if needed. See: Layout & Safety.
What’s a minimal ESD/EFT/Surge test set before release?
IEC 61000-4-2 ±8/±15 kV at ports/case, EFT and Surge per product class, and recovery verification. Capture the same waveform set every build for traceability. See: Validation.
Best practice to log PG/FLT so field issues are diagnosable?
Debounce PG (5–20 ms), latch FLT on any protection, and clear by timeout/reset/cool-down. Store timestamp, code, and count; export at service points. See: State.
What to verify when doing pin-to-pin cross-brand replacements?
Match thresholds, Iq (ship/normal), driver type, action policy, timing (debounce/hysteresis), and thermal limits. Re-run inrush/surge/ESD and confirm PG/FLT behavior. See: IC Selection, Validation.
When should I switch to an eFuse/Hot-Swap or a full BMS/AFE?
Choose eFuse/Hot-Swap for board-level inlet control and current limiting; choose BMS/AFE for multi-cell balancing, stack monitoring, and diagnostics beyond pack-level switching. See siblings: eFuse/Hot-Swap, BMS/AFE.
Lead time looks risky—how do I keep alternatives ready?
Shortlist by buckets/tags first (protector vs. HS driver vs. ideal-diode). Keep a pin-to-pin option and one “near-fit” per brand. Validate once and archive waveforms/checklists for fast swaps. See: IC Selection, Validation.

All FAQs reflect pack-level protection & switching. For chargers or cell-monitoring AFEs, use sibling pages.

Resources & RFQ

Download executable worksheets and templates, then submit your BOM/RFQ for 48h turnaround. Files use fixed names so you can update them later without changing links.

PDF

bp-protector-sizing-worksheet.pdf

Worksheet for thresholds, Rsense, FET & thermal quick estimates.

Est. size~200–400 KB
Download
XLSX

bp-dvdt-inrush-calculator.xlsx

Estimate precharge R and allowable dV/dt vs. Csys & Iinrush.

Est. size~50–120 KB
Download
PDF

bp-bringup-checklist.pdf

Power-on, safety, and scope capture list for repeatable bring-up.

Est. size~120–250 KB
Download
PDF

bp-validation-report-template.pdf

Pass/fail criteria, waveform slots, and signature lines for audits.

Est. size~180–350 KB
Download

How we help

  • Cross-brand selection with action policy (Latch/Retry) and Low-Iq shipping.
  • Pin-compatible alternates; quick checks on thresholds & thermal headroom.
  • Risk notes on inrush, ESD, and SOA for your topology.

Before you upload

  • Include PN, alt allowed, package, thresholds, current, and temperature range.
  • Add port/OR needs (ideal-diode), PG/FLT signaling, and wake sources.
  • Mention test status (inrush, ESD, short) if available.

Sibling Pages

Related topics—text links only to avoid duplication. Explore each area for deeper design details.

  • Charger PMIC

    USB-C/PD, JEITA, CV/CC charging path control—pack-level protection covered on this page only.

  • eFuse / Hot-Swap

    Board-level inlet protection and hot-plug with current limiting, surge handling, and fault logging.

  • Load Switch / Ideal Diode-OR

    Board-level path multiplexing and one-way conduction for multi-source systems.

  • Supervisors / Watchdog

    System power-good, reset timing, and watchdog coordination with pack PG/FLT.

  • PMBus / PSM

    Digital monitoring & configuration for multi-rail power—beyond pack-level switching.

Links are placeholders—adjust to your site’s actual URL structure.

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