Series Bandgap Reference: Low Power, Wide VIN, PSRR

Q: How do I budget initial accuracy, tempco, line/load regulation, and long-term drift into one number?

Express every contributor in millivolts at the application temperature span and operating points. Convert tempco from ppm/°C: ΔV = VREF × TC × ΔT. Translate line/load regulation into mV for your VIN and ILOAD excursions. Add long-term drift for the intended service life. Combine either by worst-case summation for guarantees, or RSS for statistical designs, then compare to your allowable error.

Q: What PSRR must a reference meet when the upstream is a switching buck with X mV ripple?

Decide the maximum allowed ripple on VREF, then back-solve PSRR at the buck’s fundamental and harmonics: ΔVREF = ΔVIN / 10^(PSRR/20). Include any input filter attenuation and buffer gain. Check at 100 kHz–1 MHz where many bandgap buffers roll off. If PSRR is insufficient, add RC/π filtering or a pre-regulator to meet the target margin.

Q: How do I convert ppm/°C into mV error for 2.5 V and 4.096 V rails across −40~+125 °C?

Use ΔV = VREF × TC × ΔT, where TC is in ppm/°C and ΔT is the temperature span. For −40 to +125 °C, ΔT = 165 °C. Example: 25 ppm/°C on 2.5 V gives 2.5 × 25e-6 × 165 ≈ 10.3 mV. On 4.096 V, the same TC yields ≈ 16.9 mV. Add this term into your total accuracy budget alongside initial error and drift.

Q: Series vs shunt: when does a shunt still win for tiny currents or ultra-wide VIN?

Shunt references can be attractive when you need two-terminal simplicity, very wide VIN, or to establish precise thresholds in current-mode loops. They tolerate broad bias currents and can be embedded as error-amplifier elements. However, for low Iq, stable line/load regulation, and buffered rails feeding ADCs or DACs, a series reference is typically quieter, more efficient, and easier to filter.

Q: How do I size output capacitor/ESR to avoid oscillation with long traces and load steps?

Check the datasheet’s stability window for Cout and ESR, then account for temperature and aging drift. Long traces add series inductance; include a small series resistor or an end-of-line RC snubber to damp resonances. Target phase margin ≥ 45–60°. Validate with worst-case load steps and VIN corners, measuring overshoot, undershoot, and settling within your allowed LSB window.

Q: What RC/noise-band setting keeps a 16-bit ADC’s SNR from collapsing?

Limit integrated VREF noise to a small fraction of one LSB_rms over the converter’s effective bandwidth. Choose RC so the reference noise above the ADC’s sampling and image bands is strongly attenuated, but transient droop during sampling remains acceptable. Use the ADC’s input model to check acquisition time and step load. Validate SNR/ENOB with coherent tones and known OSR.

Q: How do I derate dropout margin vs temperature and load transients?

Dropout grows with temperature and load because device mobility falls and buffer headroom increases. Reserve extra VIN–VREF margin for cold-crank, hot-soak, and dynamic load steps. Plot minimum VIN across corners and include source impedance. If headroom is tight, add a pre-regulator, reduce VREF, or relax load transients using soft-start and local storage capacitors near the reference pin.

Q: What layout rules cut ground bounce and ripple feedthrough into ADC/DAC rails?

Use Kelvin sense back to the reference’s ground pin. Join AGND and DGND at a single low-impedance point. Keep the reference, its RC/π filter, and decoupling capacitors tight and isolated from switching currents. Avoid magnetic field coupling from inductors. Route VREF away from high dv/dt nodes, and ensure measurement points use short loops with low-inductance probing.

Q: Can I share one reference between ADC and DAC without crosstalk?

Yes, but buffer and isolate. Provide separate decoupling and small series resistors for each branch to reduce load-induced modulation. Ensure the reference driver can source and sink combined dynamic currents. If ADC sampling transients corrupt DAC output or vice versa, add an additional buffer stage or split rails. Verify with simultaneous worst-case activity patterns and spectral measurements.

Q: What acceptance test proves the PSRR claim on my real board, not just SPICE?

Inject a known ripple at VIN or the upstream node using a wideband source and coupling network, then measure VREF with a low-noise front-end. Sweep key frequencies: 100 Hz, 1 kHz, 100 kHz, and 1 MHz. Record ΔVIN and resulting ΔVREF to compute PSRR. Control probe grounding and bandwidth. Compare against targets from the accuracy budget and document pass/fail.

What It Is & When to Use

A series bandgap reference forms an almost-constant voltage by summing a PTAT term with a CTAT V_BE term and adding curvature correction. The result is closed by an error amplifier and buffered to drive precision rails (2.048 / 2.5 / 3.0 / 4.096 / 5.0 V).

Lower Iq for battery devices.
Tighter line/load regulation for ADC/DAC/LDO reference rails.
Wider VIN envelope and predictable cold-start/UVLO behavior.

Common bins: 2.048 / 2.5 / 3.0 / 4.096 / 5.0 V. 2.048/4.096 V pair nicely with binary-coded converters. For industrial/automotive (−40~+125 °C), plan for cold-crank and transient immunity.

Aspect	Power (Iq)	Line/Load Regulation	VIN Efficiency	BOM/Cost (brief)
Series Bandgap	Low (favors battery)	Tight; buffered output	Wide VIN; stable across ramps	Typically moderate

Select (use series bandgap) if

Iq budget is tight (battery/IoT).
ADC/DAC/LDO rails demand tight line/load regulation.
VIN varies widely or ramp shape is tricky.

Avoid if

A tiny bias branch current must set simple thresholds.
Existing loop requires a two-terminal threshold element.

How It Works

Core synthesis: V_REF ≈ V_BE + k·ΔV_BE. Here, V_BE is CTAT and ΔV_BE is PTAT. The coefficient k is set by resistor ratio or device area ratio. Curvature correction (first/second order) shapes the tempco towards 10–50 ppm/°C.

An error amplifier closes the loop; the output is buffered to drive external loads. Stability depends on C_out/ESR, load steps, and wiring inductance—details are mapped to the ESR window in the stability section.

Startup circuits prevent latch-off and ensure reliable cold-start across process/temperature. Acceptance metrics include start time, minimum VIN, and behavior at −40/125 °C.

Noise arises from the core, the amplifier, and the buffer (low-frequency 1/f and broadband); PSRR varies with frequency (100 Hz / 1 k / 100 k / 1 MHz). Proper placement of RC/BUF and LC/π elements breaks ripple feedthrough to precision ADC rails.

Temperature Coefficient (TC)

Measure at −40/25/125 °C. Convert to ppm/°C, then back to mV on your chosen V_REF. Target 10–50 ppm/°C.

PSRR vs Frequency

Inject ripple at 100 Hz / 1 k / 100 k / 1 MHz; log ΔV_REF. Back-solve minimum required PSRR for your upstream spectra.

Noise (two bands)

0.1–10 Hz: μV_pp; 10 Hz–10 kHz: μV_rms. State the integration bandwidth explicitly.

Startup & Cold-Start

Verify start time, minimum VIN, and no latch-off at corners. Include a ramp-rate sweep to expose delayed starts.

Electrical Traits & Budgets

Build a one-number accuracy budget at the point of use by combining: initial accuracy, temperature coefficient, long-term drift, line/load regulation, noise (0.1–10 Hz μV_pp & 10 Hz–10 kHz μV_rms), and PSRR residuals at 100 Hz / 1 k / 100 k / 1 MHz. Provide both worst-case sum (WC) and RSS views.

Reference Bin & Accuracy

V_REF: 2.048 / 2.5 / 3.0 / 4.096 / 5.0 V
Initial accuracy @25 °C (% of V_REF)
TC (ppm/°C, −40~+125 °C)

Noise & PSRR

0.1–10 Hz noise (μV_pp)
10 Hz–10 kHz noise (μV_rms; bandwidth stated)
PSRR @ 100 Hz / 1 k / 100 k / 1 MHz

Operating Envelope

Iq; VIN range & dropout margin
Line/Load regulation (mV/V, mV/mA)
Stability window: C_out / ESR allowed

Temperature Drift (ppm → mV)

ΔV_TC = V_REF · TC · ΔT · 10⁻⁶
Example (TC = 20 ppm/°C, ΔT = 165 °C): 2.5 V → 8.25 mV; 4.096 V → 13.52 mV.

Total Accuracy (WC vs RSS)

WC: E_TOT^WC = Σ|E_i| (production/automotive)
RSS: E_TOT^RSS = √(Σ E_i²) (engineering estimate)

PSRR Back-Solve

PSRR_min(dB) = 20·log₁₀(ΔV_IN/ΔV_REF,target)
Example: 50 mV at 100 kHz, target 100 μV → 54 dB.

Contributor	Method (WC/RSS)	Freq / ΔT / Notes
Initial Accuracy		@25 °C
Tempco (ΔV_TC)		ppm/°C; −40~+125 °C
Line Regulation		mV/V
Load Regulation		mV/mA
Noise 0.1–10 Hz		μV_pp
Noise 10 Hz–10 kHz		μV_rms (BW stated)
Long-Term Drift		ppm/khr
PSRR Residual		freq-tagged
Total (WC)	Target ≤ X mV (pass/fail)
Total (RSS)	For engineering estimate

Edit bar widths to match your numbers; the red dashed line is the acceptance target.

Temperature Coefficient

Three-point method (−40/25/125 °C). Convert ppm/°C → mV on your bin.

Noise Measurements

0.1–10 Hz in μV_pp; 10 Hz–10 kHz in μV_rms with bandwidth stated.

PSRR vs Frequency

Inject at 100 Hz / 1 k / 100 k / 1 MHz; back-solve PSRR for your ripple.

Line/Load & Stability

mV/V, mV/mA; verify C_out/ESR window and step-load recovery.

Variants & Design Dials (Series Bandgap Only)

Low-Noise Route

Targets: LF ≤ X μV_pp; WB ≤ Y μV_rms; PSRR@100 k ≥ Z dB
Constraints: C_out/ESR in green window; Iq ≤ I_max
Side effects: higher Iq, cost/size

Nano-Iq Route

Targets: Iq ≤ Iq_max; t_start ≤ t_max; PSRR ≥ P_min
Advice: add endpoint RC; check load-drive
Side effects: weaker drive; WB noise may rise

Wide-VIN + Auto Route

Targets: VIN_max, PSRR@100 k/1 M ≥ P_min, TC ≤ T_max
Must pass: cold-start/UVLO; C_out/ESR green window
Side effects: Iq↑, cost↑

Low-Noise vs Standard Bins

Specify both bands: 0.1–10 Hz μV_pp and 10 Hz–10 kHz μV_rms. Low-noise bins trade higher Iq/size/cost for better ENOB margin.

Nano-Iq vs Wide-VIN Families

Nano-Iq favors sleep/periodic sampling; Wide-VIN favors cold-crank immunity and ripple headroom; ensure dropout margin across temperature.

Automotive/Industrial Grade

AEC-Q100 grade, −40~+125 °C. Plan long-term drift targets and bin/trim strategy for lot-to-lot consistency.

Curvature-Correction Depth

First vs second order shaping of TC and extreme-temp offsets; deeper correction may raise loop complexity/cost.

Buffer & Stability Window

Internal buffer type defines C_out/ESR green window; use endpoint RC for long traces; verify step-load stability.

Output Options & Trim

2.048/2.5/3.0/4.096/5.0 V fixed bins; factory trim improves initial accuracy but may impact drift/cost.

PSRR vs Frequency Profile

Check 100 Hz / 1 k / 100 k / 1 MHz; match to upstream buck/boost/linear spectra to limit residuals.

Package & Thermal

RθJA and self-heating amplify effective drift; respect height and airflow; keep hot parts away from the reference.

Series-only variant dials: each card shows measurable targets and typical side effects for selection.

Do Not

Drop nano-Iq parts into high-HF-noise rails without RC/BUF.
Assume low-noise bins are always better regardless of Iq/size.
Judge PSRR only at low frequency; check 100 k–1 MHz.

Selection Recipes

Convert scenarios into copyable process cards: set thresholds → compute limits → wire for stability → verify/accept. Replace placeholder symbols (α/β/γ etc.) with your targets to lock the decision.

A · ADC Reference (12/16/24-bit)

Goal: Keep V_n,REF and sampling transients from degrading SNR/ENOB.

Noise limit: V_n,REF,rms ≤ α·LSB_rms, α≈0.25。
LSB: LSB = V_FS/2^N; LSB_rms = LSB/√12。
Bandwidth: integrate across effective ADC bandwidth B; state B explicitly.

Example (16-bit, 4.096 V): LSB=62.5 µV; LSB_rms=18.0 µV → V_n,REF,rms ≤ 4.5 µV.

Sampling transient: I_kick≈C_S·ΔV/Δt; droop ΔV≈I_kick·Z_OUT,REF ≪ LSB。

RC/BUF: ensure Z_OUT,REF(f_s) ≪ LSB/I_kick; if needed add low-noise buffer; end RC at ADC REF pin.

B · DAC Reference

Goal: Prioritize line/load regulation; immunize against update glitches & load steps.

Line/Load ≤ specified mV/V & mV/mA across temp/load.
PSRR ≥ target at the DAC update clock and harmonics.
Isolate VREF from analog output rails (RC/π or buffer).

Step spec: ΔV ≤ β·LSB (β≤0.25); RC: 1–22 Ω + 1–10 µF || 100 nF, keep C_out/ESR in green window.

C · LDO Reference/Bias

Goal: Maintain dropout margin and startup order; attenuate upstream ripple.

V_IN,min ≥ V_OUT + V_DO(I,T) with 10–20% margin.
PSRR ≥ target at buck ripple bands (100 k–1 MHz) and 100/120 Hz.
Kelvin VREF return to LDO GND; end RC for long traces.

Sequence with PG/supervisor; avoid back-powering the reference node.

D · Low-Power IoT

Goal: Minimize Iq; guarantee hold accuracy under duty-cycled wake/measure/sleep.

Iq ≤ target (nA–µA); t_wake ≤ budget; bandwidth-limited noise.
Hold error: ΔV_hold ≤ γ·LSB (γ≤0.25).
C_H ≥ I_leak·t_hold/ΔV_hold; optionally gate the buffer.

Measure wake-time distribution vs temperature; compute average current.

Scenario	Noise (0.1–10 Hz / 10 Hz–10 kHz)	PSRR (100 Hz / 1k / 100k / 1M)	Iq	Cout / ESR window	VREF bins	Startup / Order	Notes
ADC 12/16/24-bit	≤ α·LSB_rms / limit in µV_rms across B	≥ P_min at f_s harmonics	As needed for BUF drive	Green window; end RC at ADC REF	2.048 / 4.096 V	REF before conversion; PG sync	Kelvin sense; separate AGND/DGND
DAC	Low WB µV_rms; LF pp optional	≥ target at update clock ± harmonics	Moderate	RC/π isolation; stability check	2.5 / 3.0 / 4.096 V	REF stable before output enable	Glitch + step recovery budget
LDO Bias	Moderate WB; LF pp low	≥ target at 100k–1M & 100/120 Hz	Per thermal budget	Green window; long-trace RC	2.5 / 3.0 / 5.0 V	Sequence with PG/supervisor	Dropout margin across temp
Low-Power IoT	BW-limited to meet γ·LSB	Enough at MCU clocks/radios	nA–µA class	Small C; hold cap per leakage	2.048 / 3.0 V	Wake→settle→measure→sleep	Gate buffer if needed
Tip: add a “Pass/Fail ≤ X mV” row to bind the one-number acceptance.

Use-case → recipe matrix: thresholds, calculations, wiring & verification at a glance.

Integration & Layout

Wire and route the reference like a precision sensor: quiet supply, Kelvin returns, controlled ESR, and clear injection/measurement points.

Decouple locally: 100 nF + 1–10 µF; add RC or π (C–R–C) if ripple spectrum demands.
Kelvin-sense VREF and GND; join AGND/DGND at a single star near the load.
Keep digital return currents off the reference path; no thin necks carrying pulse currents.
Long traces: add series R (1–22 Ω) + end RC (100 nF–1 µF) to tame ringing; verify ESD return path.
Coexistence with switchers: route away from inductors; shield or distance high di/dt loops.
Respect stability window: keep C_out/ESR in the green zone, even for parallel MLCCs.
Isolate VREF from AVDD decoupling; do not share high-current nodes.
Thermal: avoid hot spots; consider RθJA and self-heating amplification of drift.
Probing & injection: provide short-ground probe pads; series R for ripple injection.
Startup & order: gate with PG/supervisor; prevent back-power via diodes or gated paths.

Common Pitfalls

Over-paralleling MLCC → ESR too low → oscillation.
Ferrite as “magic filter” → high-Q peaking and phase issues.
Sharing VREF with large AVDD return currents.

Verification Pack

Ripple inject at 100 Hz / 1 k / 100 k / 1 MHz; log ΔV_REF.
Step load 0↔I_max; measure overshoot & settle time.
Cold/Hot start; check sequencing and back-power protection.

Place VREF like a precision sensor: quiet filter, correct returns, end RC at loads, and explicit keep-out from switchers.

Stability & ESR Window

Model the buffered series reference as a two-pole system: the dominant pole from (Rout‖Rload)·Cout, a secondary pole inside the amplifier, and a compensating ESR zero. The goal is phase margin (PM) ≥ 45–60° while meeting load-step limits (overshoot/undershoot and settle time).

Key Relations

ESR zero: f_z,ESR = 1/(2π·ESR·C)
Dominant pole: f_p1 ≈ 1/(2π·(R_out‖R_load)·C)
2^nd-order overshoot: OS ≈ e^−ζπ/√(1−ζ²) (ζ loosely maps to PM)
Load-step spec (recommended): OS ≤ 0.1%·V_REF or ≤ 0.25·LSB; t_settle ≤ target period

Design Steps (Copyable)

Set crossover f_c (per device guidance or 1–5 kHz).
Back-solve C_out so f_p1 < 0.2–0.3·f_c.
Place f_z,ESR within [0.3, 0.7]·f_c ⇒ solve ESR.
With aged/biased values (C_min, ESR_max) recompute PM, OS, t_settle.

Load-Step Protocol

0 ↔ I_max, edges at 100 ns / 1 µs / 10 µs (three speeds).
Record peak OS/US and t_settle (two thresholds: ±0.1% and ±1 LSB).
VIN (min/typ/max) × temperature (−40/25/125 °C) × DC bias (0/50%) combinations.

ESR–C map: keep f_z,ESR near 0.3–0.7·f_c; verify load-step overshoot and settle time across temperature and bias.

Select C from the target f_c; then solve ESR so f_z,ESR ≈ 0.3–0.7·f_c.
Re-check PM/OS/t_settle using C_min / ESR_max after temp/bias/aging.
If multiple MLCCs make ESR too low, add a small series R (0.1–1 Ω) to shape effective ESR.
For long traces, add series R (1–22 Ω) + end-point RC (100 nF–1 µF) to control ringing/Q.
Load step: 0↔I_max; fast/medium/slow; two thresholds (±0.1% and ±1 LSB).

Reliability & Drift

Quantify the time dimension: long-term drift (ppm/khr), post-reflow offset, self-heating, and automotive transients. Convert them into an executable aging matrix with clear acceptance bands.

Temp (°C)	Time (h)	VIN	Load	Metrics	Acceptance
25 / 85 / 125	0 / 168 / 500 / 1000	min / typ / max	open / typ / I_max	ΔV_REF (ppm), noise (0.1–10 Hz & 10 Hz–10 kHz), PSRR, t_startup	P95 ≤ X ppm @ each node; no accelerating trend

Conversions

ppm → mV: ΔV = V_REF · ppm · 1e−6
Self-heating: ΔT_self ≈ P · R_θJA, then ΔV ≈ V_REF·TC·ΔT_self
Aging (log-time trend): extrapolate ppm/khr to 1–5 years with Arrhenius (e.g., 0.7 eV) at use temperature

Automotive Notes

AEC-Q100 grade & temp range (−40~+125 °C typical for Grade 1)
ISO 7637-2 pulses: limit residuals on the reference rail via TVS/RC/π
Cold-crank/low temp: startup time and ringing acceptance

Post-Reflow Strategy

Measure pre-reflow baseline → reflow → 24–72 h → thermal cycle → re-measure
Define |ΔV_post| ≤ X ppm; after 3 cycles ≤ Y ppm
For critical rails: second trim/cal table or firmware compensation

Drift & reliability overview: quantify ppm vs time, reflow offsets, and self-heating induced drift; bind acceptance with P95/P99 limits.

Test log: sample IDs, lot/package, temperature profile, calibration certificates, measurement uncertainty.
BOM notes: automotive grade, temp range, long-term drift target, post-reflow recal strategy, transient immunity and reference-rail protection.
Annualized eval: convert 1000 h @ 125 °C to use temperature and output 1/3/5-year ppm targets.

Cross-Brand Mapping (Series Bandgap References)

Scope: external series/buffered bandgap voltage references only (shunt/TL431-class excluded). Focus dimensions: Low-noise, Wide VIN / Automotive, Nano-Iq, and General precision.

Texas Instruments

REF5050A-Q1 (5.0 V; low noise/low drift; automotive). Datasheet
REF3425 (2.5 V; low drift, low power; small footprint). Product page / DS
LM4132-Q1 (multi-V; precision LDO-style series ref; SOT-23). Product page · Datasheet (PDF)
REF50xxA-Q1 family (2.048/2.5/3.0/4.5/5.0 V; low noise/drift). Datasheet family

Notes: broad VREF options, Q1 grades available; good for low-noise ADC rails and automotive wide-VIN systems.

STMicroelectronics

TS33 family (1.2/1.8/2.048/2.5/3.0/3.3/4.096/5.0 V; micropower). Datasheet · Product page

Notes: very low Iq with industrial temp range; solid choice for IoT and portable designs needing series references.

Renesas

ISL21090 (1.25/2.5/5.0/7.5 V; ultra-low noise; wide VIN). Datasheet
ISL71090SEH25/50 (2.5/5.0 V; ultra-low noise; 4–30 V or 7–30 V VIN). 2.5 V DS · 5.0 V DS

Notes: excellent 0.1–10 Hz noise and long-term stability for 16–24-bit ADC/DAC systems; harsh-env variants available.

onsemi

No current mainstream discrete series/buffered precision reference family comparable to TI/Renesas/Microchip/ST. Consider cross-brand alternates above for external precision rails.

Microchip

MCP1501 (buffered series ref; multi-V; strong sink/source). Datasheet
MCP1525 / MCP1541 (2.5 V / 4.096 V; compact; easy sourcing). Datasheet · Product page

Notes: good drive for LDO/DAC rails; convenient SOT/TO-92 options for prototypes and small-batch builds.

NXP

Focused on MCUs/PMICs with internal bandgap; no widely available discrete series precision reference line. Use TI/Renesas/Microchip/ST for external VREF.

Melexis

Automotive sensors/actuators; precision bandgap is typically internal. No discrete series reference families comparable to above.

Use-case	TI	ST	Renesas	onsemi	Microchip	NXP	Melexis
ADC 16–24-bit (low noise)	REF50xxA-Q1 DS	TS33 DS	ISL21090 DS	—	MCP1501 DS	—	—
IoT / Micropower	REF34xx DS	TS33 PG	ISL21090 (low-Iq options by trim) DS	—	MCP1525/1541 DS	—	—
Wide VIN / Automotive	LM4132-Q1 DS	TS33 (-40~+125 °C) DS	ISL71090SEH25/50 DS	—	MCP1501 DS	—	—
LDO/DAC Reference Rail (drive)	LM4132-Q1 PG	TS33 PG	ISL21090 DS	—	MCP1501 DS	—	—

BOM & Procurement Notes

Required fields

VREF (2.048 / 2.5 / 3.0 / 4.096 / 5.0 V)
VIN range & dropout headroom
Initial accuracy & TC (ppm/°C)
Noise (0.1–10 Hz μVpp; 10 Hz–10 kHz μVrms)
PSRR at 100 Hz / 1 k / 100 k / 1 MHz
Iq (active/standby)
Stability window (Cout / ESR)
Package height & RθJA
AEC-Q100 grade (if required)
Second-source (Y/N)

Risks & mitigations

ESR window mismatch → lock specific capacitor PN; add end-RC or small series R for damping.
Pin/semantics mismatch → keep within same family/footprint where possible.
PCN/EOL exposure → prefer active families (TI REF34xx/REF50xxA-Q1, Renesas ISL21090/ISL71090, Microchip MCP1501, ST TS33).
MOQ/lead time → pick SOT-23/SC70 mainstream PNs; keep TO-92 fallback (e.g., MCP1525) for lab builds.

Submit your BOM

Need a cross-brand shortlist (TI / ST / Renesas / Microchip) with capacitor ESR window pre-checked? Send your constraints.

Submit BOM (48h)

Brand	Series / PN	Why	Datasheet
TI	REF5050A-Q1 (5.0 V)	Low noise & drift; automotive	ti.com/product/REF5050A-Q1
TI	REF3425 (2.5 V)	Low drift, low Iq, small footprint	Datasheet PDF
TI	LM4132-Q1 (multi-V)	Precision LDO-style series ref; EN pin	Datasheet PDF
Renesas	ISL21090 (2.5 V etc.)	Ultra-low 0.1–10 Hz noise; wide VIN	Datasheet
Renesas	ISL71090SEH25/50	Harsh-environment, 4–30 V/7–30 V VIN	2.5V · 5.0V
ST	TS33 (multi-V)	Micropower; −40~+125 °C	Datasheet
Microchip	MCP1501 (buffered)	Strong sink/source; handy for LDO/DAC refs	Datasheet
Microchip	MCP1525 (2.5 V) / MCP1541 (4.096 V)	Accessible PNs for prototypes; multiple packages	Datasheet · Product page

Frequently Asked Questions

How do I budget initial accuracy, tempco, line/load regulation, and long-term drift into one number?

Express every contributor in millivolts at the application temperature span and operating points. Convert tempco from ppm/°C: ΔV = VREF × TC × ΔT. Translate line/load regulation into mV for your VIN and ILOAD excursions. Add long-term drift for the intended service life. Combine either by worst-case summation for guarantees, or RSS for statistical designs, then compare to your allowable error.

What PSRR must a reference meet when the upstream is a switching buck with X mV ripple?

Decide the maximum allowed ripple on VREF, then back-solve PSRR at the buck’s fundamental and harmonics: ΔVREF = ΔVIN / 10^(PSRR/20). Include any input filter attenuation and buffer gain. Check at 100 kHz–1 MHz where many bandgap buffers roll off. If PSRR is insufficient, add RC/π filtering or a pre-regulator to meet the target margin.

How do I convert ppm/°C into mV error for 2.5 V and 4.096 V rails across −40~+125 °C?

Use ΔV = VREF × TC × ΔT, where TC is in ppm/°C and ΔT is the temperature span. For −40 to +125 °C, ΔT = 165 °C. Example: 25 ppm/°C on 2.5 V gives 2.5 × 25e-6 × 165 ≈ 10.3 mV. On 4.096 V, the same TC yields ≈ 16.9 mV. Add this term into your total accuracy budget alongside initial error and drift.

Series vs shunt: when does a shunt still win for tiny currents or ultra-wide VIN?

Shunt references can be attractive when you need two-terminal simplicity, very wide VIN, or to establish precise thresholds in current-mode loops. They tolerate broad bias currents and can be embedded as error-amplifier elements. However, for low Iq, stable line/load regulation, and buffered rails feeding ADCs or DACs, a series reference is typically quieter, more efficient, and easier to filter.

How do I size output capacitor/ESR to avoid oscillation with long traces and load steps?

Check the datasheet’s stability window for Cout and ESR, then account for temperature and aging drift. Long traces add series inductance; include a small series resistor or an end-of-line RC snubber to damp resonances. Target phase margin ≥ 45–60°. Validate with worst-case load steps and VIN corners, measuring overshoot, undershoot, and settling within your allowed LSB window.

What RC/noise-band setting keeps a 16-bit ADC’s SNR from collapsing?

Limit integrated VREF noise to a small fraction of one LSB_rms over the converter’s effective bandwidth. Choose RC so the reference noise above the ADC’s sampling and image bands is strongly attenuated, but transient droop during sampling remains acceptable. Use the ADC’s input model to check acquisition time and step load. Validate SNR/ENOB with coherent tones and known OSR.

How do I derate dropout margin vs temperature and load transients?

Dropout grows with temperature and load because device mobility falls and buffer headroom increases. Reserve extra VIN–VREF margin for cold-crank, hot-soak, and dynamic load steps. Plot minimum VIN across corners and include source impedance. If headroom is tight, add a pre-regulator, reduce VREF, or relax load transients using soft-start and local storage capacitors near the reference pin.

What layout rules cut ground bounce and ripple feedthrough into ADC/DAC rails?

Use Kelvin sense back to the reference’s ground pin. Join AGND and DGND at a single low-impedance point. Keep the reference, its RC/π filter, and decoupling capacitors tight and isolated from switching currents. Avoid magnetic field coupling from inductors. Route VREF away from high dv/dt nodes, and ensure measurement points use short loops with low-inductance probing.

Can I share one reference between ADC and DAC without crosstalk?

Yes, but buffer and isolate. Provide separate decoupling and small series resistors for each branch to reduce load-induced modulation. Ensure the reference driver can source and sink combined dynamic currents. If ADC sampling transients corrupt DAC output or vice versa, add an additional buffer stage or split rails. Verify with simultaneous worst-case activity patterns and spectral measurements.

What acceptance test proves the PSRR claim on my real board, not just SPICE?

Inject a known ripple at VIN or the upstream node using a wideband source and coupling network, then measure VREF with a low-noise front-end. Sweep key frequencies: 100 Hz, 1 kHz, 100 kHz, and 1 MHz. Record ΔVIN and resulting ΔVREF to compute PSRR. Control probe grounding and bandwidth. Compare against targets from the accuracy budget and document pass/fail.

How do I choose between nano-Iq and low-noise bins for battery devices?

Start from the system’s energy budget and allowable VREF noise. Nano-Iq parts extend battery life but usually raise wideband noise and reduce PSRR. If the converter oversamples or averages heavily, nano-Iq may suffice. For precision DC or low-frequency accuracy, pick low-noise bins and duty-cycle the reference or the measurement to meet both lifetime and performance targets.

What changes for AEC-Q100 rails—cold-crank, load-dump, and self-heating?

Validate operation across cold-crank droops and negative temperatures where dropout and loop gain shift. Protect against load-dump and ISO 7637-2 transients with input clamps and filters. Model self-heating: Tj = Ta + θJA × Pd; the resulting drift adds to the budget. Prefer Q-grade parts with documented drift, and verify across VIN corners and temperature extremes on the actual harness.

Verification & Delivery

A. Measurement Scripts

Temperature coefficient: Measure VREF at −40/25/125 °C (add −20/+85 °C if needed) after 10–15 minutes soak; fit TC in ppm/°C and convert to mV for your rail.
Board-level PSRR: Inject ripple at 100 Hz/1 k/100 k/1 MHz; record ΔVIN and ΔVREF to compute PSRR. Control probe bandwidth and grounding.
Noise: 0.1–10 Hz in μVpp and 10 Hz–10 kHz in μVrms; state integration bandwidth and windowing for comparability.
Load step stability: 0↔I_max with 100 ns/1 μs/10 μs edges; record overshoot/undershoot and settling at ±0.1% and ±1 LSB thresholds.
Long-term drift & post-reflow offset: Age at 25/85/125 °C for 0/168/500/1000 h; log ppm vs log(time). Pre-reflow → reflow → 24–72 h → thermal cycles → post-measure; define |ΔV| limits.

B. Acceptance Template (copy & use)

Total accuracy: Initial error + tempco (mV) + line/load regulation + noise (band-limited) + long-term drift + PSRR residual → combined ≤ target (RSS for statistics or worst-case for guarantees) with 10–20% margin.
Stability: Phase margin ≥ 45–60°; overshoot ≤ 0.1%·VREF or ≤ 0.25 LSB; settle within spec at C_min/ESR_max.
Reliability: P95 drift ≤ limit across stress matrix; post-reflow |ΔV| within limit; no upward trend after aging.

C. Resources

TI REF5050A-Q1: Datasheet / Product
TI LM4132-Q1: Datasheet
ST TS33: Datasheet
Renesas ISL21090: Datasheet
Renesas ISL71090SEH: 2.5 V · 5.0 V
Microchip MCP1501: Datasheet
Microchip MCP1525 / MCP1541: Datasheet

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Series Bandgap Reference

Series Bandgap Reference

What It Is & When to Use

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Avoid if

How It Works

Temperature Coefficient (TC)

PSRR vs Frequency

Noise (two bands)

Startup & Cold-Start

Electrical Traits & Budgets

Reference Bin & Accuracy

Noise & PSRR

Operating Envelope

Temperature Drift (ppm → mV)

Total Accuracy (WC vs RSS)

PSRR Back-Solve

Temperature Coefficient

Noise Measurements

PSRR vs Frequency

Line/Load & Stability

Variants & Design Dials (Series Bandgap Only)

Low-Noise Route

Nano-Iq Route

Wide-VIN + Auto Route

Low-Noise vs Standard Bins

Nano-Iq vs Wide-VIN Families

Automotive/Industrial Grade

Curvature-Correction Depth

Buffer & Stability Window

Output Options & Trim

PSRR vs Frequency Profile

Package & Thermal

Do Not

Selection Recipes

A · ADC Reference (12/16/24-bit)

B · DAC Reference

C · LDO Reference/Bias

D · Low-Power IoT

Integration & Layout

Common Pitfalls

Verification Pack

Stability & ESR Window

Key Relations

Design Steps (Copyable)

Load-Step Protocol

Reliability & Drift

Conversions

Automotive Notes

Post-Reflow Strategy

Cross-Brand Mapping (Series Bandgap References)

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Verification & Delivery

A. Measurement Scripts

B. Acceptance Template (copy & use)

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