H2-1 — Scope, power levels, and “fast charging” definitions (PD/PPS/QC)

This chapter locks the engineering boundary: only the adapter/charger hardware from AC mains to USB output (VBUS). It also defines PD, PPS, and QC in hardware terms so later chapters can stay evidence-driven and avoid cross-topic spill.

• Fixed voltage classes: 5V / 9V / 15V / 20V are the mainstream rails exposed on VBUS.
• PPS (Programmable range): commonly 3.3–21V with step changes; the sink may sweep voltage while drawing power.
• Typical power tiers: ~20–240W adapters exist; higher tiers amplify thermal, EMI, and protection tuning sensitivity.

• PD (Fixed PDO behavior): discrete VBUS setpoints; stress appears as step transitions and renegotiation events.
• PPS (Programmable Power Supply): quasi-continuous VBUS control; stress appears as sweep stability, cable drop compensation, and limit-mode interactions.
• QC (compat modes): alternative handshake that still maps to “VBUS mode selection + current limiting + protections” on the adapter side.

• CC/CV view: current limit and voltage regulation define normal operation and overload response.
• Constant power view: when power is held roughly constant, I ≈ P / V; lower VBUS implies higher current for the same watts.
• Adapter implications: the “worst-case heat” often shifts to low-voltage / high-current conditions (SR FETs, output inductors/caps, connector and cable losses, OCP margins).
• Evidence hook for later testing: electronic-load sweeps that separate CV/CC/CP regions make limit-mode behavior measurable (thresholds, settling, hiccup/latch decisions).

H2-2 — System block diagram: end-to-end power path & control domains

This architecture map provides a 30-second mental model of an AC-to-USB-C fast charger. The same diagram will be referenced by later chapters for EMI, PFC, flyback/ACF/LLC, SR, PD/PPS control, and debug evidence.

• Input protection & inrush: fuse/NTC/MOV set the survival envelope and inrush waveform.
• EMI filter: shapes conducted noise paths; strongly coupled to leakage/common-mode behavior.
• Bridge rectifier: creates the HV DC bus; commutation can become an EMI contributor.
• (Optional) PFC: regulates the bulk bus and changes downstream operating points and stress.
• Isolated conversion: flyback/ACF/LLC + transformer delivers isolated energy to secondary.
• Secondary SR + filter: drives efficiency, ripple and transient response at high current.
• USB-C PD control domain: CC detection, contract enforcement, VBUS gating/sensing.

• Energy domain: AC → bulk → switch node → transformer → SR → VBUS.
• Regulation domain: primary loop (current/voltage sensing, clamp/snubber stability) and secondary dynamics (LC damping).
• Protocol/policy domain: PD/PPS sets allowed VBUS behavior and may trigger detach/limit based on faults.

• TP1 Bulk bus (post-bridge / post-PFC): reveals brownout/hold-up and ripple stress.
• TP2 Primary switch node (drain): reveals ringing, clamp health, and switching regime.
• TP3 Secondary rectification region (SR gate / rect node): reveals SR timing and ringing.
• TP4 VBUS ripple & transient at connector: correlates to detach, OCP/OVP triggers, and device complaints.
• TP5 CC1/CC2 status + PD fault reason: separates “policy detach” from “power collapse”.

H2-3 — Input protection + inrush + EMI filter: what to choose and what breaks

Adapter front-end hygiene determines surge robustness, conducted EMI margin, leakage behavior, and long-term reliability. This section focuses on measurable cause–effect: component coordination, waveform fingerprints, and pre-scan evidence.

• Protection stack: fuse + MOV/TVS define the “energy absorption → disconnect” sequence under surge events.
• Inrush shaping: NTC (or relay/active inrush) controls the bulk-cap charging current at plug-in and hot-replug.
• EMI network: X-cap and DM elements target differential-mode noise; Y-cap and CM choke manage common-mode return paths.
• Hidden coupling: Y-cap and parasitic capacitance form a leakage path; CM noise reduction often trades against touch/leakage constraints.

• DM sources: bridge commutation and pulsed charging of the bulk capacitor; also the switching current ripple in the primary power stage.
• CM sources: fast dv/dt at the primary switch node couples through parasitic capacitance (primary-to-secondary, heatsink-to-chassis, winding capacitance).
• Victim linkage: CM paths often dominate broad-band rise in the conducted EMI spectrum; DM paths often create stronger “tone-like” peaks around switching harmonics.

• Conducted EMI pre-scan (LISN): capture spectrum at LISN ports and look for shape: harmonic clusters near switching frequency (edge/loop-driven) vs broad-band lift (CM-path-driven).
• Bulk correlation: measure TP1 bulk bus ripple while scanning; large line-cycle ripple can modulate switching behavior and spread noise.
• Inrush capture: record input current and bulk voltage ramp at plug-in; check for double-kicks, slow-ramp UVLO cycling, or abnormal peaks on hot replug.
• Quick isolation logic: if EMI shape shifts strongly with switching edge control (gate drive/slew) it is edge/loop dominated; if it shifts with Y-cap/CM network it is return-path dominated.

H2-4 — PFC or no PFC: when it’s needed and what it changes downstream

PFC is not a “checkbox”; it reshapes the bulk bus and changes downstream operating margins, brownout behavior, and hold-up dynamics. This section provides decision triggers and adapter-only evidence to validate the impact.

• Higher power tiers: as watts increase, peak input current and thermal density rise; bulk behavior becomes a stronger limiter.
• Efficiency/temperature goals: when low touch temperature at high output power is a priority, controlling the bulk bus can improve downstream margin.
• Wide-line robustness: when operation must remain stable across weak mains and brownout conditions, the bulk bus behavior becomes a first-class constraint.

• No-PFC bulk: rectified mains creates a large line-cycle envelope ripple; downstream stages must regulate across a wider instantaneous bus swing.
• PFC bulk: bulk is actively shaped; ripple amplitude and spectrum shift; downstream conversion sees a more controlled bus (but with its own switching artifacts).
• Practical consequence: control-loop headroom and protection thresholds should be evaluated against the bulk waveform, not a single DC number.

• Boost PFC: common architecture that shapes the bulk bus and input current profile.
• Transition-mode vs CCM: trade space between efficiency, EMI signature, component stress, and control complexity; the key is how each influences bulk ripple and switching noise coupling.

H2-5 — Primary conversion topology: Flyback vs ACF vs LLC (selection by power tier)

Topology choice becomes mechanical when driven by constraints: power tier, volume target, efficiency/thermal headroom, EMI risk tolerance, and BOM cost. This section maps those constraints to QR flyback, active-clamp flyback (ACF), and LLC, then links each to measurable “failure signatures.”

• QR flyback: strong candidate when cost and simplicity dominate and the design can tolerate higher peak stresses and stronger dependence on clamp/snubber tuning.
• ACF (active clamp flyback): favored when reducing primary stress and improving EMI/efficiency matter, while accepting extra control/timing sensitivity around the clamp loop.
• LLC: typically selected for higher power density and high efficiency, with the main risk shifting to tuning (resonant tank + operating window) and light-load behavior.

• Primary drain waveform: measure spike height and ringing decay; correlate with conducted EMI shape and device temperature rise.
• Primary current sense: check peak and slope consistency across line/load; look for jitter or abnormal cycle-to-cycle behavior.
• ACF clamp node / LLC resonant current: verify energy circulation remains controlled through transitions and at light load.
• Thermal map: identify hotspots (MOSFET, transformer, clamp device, rectifier path). Thermal hotspots are usually the limiting constraint.

H2-6 — Secondary side: SR, output filters, and ripple/transient control

Output quality and thermal limits are frequently secondary-limited. The rectification method (SR vs diode), output LC network, and real-world ESR/ESL determine ripple, transient response, and stability under PPS operating points.

• Higher output current: SR reduces conduction loss and can materially improve touch temperature and efficiency margin.
• Thermal bottlenecks: when the secondary rectifier is a hotspot, SR often provides the cleanest relief without changing the primary topology.
• Complexity trade: SR introduces timing and reverse-conduction control requirements, especially across light-load transitions.

• Controlled undershoot/overshoot: transient deviation remains bounded and does not trigger mode hopping.
• Fast settling without sustained ringing: a small number of damped cycles is acceptable; persistent oscillation indicates margin loss.
• No low-frequency wobble: repeated slow modulation often correlates with burst/skip interaction or poor sense placement.

• Operating point movement: PPS and constant-power tendencies shift V/I operating points, changing the effective loop gain and plant dynamics.
• Added delay/extra loop: cable drop compensation or remote sensing introduces additional phase lag; margin can shrink under worst-case cable and connector conditions.
• Practical symptom: load steps look fine at fixed 5V/9V, but become sluggish or ringy under PPS ranges due to reduced phase margin.

• Ripple measurement pitfalls: long probe ground leads create false ringing; use a short return method and consistent bandwidth limiting when comparing designs.
• Where to measure: compare ripple at the output capacitor pads vs at the connector to separate filter performance from cable/connector impedance.
• Load-step capture: record Vout + Iout simultaneously; look for recovery time, ringing decay, and any mode transitions (burst/skip) near light load.

H2-7 — USB-C PD/PPS/QC control plane: CC pins, VBUS switching, and policy enforcement

Fast-charging stability depends on a hardware control plane: CC detection establishes attachment and cable capability, the controller enforces a contract (PDO/PPS/QC), and VBUS power-path switching applies that policy to the power stage. Most “mystery” drops are explainable by correlating CC/contract state with VBUS droop and protection flags.

• Attachment integrity: CC instability can be induced by connector resistance, contamination, or noise injection from switching edges and return-path coupling.
• eMarker capability: cable capability limits current/power tiers; incorrect capability reads typically lead to repeated fallback or “won’t step up” behavior.
• VCONN reliability: unstable VCONN can manifest as intermittent cable-ID reads and contract oscillation under load transitions.

• Soft-start / inrush control: dv/dt limiting and current limit behavior determine whether a contract change causes a VBUS dip.
• VBUS OVP and discharge: over-voltage responses and controlled discharge behavior affect renegotiation stability and “quick reattach.”
• Reverse-current management: prevents back-feed and reduces false fault triggers during rapid PPS transitions.

H2-8 — Sensing, protections, and metering: making faults explainable

Protection that triggers without explanation looks like random instability. Explainable protection ties sensing, thresholds, blanking/deglitch windows, and action modes (foldback/hiccup/latch) to a minimal telemetry set so the reason for each fallback is recoverable.

• OVP: distinguish short spikes from sustained overshoot using a deglitch window; record peak and dwell time.
• OCP/SCP: define whether the trip is peak-based or average-based; coordinate blanking time around setpoint changes and soft-start edges.
• OTP: apply hysteresis and recovery rules to avoid temperature-edge chatter that mimics intermittent drops.
• UVLO / brownout: treat input sags as a diagnosable class of events (counter + timestamp), not a “silent” reset.

• Fault code: OVP/OCP/SCP/OTP/UVLO and the action taken (foldback/hiccup/latch).
• Context snapshot: VBUS, temperature, Ipeak, and an input brownout counter to separate line events from load events.
• Sequence / counters: retry count, hard reset count, and “last contract” index so control-plane and power-plane timelines can be aligned.

• Blanking/deglitch windows: apply around soft-start, contract changes, and PPS setpoint transitions to suppress sampling of predictable spikes.
• Layered limits: separate policy-level power limiting from hardware fast-trip; ensure one clear dominant path per event class.
• Deterministic recovery: define recovery thresholds and hysteresis for OTP/UVLO to prevent state chatter that looks random.

H2-9 — Thermal design & derating: why chargers throttle or die

Thermal problems are rarely “everything is hot.” Most throttling and sudden failures are dominated by one or two hotspots (primary switch, transformer, SR devices, or the USB-C interface) coupled to a weak thermal path to the enclosure and ambient. A measurable thermal approach links loss sources, thermal resistance paths, time constants, and derating policy.

• Junction → package: sets the first temperature rise step; limited by silicon and package design.
• Package → PCB: copper area, vias, and local plane geometry determine whether heat spreads or stays concentrated.
• PCB → enclosure → ambient: the most common “shortest board” in compact chargers; drives touch temperature and long-duration stability.

• Too far from the hotspot: protection reacts late, allowing repeated thermal stress before derating engages.
• Too much thermal mass: slow response (large τ) masks transient heating during PPS sweeps and load steps.
• Wrong coupling: measuring “air pocket” or enclosure skin temperature can miss junction peaks in switching devices and SR paths.

• Low-voltage PPS regions: maintaining the same output power forces higher current, pushing SR devices, output copper, and the connector toward worst-case heating.
• Policy coupling: when thermal derating changes available current, contracts can fall back, and repeated policy changes can look like instability unless logged.

H2-10 — Validation test plan (bench): pass/fail criteria and minimum instrumentation

A compact but deep bench validation plan reduces field surprises. Each test item should define setup, measurement, and pass criteria in a consistent format, and should generate artifacts that correlate electrical behavior (VBUS, ripple, transients, protections) with control-plane behavior (contracts, PPS sweeps, attach/detach cycling).

• Leakage awareness: Y-cap choices and layout impact touch sensation and leakage behavior; treat anomalies as design risks.
• Isolation boundary: any unexpected coupling or breakdown indicators are hard-stop issues; record as failures for design review.

• Brownout: observe recovery mode (limit/hiccup/latch), and confirm counters/logs make the event class explainable.
• Surge/EFT/ESD (power-stage level): look for false trips, resets, repeated renegotiation, and persistent drift after events.
• EMI pre-scan: identify signature shapes (CM vs DM, switching harmonics, rectifier commutation components) to drive targeted design fixes.

• PDO stepping: step 5/9/15/20V contracts and correlate VBUS droop with policy state and protection flags.
• PPS sweep: sweep voltage setpoints to expose false OCP windows and transient instability; record Ipeak and VBUS min duration.
• Attach/detach cycling: repeated connect/disconnect to validate consistent detach reasons, counters, and stable re-attach behavior.