What this page delivers

Engineering outcomes expected at the end of this page

• A one-page architecture decision (1S/2S, ports, pass-through policy, power budget).
• A measurable definition of “capacity” (Wh and cut-off points), not only “mAh on label”.
• A consistent trip order for protection layers (port protection → system limit → pack protection → cell safety).

Design-decision bullets (link specs to block choices)

• If 65W is required, define sustained power at temperature first; then decide 1S vs 2S based on current/heat density and enclosure limits.
• If interoperability is a priority, cover common fixed PDOs robustly before expanding PPS; PPS adds mode-transition and droop corner cases.
• If pass-through is promised, specify allowed output behavior during transitions; require power-path/load-sharing that prevents VBUS dips triggering PD fallback.
• If “accurate battery %” is a requirement, define full/empty points and the calibration workflow; gauge accuracy is limited by ESR drift, temperature, and cut-off thresholds.
• If “not hot to touch” is required, declare derating policy explicitly (step-down vs smooth throttling) and test with worst-case stack (charge + discharge).

When it wins

Boost-only architectures simplify control and reduce component count. The primary design stress shifts to the battery-side current path, connector losses, and hot-plug stability.

• Battery-side peak current: at higher output power, 1S battery current rises quickly and dominates heat density.
• Cable/connector sensitivity: VBUS droop from IR loss can trigger PD fallback, resets, or oscillating re-negotiation.
• Pass-through limitations: without true load sharing, attach/detach events often cause output glitches.

When it wins

A bi-directional buck-boost provides control headroom across multiple VBUS targets and mitigates droop sensitivity. The real complexity is mode management (charge ↔ discharge ↔ OTG) and risk edges during transitions.

• Mode transitions: attach/detach, PPS step changes, and role swaps are common glitch sources.
• Protection interaction: current limiting + thermal derating must be coordinated to avoid “limit oscillation”.
• Evidence-based debug: stable operation requires predictable signals at VBUS/BAT/SYS/ISENSE/NTC during transitions.

When it wins

A 2S pack reduces battery current for the same output power, improving thermal headroom and sustained delivery. The tradeoff is increased pack management complexity and stricter safety/protection coordination.

• Lower battery current: reduces MOSFET and copper losses, improving sustained output stability.
• Pack policy: cut-off, protection trip order, and gauge calibration must align with 2S behavior.
• Implementation cost: additional protection considerations and integration effort.

Key policy decisions

• Shared DC-DC: lower BOM, but requires explicit arbitration (priority, fairness, minimum guarantees) to prevent unexpected droop or fallback.
• Per-port power path: better fault isolation and simpler interoperability, at higher BOM and area.
• Dual-C risk: simultaneous negotiations, role swaps, and PPS step changes require a deterministic policy manager to avoid oscillations.

• Placement: pack-side measurement is required for consistent SoC under varying load and charge direction.
• Core signals: pack current (coulomb count), pack voltage (OCV correction & cut-off), temperature (cold/heat behavior).
• Architecture dependency: pass-through and frequent direction changes increase the need for a stable sense point and transition-aware filtering.

• Synchronous buck-boost (4-switch): supports multiple VBUS targets and bidirectional power flow with controlled transitions.
• Buck + boost split stage: can be cost-effective in some 2S designs but increases mode boundaries and transition edge cases.
• System-level inductor sizing: impacts heat, transient response, and EMI margin; treat it as a stability and thermal knob, not only an efficiency knob.

• Reverse-blocking: prevents back-feed when another source is attached; typically implemented with back-to-back FETs or ideal-diode control.
• Load sharing (pass-through): input power feeds system load first; remaining power charges the pack; the pack supplements when input is insufficient.
• Protection order: port protection → system limiting → pack protection must be deterministic to avoid oscillation and “mysterious resets”.

• Soft-start / precharge: limits inrush into downstream capacitance and avoids adapter resets and droop-triggered renegotiation loops.
• Droop guard: define a minimum VBUS window during transitions; enforce a controlled ramp rather than a hard connect.
• Cable reality: long or high-resistance cables amplify droop; stable behavior must be validated with worst-case cables.

Glitches occur at “risk edges” where control targets, current direction, or port roles change faster than the power stage and protection layers can settle.

• Attach/detach: sudden topology change; common outcomes are VBUS dip, PD fallback, or latch-off if protection order is unclear.
• PPS step change: VBUS target jumps; weak transition policy can produce overshoot/undershoot and renegotiation loops.
• Pass-through enable: power direction and current limit rules shift; incorrect sequencing causes oscillation between charge and discharge.

• VBUS: detect droop, overshoot, and recovery time; correlate with negotiation fallback events.
• BAT and SYS rails: determine whether the pack or system rail is collapsing during transitions.
• ISENSE (Rsense or internal sense): see current direction changes and whether limiting is oscillating.
• NTC/temperature: confirm derating entry/exit behavior and thermal-triggered policy changes.
• SW node (qualitative only): identify abnormal hiccuping or repeated restart patterns during droop events (no deep control-theory required).

• Role decisions change the power path: VBUS switch states, current direction, and limit rules can flip within milliseconds.
• Dead-battery behavior must be deterministic: before a full contract, the system should avoid large inrush and protect SYS from brownout.
• Risk edges: attach/detach and role swap are the most common triggers for droop, resets, or re-negotiation loops.

• Fixed PDO (simpler): fewer transition edges, lower debug cost, often the best “stability-first” baseline.
• PPS (more flexible): can reduce loss and improve charging behavior, but introduces step transitions that stress droop guard and mode policy.
• System requirement for PPS: clean VBUS ramps, controlled inrush, and transition-aware current limiting to prevent fallback loops.

• Droop is a system event: cable + connector loss reduces VBUS margin and can cause brownout resets or PD fallback.
• Heat makes it worse: connector temperature increases resistance, shrinking margin further during sustained load.
• Design consequence: define a droop guard policy (ramp/limit/derate) instead of “hard-connecting” into full load.

• Budget must be sustained: thermal derating should dynamically reduce available watts and trigger planned downgrades.
• Prevent “steal” behavior: a new contract should not collapse an existing port without a deterministic downgrade path.
• Define minimum guarantees: reserve baseline power for the protected port, or limit negotiation options when budget is tight.

• E-marker dependency: cable capability can restrict reachable contracts; design should degrade gracefully when the cable is limiting.
• VCONN budget: powering VCONN is a real load; it impacts thermal headroom and multi-port budget under edge cases.
• QC behavior: treat voltage changes as transition events; apply the same ramp and droop guard discipline as PD target updates.

• Coulomb counting: excellent for dynamic tracking but highly sensitive to offset, drift, and direction-change handling.
• OCV-based correction: requires relaxation; errors grow when the pack rarely rests or when loads are pulsed.
• Hybrid: reduces long-term drift but depends on temperature and impedance modeling consistency across real-world conditions.

• Placement defines truth: the sense point must capture the pack current actually entering/leaving the pack across all modes.
• Kelvin routing prevents false offsets: poor Kelvin pickup or shared return paths inject load-dependent error.
• Temperature drift matters: drift looks like “phantom current” over time and accumulates SoC error.

• Cold sag: higher impedance increases voltage drop under load, triggering early cut-off even when SoC appears high.
• Aging shift: impedance rises with cycles; without model adaptation, displayed SoC becomes optimistic under load.
• Design consequence: cut-off policy and SoC display must remain consistent under high-power discharge and low temperature.

• “Full” must be conditional: learning should occur only when termination and thermal conditions are valid.
• “Empty” must reflect system cut-off: if the system cuts off early under load, learning logic must account for that behavior.
• Avoid over-learning: too-frequent recalibration can create instability in displayed SoC and user experience.

• Hostless: faster integration and stable baseline behavior, but limited coordination with complex multi-port policies.
• Host-based: enables system-aware filtering and event-based learning, with higher firmware and validation cost.

• Precharge: limits current into a low-voltage pack; unstable precharge often looks like “starts then stops”.
• CC (fast charge): current is bounded by input budget (VBUS droop), thermal headroom, and protection limits.
• CV taper: the system is most sensitive to threshold definition; noisy current sensing can cause premature termination or looped re-start.
• Termination & recharge thresholds: overly aggressive settings produce “never reaches 100%” or frequent top-up heating cycles.

• Multi-zone policy: use step-down or slope derating to avoid swelling risk and prevent repeated OTP trips.
• Sensor representativeness: NTC placement must reflect cell temperature, not a local hotspot (inductor/FET) that causes false derating.
• User-visible outcome: well-designed derating looks like “slower charge”, not “random disconnect”.

• Pack protector (protector IC + dual FET): last-line defense for cell safety; should not be the first responder for external port faults.
• System eFuse / current limit: best as an early, recoverable responder to port-side shorts, overloads, or cable faults.
• PMIC-integrated protection: fast and compact, but policy and recovery behavior may be less configurable than a dedicated stack.

• Auto-retry: improves perceived robustness but can create heat and oscillation if the root cause persists.
• Latch: safer and more diagnosable, but requires a clear recovery action (re-plug, button, timeout).
• Best practice: use step-back (reduce power/current) before hard trip, especially for OTP and droop-related events.

• Mismatch dominates behavior: cell imbalance increases early cut-off and SoC inconsistency under load.
• Architecture consequence: 2S packs typically need clearer per-cell monitoring boundaries to avoid repeated protection events.
• System objective: prevent “one cell trips, the product looks dead” by defining recovery and user-facing behavior explicitly.

• High-load discharge: DC-DC switching loss + inductor copper loss + connector I²R are dominant contributors.
• Fast charge: input path loss + charger PMIC dissipation + pack impedance heating determines internal temperature rise.
• Pass-through: the worst-case blend—bidirectional flow and frequent transitions stress both thermal margin and policy stability.

• Inductor / HS FET: hotspots that drive junction temperature and trigger internal protections.
• Sense resistor: I²R heating can distort measurement and accelerate derating decisions.
• Connector: contact resistance increases with heat, turning droop into a thermal runaway mechanism.

• Representative placement: one NTC cannot represent both cell and hotspot; separate “cell safety” and “hotspot protection” intents.
• Multiple sensors: add a hotspot sensor near the power stage and a pack-focused sensor closer to the cells.
• Junction reporting: use IC die temp as fast protection input, but keep policy consistent with external NTC to avoid policy fighting.

• Step-down (staged): predictable power levels; easier to validate and to explain in UI behavior.
• Analog throttle: smoother, but must avoid oscillation with protocol steps and power-path transitions.
• Policy stability: enforce cooldown hysteresis and minimum dwell time to prevent rapid up/down power toggling.

• Material matters: metal spreads heat to reduce hotspots, while plastic often concentrates heat near the power stage.
• Skin temperature target: policy should be constrained by both hotspot safety and external touch comfort.
• Thermal path: prioritize contact quality (pad/interface) and copper spreading before increasing complexity.

• Switch loop radiates when its loop area and ringing are uncontrolled.
• Connector loop turns the cable into an antenna; long/poor cables amplify droop and ringing.
• Sense loop is often the first victim—noise corrupts current/voltage readings and causes false limits or gauge glitches.

• ESD diode placement: the goal is to clamp early and keep discharge current out of sensitive return paths.
• Common-mode choke: targets common-mode energy on the cable; it is a cable-antenna control tool.
• VBUS TVS selection: must balance clamp strength vs added capacitance/leakage that can destabilize negotiation on long cables.

• VBUS overshoot: can trigger input OVP or cause internal rail disturbance at attach.
• Ringing + droop: long-cable inductance increases ringing energy; droop increases the chance of PD reset or MCU brownout.
• Design intent: reduce loop energy (short paths, controlled ramp) and protect without forcing repeated attach cycles.

• Return path consistency: keep high-current return out of measurement/control reference paths.
• Shielding reality: metal/plastic enclosure decisions change where common-mode currents flow and where ESD energy returns.
• Goal: a predictable return path prevents noise from masquerading as real current/voltage events.

• Two cables: known-good short cable + long cable to expose droop/ringing sensitivity.
• One fixed load: resistive or electronic load at a stable level to remove “real device” variability.
• Thermal A/B: warm soak vs cool soak to separate thermal derate from protocol/power-path faults.
• Port A/B: single-port vs dual-port to reveal shared budget or return-path interactions.