Qi Wireless Charging: Tx Drivers, Rx Power-Path, FOD & Thermal
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Qi wireless charging is a closed-loop system: stable charging comes from keeping the Tx drive/modulation, Rx rectification + power-path, FOD, and thermal derating in a safe operating margin even when alignment and materials change. Most “slow/hot/drop/reconnect” issues can be pinned down quickly using two evidence streams—bus V/I behavior and temperature/log timelines—then mapped to the right block for a targeted fix.
Definition & Engineering Boundary: what this page solves
This chapter pins down a searchable definition, then “locks the scope” so every later section stays vertical: Tx drive/modulation, Rx rectification + power-path, FOD, thermal derating, and evidence-based validation.
Qi wireless charging is a near-field magnetic power link that transfers energy from a transmitter pad to a receiver coil while regulating delivered power with closed-loop control. Designs combine TX drive/modulation, RX rectification and power-path control, plus safety functions such as foreign-object detection and thermal derating, validated by waveforms, temperature curves, and event logs.
In scope
Tx driver & modulation control; coil/tank as engineering interfaces (no EM derivations); Rx rectifier + loss hotspots; Rx power-path behaviors (backfeed, dropout, limiting); FOD & thermal derating; validation evidence.
Out of scope
Wired fast-charge protocol deep dives (PD/QC/PPS); AC adapter power-stage topologies (PFC/flyback/LLC); battery cell management/balancing; OS/app/cloud topics; certification procedure walkthroughs.
Mention-only
USB-C input power and downstream battery-charger IC are referenced only to explain Rx power-path constraints (no charger algorithm details).
- Waveforms: Tx coil current/voltage & phase trend; Rx rectified-bus ripple; power-path dropout/UVLO edges; delivered power “hunting” signatures.
- Thermal curves: ΔT vs time at Tx/Rx hotspots; power vs time aligned to derating actions; misalignment sweep vs temperature rise.
- Event logs: re-ping/reconnect count; FOD trip codes/time-to-trip; thermal-state transitions (limit/derate/shutdown); power-request steps.
System context: where Qi lands, and why the Rx power-path is the control point
Wireless charging delivered power is not constant: it shifts with alignment, thermal state, and FOD actions. The Rx power-path is the component that turns a fluctuating rectified bus into a stable, safe supply for the device load.
System stability is dominated by whether the Rx power-path can (1) prevent backfeed into the rectified bus, (2) avoid dropouts during load steps, and (3) enforce current/thermal limits without forcing repetitive reconnect cycles.
Interface 1: rectified bus
The rectifier output is a “raw” DC bus whose ripple and sag reflect coupling and control dynamics. It must be monitored at the moment of attach, power ramps, and every reconnect.
Interface 2: system load
Smartphones and accessories exhibit burst loads (radio wakeups, display events, audio peaks). Load steps that exceed headroom will trigger bus sag → UVLO → re-ping.
Interface 3: sensing & thermal
NTC/temperature inputs and protection states should be treated as control inputs, not “extra signals”: derating decisions reshape delivered power and user-perceived charge behavior.
- Backfeed risk: When another source exists (wired input or battery-backed rail), the Rx path must block reverse current into the rectified bus to avoid heat and false trips.
- Dropout risk: A bus dip during load transients can reset the control handshake; minimizing UVLO “edge time” is often more important than peak efficiency.
- Limit behavior: Current limiting and thermal derating must be coordinated to reduce “hunting” (power up/down oscillation) that users experience as on/off charging.
| Form factor | Load profile | Power-path priority | Most sensitive failure symptom |
|---|---|---|---|
| Smartphone | Burst loads; frequent wake/sleep events; tight thermal comfort limits | Fast transient handling, robust dropout immunity, predictable derating curve | “Charging toggles on/off” during high activity or warm surfaces |
| Earbuds case | Lower average power; enclosure traps heat; small coils → alignment sensitivity | Backfeed blocking, low-loss rectification, thermal ramp management | “Slow charge + warm case” or early stop due to thermal state |
| Small IoT | Often steady load; minimal cooling; strict current budget | Simple stable bus regulation, conservative limiting, FOD/thermal safety margins | Attach succeeds but brownout occurs at peak load or during ramp |
End-to-end flow: from “attach” to steady power in 5 steps
Field symptoms such as slow charging, intermittent disconnects, and overheating map cleanly to one of five flow steps. Each step has a minimum evidence set (waveform / thermal / event log) that allows fast, non-ambiguous classification.
Why this 5-step model matters
- Prevents vague debugging: “It disconnects” becomes “disconnect occurs at Step-2 ramp” or “Step-4 load step”.
- Creates a shared evidence language: each step has 2 primary observables that are easy to capture and compare across builds.
- Locks the scope vertically: the root cause must be explainable by Tx modulation, Rx bus stability, power-path behavior, FOD, or thermal derating.
Step 1Detect / wake (ping & presence)
Must be true: coupling is sufficient for repeatable detection; the system enters a stable “presence-check” pattern.
Common failure shape: repeated attach retries, or success only with certain cases/magnet accessories.
Minimum evidence: (Waveform) repeatable detect-pattern on Tx coil current; (Log) attach/retry counter or failure code timeline.
Step 2Enter operating point (ramp & regulation start)
Must be true: modulation control reaches a stable operating point without hunting.
Common failure shape: brief charge, then drop; or power ramps but never settles.
Minimum evidence: (Waveform) coil phase jump / sudden waveform regime change; (Thermal) abnormal Tx hotspot ΔT slope during ramp.
Step 3Build a stable rectified bus (Rx rectifier)
Must be true: rectified bus ripple and sag remain inside the Rx power-path headroom window.
Common failure shape: “charging shown” but re-ping events occur; bus ripple triggers false state transitions.
Minimum evidence: (Waveform) Rx bus ripple + sag floor at load edges; (Log) UVLO/reconnect timestamp correlation.
Step 4Power-path supplies load (limit without dropouts)
Must be true: load steps do not pull the bus below UVLO; limiting actions do not induce repeated reconnect cycles.
Common failure shape: charge icon toggles; disconnect during screen/radio/audio bursts.
Minimum evidence: (Waveform) bus V + system current during step; (Log) limit-state toggles per minute.
Step 5Safety & derating (FOD / thermal / misalignment)
Must be true: safety actions are predictable and smooth (derate curve) rather than oscillatory.
Common failure shape: false FOD trips (slow charge), or thermal derating that looks like random disconnects.
Minimum evidence: (Thermal) ΔT–time aligned with power–time; (Log) FOD/thermal state transitions and dwell time.
Fast classification rules (keep debugging objective)
- Problem happens immediately at attach: prioritize Step 1–2 evidence (detect pattern + phase stability).
- Problem happens only under activity bursts: prioritize Step 3–4 evidence (bus sag floor + limit events).
- Problem worsens over time / heat: prioritize Step 5 evidence (ΔT slope + derate/FOD logs).
Tx drivers & modulation: why “same coil” can be stable on one device and unstable on another
Tx stability is dominated by where the system lands in the operating-point space. Misalignment, shielding, thermal rise, and Rx loading shift that operating point, changing losses, EMI behavior, and control-loop margins.
Engineering focus (not a standards walkthrough)
- Tx power stage: half-bridge/full-bridge + resonant tank as a controlled source for coil current and phase.
- Control knobs: frequency / duty / amplitude as practical levers that move the operating point and loss distribution.
- Required observables: coil current/voltage, phase trend, and input power estimate—enough to detect instability zones.
Minimum measurement set (3 probes, maximum leverage)
- Input power trend (Vin/Iin): identifies high-loss regions where input rises but delivered power does not.
- Coil current + phase trend: detects entry into unstable zones (phase jumps, regime changes, or periodic hunting).
- Tx hotspot temperature: validates whether losses concentrate in MOSFETs/coil/shielding during ramps or derating.
Instability red flags (actionable, field-friendly)
- Red flag 1 — phase jump: after a power step, phase flips abruptly and stays there → likely operating-point boundary crossing.
- Red flag 2 — periodic hunting: power ramps up/down with a repeatable period → control margin + thermal/limit coupling issue.
- Red flag 3 — sawtooth input power: input “zig-zags” while delivered power plateaus → high-loss region or misalignment-induced penalty.
Next-step verification actions (keep tests decisive)
Lock alignment (mechanical fixture), repeat the same load step, then repeat at a lower starting temperature. If the red flag disappears only with improved alignment, the operating-point shift is alignment-driven; if it disappears only with cooling, the boundary is thermally driven; if neither helps, focus on loop dynamics and sensing accuracy.
Coil, matching, and alignment: one root cause behind efficiency, heat, and disconnects
Misalignment and structural metal do not only reduce efficiency—they shift the operating point into a joint failure zone: Tx current rises, the Rx rectified bus becomes less stable, loss concentrates into hotspots, and safety derating or reconnect loops become more frequent.
Causal chain (alignment → loss → thermal → derate/disconnect)
- Coupling drops (offset/tilt/gap): Tx raises coil drive to meet a power request → Tx Icoil / input power trend up.
- Rx headroom shrinks: less effective energy transfer → rectified-bus ripple rises, sag floor drops.
- Loss re-distributes: more energy becomes heat in Tx/Rx/shield/nearby metal → ΔT slope increases.
- Safety actions engage: thermal derate or loss-based safety margins tighten → delivered power steps down.
- User-visible symptoms: slow charging, on/off charging, warm pad/device → reconnect events cluster at certain offsets.
Engineering consequenceWhat coupling change looks like in measurements
Tx-side signature: coil current increases and phase/operating point shifts; input power can rise while delivered power plateaus.
Rx-side signature: rectified bus ripple grows and sag floor deepens, increasing UVLO and reconnect probability.
Shield / metalWhy structural metal changes heat and safety margins
Shielding and nearby metal parts can reduce external field and improve coexistence, but they also introduce additional loss paths and alter the “baseline loss” seen by the system. When baseline loss is higher, the margin for distinguishing abnormal loss becomes narrower—raising the risk of conservative derating or, in some builds, weaker sensitivity to truly abnormal loss.
Moat evidence: alignment scan test (offset → delivered power → ΔT)
- Scan variables: X/Y offset (primary), gap (optional), tilt (optional).
- Must-record outputs: delivered power (or equivalent), Tx input power, ΔT at key hotspot(s).
- Optional outputs: reconnect count per minute; Rx bus ripple/sag at the “critical offset band”.
- Interpretation: input power rising while delivered power falls indicates entry into a high-loss region; a sudden increase in ΔT slope marks the thermal-dominated boundary.
| Scan point | Offset / gap | Delivered power trend | Tx input power trend | ΔT hotspot trend |
|---|---|---|---|---|
| Center | 0 mm | highest / stable | lowest for same request | slow rise |
| Edge band | mid offset | drops / more steps | rises | faster rise |
| Critical band | large offset | plateau or collapse | sawtooth / spikes | ΔT slope “knee” |
Rx rectifier deep dive: why “low power” can still run hot, and why low voltage is harder
Rx-side heat is often dominated by low-voltage, high-current physics: small conduction drops and path resistance scale into large losses, while bus ripple and sag become more likely to trigger UVLO and reconnect behavior. Rectifier choice and timing quality decide where heat concentrates.
Diode vs synchronous rectification (engineering trade-offs)
- Diode rectification: simple and robust, but fixed forward drop makes low-voltage efficiency poor; heat concentrates in diodes and current paths.
- Synchronous rectification: better at low voltage due to lower effective drop, but depends on timing and gate drive quality; mistiming can increase loss sharply.
Loss mapWhere heat actually concentrates
Conduction loss: MOSFET Rds(on), diode drop, and copper path resistance dominate at low voltage/high current.
Timing-related loss (brief): overlap or reverse conduction events amplify heat and distort the rectified bus waveform.
Gate-drive overhead (brief): frequent switching and large gate charge add power that becomes local heat.
Failure modes that lead to instability or disconnects
- Ripple / sag driven UVLO: bus floor dips below the power-path headroom → UVLO → reconnect loop.
- Sync-rectifier mistiming: reverse conduction or poor commutation → loss spikes + waveform distortion → control state churn.
- OV/UV excursions: bus crosses protection thresholds → derate/stop events; user sees “charging toggles”.
Evidence pack (must-have vs optional)
- Must-have evidence: rectified-bus ripple & sag floor (captured at attach and load edges), plus hotspot ΔT on the rectifier/current path.
- Optional evidence (if measurable): synchronous-rectifier gate timing waveform; state/flag logs for UV/OV/limit transitions.
Rx power-path: the core block that prevents dropouts, blocks reverse flow, and limits current
Wireless power arrives as a rectified bus with ripple, sag, and operating-point movement. The Rx power-path converts that “variable source” into predictable system behavior: stable supply to the load, controlled current limiting, and reverse-flow blocking. Most field “disconnect” symptoms are explainable by how the power-path reacts during bus build-up and load transients.
Three typical responsibilities (written as behaviors)
- OR-ing / path selection: chooses who powers the system and prevents unwanted backfeed into the rectified bus.
- Current limiting: clamps input stress and prevents the system load from pulling the bus below UVLO during bursts.
- Load priority: protects the system rail first; secondary sinks are reduced when headroom is tight (mention-only).
Field symptom mapping (fast root-cause narrowing)
| Symptom | Most likely mechanism | Fast evidence clue |
|---|---|---|
| “Lights up then drops” | Bus cannot build stable headroom, or load transient is too large at start; early limiting forces repeated bus collapse. | Vbus shows repeated climb → deep sag; reconnect count clusters within seconds of attach. |
| “Charges but keeps reconnecting” | UVLO triggers due to sag floor, or power-path state toggles (enable/limit chatter). | Vbus sag aligns with state transitions; Iin shows periodic hunting near a boundary. |
| “Gets hotter then slower” | Thermal rise drives limiting/derating; limiting increases request pressure and raises Tx/Rx losses. | ΔT slope increases before delivered power steps down; reconnect loop appears at higher temperature. |
Coupling loopThermal → limit → more stress → more thermal
Temperature rise reduces headroom and forces stronger limiting; the system attempts to sustain power, which pushes the Tx operating point harder. This raises losses in coils, shielding, and rectification paths, accelerating ΔT and driving deeper derating or reconnect behavior.
Evidence pack (two waveforms + timestamps)
- Waveform #1 — rectified bus voltage (Vbus): bus build-up, ripple, sag floor, UVLO proximity.
- Waveform #2 — input current (Iin): limiting entry/exit, hunting, boundary behavior under load steps.
- Timestamp alignment: correlate UVLO/limit/reconnect events (or counters) to the waveform moments.
FOD deep dive: detection as a decision chain, and why false positives and misses happen
FOD is fundamentally a safety guard against abnormal loss. The practical implementation is not a single threshold—it is a decision chain: estimate loss using measurable quantities, compare against a baseline, apply time integration to reject spikes, and tighten decisions using thermal rise rate. Most false alarms and misses come from baseline shifts (shielding/metal, alignment) and from “small but fast local heating” objects.
Core concept: abnormal loss (an engineering “loss budget”)
- Measure: input power trend (Pin) and delivered power trend (Pdel or equivalent).
- Estimate loss: loss behaves like “Pin − Pdel” plus known baseline contributors.
- Decide: abnormal loss is flagged when the estimate deviates persistently or when ΔT slope is inconsistent with the baseline.
Common false-positive causes (why the estimator gets fooled)
- Shielding material change: baseline loss increases → decision window narrows.
- Fixed metal brackets/screws: predictable loss looks like “foreign” loss.
- Magnetic accessories: changes alignment/gap and shifts operating point → loss estimate drifts.
- Coil offset: Pin rises while Pdel falls → abnormal-loss signature without a true foreign object.
- Temperature drift: component parameters shift → model mismatch and bias errors.
Common miss risks (what can heat locally without a big power signature)
- Thin / small metal: total loss may be modest, but local heating can be fast.
- Special positions: near concentrated flux regions where estimation error is larger.
- Fast local heating with weak Pin change: power-difference-only thresholds can be insufficient.
StrategyThreshold + time integration + ΔT slope coupling
Use a loss threshold to catch clear anomalies; add time integration to prevent short transient spikes from triggering; and couple decisions to ΔT slope so that “small but fast local heating” cases are handled more aggressively while stable thermal behavior avoids over-triggering.
FOD evidence test cases (repeatable and comparable)
- Objects: coin, key, thin metal sheet (at least three types).
- Placements: center, edge band, and offset band.
- Record: Pin, Pdel (or equivalent), ΔT, trigger time, and whether reconnect follows.
- Output: false-positive band vs miss-risk band mapped to alignment/temperature conditions.
Thermal management: temperature rise, derating curves, and “why charging slows down over time”
Thermal management is a control strategy that keeps the system safe while preserving user experience. The practical goal is to recognize where heat is generated, choose a derating mode that matches the product’s thermal path, and prove root cause using two aligned timelines: ΔT vs time and power vs time.
Heat source breakdown (measurable hotspots)
- Tx side: coil copper loss and power-stage switching loss; risk increases when alignment/gap worsens and coil current rises.
- Rx side: rectifier conduction loss, synchronous-rectification edge behavior, and output current-path loss at low voltage/high current.
- Shielding / metal / foreign objects: eddy-current and added loss that may create hotspots away from the IC.
Field practice: thermal probing should include at least one point near the Rx rectifier/current path and one point near a structural metal/shield region, not only the main IC.
Derating strategy menu (experience vs safety)
ModeStep-down power
Best user experience and stable waveforms. Suitable when thermal paths are predictable and hotspots are well-controlled. Typical signature: power drops in clean steps while charging continues.
ModeCurrent clamp
Protects bus headroom and avoids system droop. Useful when load bursts can collapse the rectified bus. Typical signature: current caps near a boundary; heating may still rise if operation stays in a high-loss region.
ModePause / retry
Most conservative for uncertain risks (possible foreign objects or poor thermal resistance). Typical signature: power periodically returns to near-zero, followed by reconnect and re-ramp.
Two slowdown paths (what “slower” usually means in measurements)
- Thermal-driven: ΔT slope rises → a derating threshold is reached → power steps down or clamps → charge rate reduces smoothly.
- Safety-driven: abnormal loss or fast local heating risk → pause/retry engages → charging becomes intermittent even if average power looks moderate.
Evidence method: ΔT vs time + power vs time (aligned)
- Curve A — ΔT vs time: track at least one Rx hotspot and one structural/shield hotspot.
- Curve B — power vs time: use input power (Pin) or delivered power trend (equivalent) as the control output.
- Alignment rule: if power steps down after ΔT slope inflects, derating is thermal-driven; if power periodically drops to zero without tight ΔT synchronization, pause/retry is likely.
- Keep conditions fixed: ambient temperature, alignment state, and load state must be held constant to avoid mixing alignment loss into the thermal narrative.
IC selection and BOM blocks: Tx, Rx, power-path, and sensing (a deployable checklist)
This section organizes the wireless charging design into functional blocks and lists the parameters that directly impact stability, heat, FOD robustness, and field debug observability. The goal is a practical checklist for engineering and procurement without turning into a product page.
BOM overview (functional map)
- Tx controller/driver: power regulation and observability hooks.
- Tx power stage: MOSFET/driver efficiency and thermal headroom.
- Rx rectifier / Rx PMIC: bus build-up, low-voltage efficiency, and protection behavior.
- Power-path: reverse blocking, current limiting, and load priority behavior.
- Sensors: temperature input and threshold hooks for derating decisions.
Deployable parameter checklist (5–8 per block)
| Block | Key parameters (selection-critical) | If selected poorly | Fast evidence |
|---|---|---|---|
| Tx controller / driver | input range; regulation step/granularity; response behavior near boundaries; sensing channels (coil current/voltage/phase as available); protection hooks; fault/status visibility; tolerance to alignment drift; thermal coordination hooks. | compatibility dropouts; hunting near operating point; unstable ramp; poor debug visibility. | Iin hunting patterns; event flags/timestamps; attach/reconnect counts. |
| Tx power stage | MOSFET Rds(on); Qg (drive loss); thermal resistance; package heat spreading; SOA/transient tolerance; gate driver strength; controllable edge behavior; layout/loop sensitivity. | unexpected heating at moderate power; early derating; intermittent resets under offset. | hotspot localization; power vs time step-down at lower-than-expected ΔT. |
| Rx rectifier / Rx PMIC | synchronous rectification capability; bus operating range; UVLO/OV behavior; low-V efficiency; ripple tolerance; fault handling; thermal protection; observability pins (status) if available. | “lights up then drops”; frequent reconnect; high heat at low voltage; unstable bus build-up. | Vbus ramp/sag; rectifier gate timing (optional); ΔT at rectifier/current path. |
| Power-path / ideal diode / load switch | limiting mode (clamp/foldback behavior); reverse blocking effectiveness; conduction drop; thermal headroom; soft-start behavior; state visibility; UVLO interaction; stability under load steps. | bus chatter; repeated UVLO; reverse-flow issues; “works cold, fails hot.” | Vbus + Iin aligned to timestamps; limit boundary patterns; reconnect periodicity. |
| Sensors (temperature) | NTC interface support; multi-point sensing support; accuracy class; sampling speed; threshold hooks; ADC/comparator integration; placement guidance; debouncing/time filtering support. | over-trigger or under-trigger derating; inconsistent behavior across units; unsafe local hotspots. | ΔT slope vs action timing; thermal map repeatability across placements. |
Mention-only: downstream battery charger ICs or USB-C rails may exist in the system power tree. Keep this page focused on wireless blocks and link out to dedicated pages when deeper coverage is needed.
H2-11 Validation & Field Debug SOP: evidence-first for “slow / drop / heat / false FOD”
What this SOP guarantees
The goal is a minimum closed-loop bench that reproduces field symptoms and converts them into two pieces of evidence: (A) bus V/I behavior and (B) temperature/log timeline. With these two, most issues can be classified to alignment/coil loss, Rx rectifier & bus stability, power-path gating/UVLO, Tx loop hunting, or FOD threshold drift.
Bench validation plan (minimum closed-loop)
Build a reproducible setup before touching thresholds: the objective is to make each failure repeatable with one variable at a time (offset, load, object, ambient).
| Test | Variable / sweep | Log (minimum) | Pass vs typical fail signature |
|---|---|---|---|
| Offset scan | Center, ±X, ±Y (e.g., 0/±5/±10 mm) | Delivered power estimate, VBUS, IIN, ΔT hot-spot | Pass: smooth degradation. Fail: “power cliff” + fast ΔT rise near common placement. |
| Load step | Light → heavy → hold (repeat 3×) | VBUS dip, IIN surge, reconnect events, UVLO flag | Pass: small dip + recovery. Fail: VBUS collapses → reconnect loop. |
| FOD matrix | Coin / key / thin foil; location near coil edge vs center | Input power, delivered power, ΔT, trip time / event code | Pass: consistent trip time for unsafe cases. Fail: false trip on safe stack-up or late trip on risky object. |
| Warm-start | Start at 25°C vs 40–50°C case temperature | Power vs time, ΔT slope, disconnect rate | Pass: predictable derating. Fail: threshold edge → intermittent reconnect. |
| ESD/EMI spot-check | Key seams/buttons/USB shield (test points only) | Reset count, connect_state toggles, error codes | Pass: no state latch. Fail: “stuck in ping/retry” after disturbance. |
Field debug “two-evidence method” (fast triage)
For each symptom, capture exactly two evidence types first. Avoid changing multiple parameters before the failure becomes repeatable.
| Symptom | Evidence A (V/I) | Evidence B (thermal/log) | Most likely bucket |
|---|---|---|---|
| “Lights for 1–3s then drops” | VBUS never builds or collapses on first load surge; IIN spikes then zero | Disconnect timestamp aligns with UVLO / protection code | Rx bus stability / power-path gating / load inrush |
| Intermittent reconnect | VBUS shows periodic dips; IIN saw-tooth; phase/power hunting (if visible) | Repeating connect/disconnect at near-constant interval | Control loop hunting, threshold edge (thermal/FOD), marginal alignment |
| “Charging gets slower over time” | Power request/delivered power ramps down while VBUS stays stable | ΔT rises then derating curve activates (stepwise or slope-based) | Thermal derating (Tx/Rx loss), coil/misalignment loss |
| False FOD trip | Input power appears “high vs delivered” even on safe stack-up | Trip correlates with temperature drift / accessory / chassis variation | FOD calibration/estimator mismatch, shielding/material change, drift |
Symptom → root-cause quick map (actionable checks)
| Symptom | First checks (in order) | Likely root cause | Block |
|---|---|---|---|
| Drop within seconds | 1) VBUS build-up slope 2) load-step dip 3) UVLO threshold edge | Bus cannot sustain inrush / UVLO triggers | Rx rectifier + power-path |
| Reconnect every N seconds | 1) periodic VBUS dip 2) IIN saw-tooth 3) thermal/FOD event boundary | Loop hunting or threshold oscillation | Tx control + Rx power-path |
| Hot but low power | 1) hot-spot location 2) delivered power vs IIN mismatch 3) offset sensitivity | High loss: misalignment / rectifier conduction / shielding loss | Coil/matching + Rx rectifier |
| FOD false trip on some builds | 1) compare same object test 2) chassis/fixture material delta 3) warm-start drift | Estimator mismatch vs mechanical stack-up | Tx FOD + thermal coupling |
| Works on some pads, fails on others | 1) offset cliff on “bad pad” 2) ripple/hunting under load 3) temperature rise rate | Compatibility margin (alignment/loop stability) | Tx modulation + coil system |
Example MPNs (reference-only, not a product list)
The items below are example material part numbers commonly used to build Qi Tx/Rx platforms and power-path/evidence logging. Equivalent alternatives exist across vendors; verify lifecycle, availability, and compliance for each design.
| Functional block | Example MPNs | Why useful in this SOP |
|---|---|---|
| Tx controller / manager |
STMicroelectronics STWBC2HP (Qi transmitter controller) NXP MWCT1012 (wireless charging transmitter controller) Texas Instruments BQ501210 (Tx manager, NRND on TI site — useful as legacy reference) |
Reproduce “pad-side” behavior (power control, modulation, FOD coupling). |
| Rx receiver / rectifier PMIC |
Texas Instruments BQ51013B (Qi receiver with synchronous rectifier) Renesas P9221-R (Qi receiver up to 15W class) STMicroelectronics STWLC38JRM (Qi receiver up to 15W class) Texas Instruments BQ51221 (receiver family reference, lower power class) |
Map “bus ripple / UVLO / thermal hot-spot” to Rx-side behavior. |
| Power-path / OR-ing / seamless switchover |
Texas Instruments TPS2121 (priority power MUX) Texas Instruments LM66200 (dual ideal diode w/ auto switchover) Analog Devices LTC4412 (ideal-diode controller, external MOSFET) |
Useful for “no backfeed / no drop / controlled switchover” and reproducing reconnect loops. |
| Current limit / protection (optional) | Texas Instruments TPS25940 (eFuse w/ reverse blocking & adjustable current limit) | Helps isolate “load step → bus collapse” as overload vs instability. |
| Temperature sensing / evidence logging |
Texas Instruments TMP117 (digital temperature sensor) Murata NCP15XH103F03RC (10k NTC, 0402 class; check lifecycle) Vishay NTCLE100E3 series (NTC family, used widely in sensing/control) |
Build repeatable ΔT curves and correlate with derating/fault events. |
| Bus V/I monitor (optional) | Texas Instruments INA238 (digital power monitor, shunt-based) | Creates clean V/I logs for the two-evidence method without manual scope capture. |
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H2-12 FAQs: symptom → evidence → section
These FAQs convert common Qi complaints (hot/slow/drop/reconnect/false FOD) into measurable evidence: bus V/I behavior + temperature/log timeline, then route to the right section for root-cause.
1) Why can the same phone become noticeably hotter or slower after adding a case or magnetic accessory?
Cases and magnetic accessories can change coil spacing, alignment repeatability, and the effective loss around shielding or metal parts. That often reduces delivered power while increasing pad input power, pushing the system into thermal derating or closer to the FOD boundary. The fastest confirmation is an offset scan (delivered power vs ΔT) with and without the accessory.
2) It shows “charging,” but disconnects after 10–30 seconds. Which two evidence signals should be captured first?
Capture (A) the rectified/bus voltage and input current over time, and (B) the temperature curve or event code timeline aligned to the same timestamps. A rapid bus collapse points to UVLO, inrush, or power-path gating; a stable bus with an immediate exit suggests a policy trigger (FOD/OTP) or control instability. Avoid changing multiple variables before the symptom becomes repeatable.
3) Low power is stable, but at high power it starts reconnecting repeatedly. Why?
High power shifts the system into a narrower stability margin: coil current rises, losses increase, and protection thresholds are approached. Reconnect loops typically come from control “hunting” on the Tx side, or power-path/UVLO oscillation on the Rx side when bus droop and limiting interact. Reproduce with a load step and a warm-start condition to expose boundary behavior.
4) Why does FOD false-trigger? Is it more often shielding/structure or threshold drift?
Both are common, but mechanical stack-up changes (shielding plates, chassis parts, magnets, coil spacing) frequently shift the loss estimate enough to mimic “abnormal” dissipation. Threshold drift becomes dominant when temperature or component aging moves the estimator baseline, causing borderline cases to flip states. The practical fix is evidence-based: compare input vs delivered power plus ΔT slope under controlled objects and positions.
5) How to distinguish “slow charging due to poor alignment” vs “slow charging due to rectifier/power-stage loss”?
Alignment-driven slow charging shows a strong spatial signature: delivered power drops sharply with offset, while temperature rise concentrates around coil/shield regions. Rectifier or power-stage loss shows a stronger electrical signature: bus ripple increases, hot spots cluster near the rectifier/power-path devices, and efficiency stays poor even at good alignment. A quick offset scan plus a bus ripple check separates these reliably.
6) Why does charging get slower as temperature rises? How should a derating curve be designed for good user experience?
As losses heat the system, thermal limits require reducing delivered power to keep hot-spot temperatures within safe bounds. Good experience usually comes from smooth, staged derating (rather than abrupt dropouts): limit current first, then step power down with hysteresis, and avoid rapid pause/retry loops. Always validate with “power vs time” and “ΔT vs time” curves under repeatable alignment.
7) If Rx bus ripple is large, is it usually a rectifier problem or power-path jitter?
Rectifier-related ripple often appears as consistent periodic ripple tied to switching/commutation behavior and can worsen with higher current. Power-path jitter more often looks like bursty droops or step-like oscillation, especially near current limit or UVLO boundaries, and may correlate with reconnect events. Measure bus ripple shape and timing relative to limiting flags; the waveform “texture” is usually enough to classify.
8) The requested power is stable, but Tx input power keeps drifting. Why?
Input power drift can come from Tx control hunting (frequency/duty/amplitude adjustments) as the operating point moves with temperature or coupling changes. It can also come from slow alignment changes in real use (micro-slips, magnet repositioning), which alter coupling and therefore coil current and losses. The discriminator is an offset sensitivity map: if small offset changes cause large Pin changes, coupling/misalignment dominates.
9) How to run an “alignment scan” that truly quantifies differences between mechanical designs?
Use a fixed grid (center, ±X, ±Y; optionally expand to 3×3), a fixed load profile, and a fixed logging format. Record delivered power estimate, input power, and at least two temperatures (Rx hot spot + case) with unified timestamps. Compare the “power cliff” location and the ΔT gradient across offset; these two metrics are usually more revealing than peak power alone.
10) Small, thin metal foreign objects can be more dangerous. Why, and how to improve detection rate?
Thin objects can concentrate eddy-current heating in a small area, creating a fast local temperature rise before total power looks extreme. That makes “global power anomaly” detection less sensitive, especially near coil edges or unusual placements. Detection improves by combining loss estimation with time integration and ΔT slope correlation (fast-rising hot spot), and by validating across object shapes and positions.
11) Users complain “it feels hot.” Should diagnosis start from Tx or Rx?
Start from the hot-spot location and the time alignment between heat rise and power behavior. If pad-side coil/power stage heats first and Pin rises, Tx loss or alignment sensitivity is likely. If Rx device area heats first with increased bus ripple or limiting, rectifier/power-path loss is more likely. A simple two-point temperature setup plus V/I logging usually resolves the direction quickly.
12) If only one hardware change is possible to improve stability, prioritize power-path or Tx sensing?
If failures look like bus collapses, UVLO trips, or reconnect loops under load steps, improving the Rx power-path (clean limiting, reverse blocking, stable switchover) usually yields the fastest stability gain. If failures look like periodic hunting with stable bus voltage, improved Tx sensing/control (better coil current/phase observability and stable control regions) tends to help more. Pick the change based on which signature dominates in two-evidence logs.
