This page shows how to choose and design a MUXed SAR ADC channel set so that many sensors share one converter core without losing accuracy, by controlling acquisition time, source impedance, crosstalk, front-end RC networks, calibration and diagnostics.

What this page solves

This page focuses on MUXed SAR ADCs with on-chip analog multiplexers used for multi-channel sensor polling. The goal is to design a single SAR core that scans many inputs while keeping crosstalk, incomplete settling, and source-impedance–related errors under control, so that each channel still meets its resolution and bandwidth targets.

The content is structured as a design-oriented application note: how to interpret MUX-related specifications, how to size acquisition time and front-end networks, and how to schedule channels and averaging for real sensor boards. It does not re-explain basic SAR conversion principles or cover fully simultaneous multi-core architectures, which are treated in separate topics.

The material is intended for engineers building multi-channel sensor input stages around a single MUXed SAR ADC, where channel count and cost matter more than perfect phase alignment between channels.

Basics & position in the ADC family

A MUXed SAR ADC combines an on-chip analog multiplexer tree, a single SAR conversion core and a channel sequencer into one device. Several input pins are switched, one at a time, onto the internal sample-and-hold and CDAC network, then converted by the same comparator and SAR logic. Multi-channel capability is achieved by time-multiplexing one core, not by having many cores in parallel.

Compared with using multiple single-channel SAR ADCs, a MUXed SAR part reduces board area, BOM cost and interface pin count, because only one converter and one digital link are needed. The trade-off is that all channels share the same front-end path and reference, so channel-to-channel crosstalk, shared configuration and non-simultaneous sampling must be managed at the system level.

Compared with a discrete external MUX plus SAR ADC, an on-chip MUX offers more tightly controlled on-resistance, leakage and parasitic capacitance, along with short internal routing and convenient channel sequencers. External multiplexers remain attractive when higher input voltage ranges, special common-mode windows or domain separation are required, at the expense of extra routing and error sources on the PCB.

A MUXed SAR ADC also differs from simultaneous-sampling / MxADC architectures. In a multi-core device, each channel has its own S/H and converter and can be sampled at the same instant, which is ideal for phase-critical current or position sensing. A MUXed SAR instead scans channels sequentially and is better suited to slowly varying, multi-channel measurements where channel count and cost are more important than nanosecond-level alignment. Phase-critical designs should refer to the dedicated simultaneous-sampling topic.

Typical MUXed SAR devices offer 4–32 channels, resolutions in the 12–18 bit range and core sample rates from roughly 10 kSPS up to about 1 MSPS. The effective sampling rate per channel scales with the number of channels being scanned; for example, a 16-channel, 1 MSPS core only delivers about 62.5 kSPS per channel when all channels are used equally, before any oversampling for noise reduction.

Channel architecture & timing model

Inside a MUXed SAR ADC, each analog input channel passes through ESD protection and an on-chip switch before reaching the shared sampling capacitor of the SAR core. For timing analysis this path can be simplified to a total resistance R_total = R_SRC + R_MUX charging an effective sampling capacitance C_S. ESD series resistors, switch on-resistance and external source impedance together define how quickly the sampling node can settle to a new input voltage.

During each conversion cycle the SAR core allocates time for acquisition and conversion. The acquisition window t_ACQ starts after the internal multiplexer switches to the next channel and the sample-and-hold enters track mode; during this interval the sampling capacitor charges through R_total toward the new input. The conversion window t_CONV follows, with the capacitor held, while the CDAC and comparator perform the successive-approximation bit trials. The total core cycle time t_CYC = t_ACQ + t_CONV is the inverse of the maximum ADC core sampling rate.

In a multi-channel configuration, the core repeats this sequence across channels: switch to channel k, acquire, convert, present a result, then advance to channel k+1. Scanning N channels in a round-robin pattern requires approximately N · t_CYC per full scan. If the core is operated at a total conversion rate f_ADC, the ideal per-channel sampling rate is roughly f_CH,ideal = f_ADC / N, before any extra averaging or digital processing.

The acquisition interval must be long enough that the sampling error on C_S is well below one LSB at the target resolution. Modeling the sampling node as a first-order RC, the residual error decays exponentially with R_total · C_S, leading to the familiar requirement that t_ACQ be several time constants long. For a given resolution N, t_ACQ is often chosen to satisfy a condition on the order of R_total · C_S · ln(2^N), with higher resolutions and larger input steps requiring more acquisition time. Any oversampling or per-channel averaging further reduces the effective per-channel sampling rate according to f_CH,eff = f_ADC / (N · M), where M is the number of samples averaged per channel.

Analog errors: crosstalk, settling & leakage

A multiplexed SAR front-end introduces several analog error mechanisms beyond those of a single dedicated channel. Input channels influence each other through crosstalk, incomplete acquisition leaves settling error, high-impedance sources are vulnerable to leakage, and switch dynamics introduce charge injection and jitter. Understanding how these mechanisms arise is essential for budgeting error in terms of LSBs, ENOB, INL, DNL and system-level noise.

Crosstalk appears when one channel’s voltage or edges disturb another channel. Capacitive coupling between adjacent input traces, internal nodes and ESD structures allows fast edges or large steps on an aggressor channel to inject charge into a victim channel. Shared paths in references, supplies or grounds can also convert channel current transients into small voltage shifts that show up in other measurements. Datasheet crosstalk specifications, often expressed in dB, quantify how much of a full-scale transition on one channel can leak into another channel’s reading.

Settling error occurs when the sampling node does not reach the final input voltage within the available acquisition time. The residual error after t_ACQ depends on R_total, C_S, the input step size and the required resolution. In a multiplexed system, the initial capacitor voltage for channel k is the previous sample, often taken on a different channel. Large differences between successive channel voltages therefore require longer acquisition time; otherwise, a portion of the previous channel’s value remains on C_S, creating a memory-like error that can look like offset, gain error or distortion depending on the signal pattern.

Leakage and charge-related effects further perturb the sampling node. Off-state switch leakage, ESD leakage and input bias currents slowly pull high-impedance sources away from their ideal value, causing droop between stimulus and sampling instant. Charge injection from MOSFET gates and drains during switching, together with aperture jitter, adds small but sudden voltage steps and random variation at the sampling instant. These contributions can be treated as additional offset and noise terms that reduce SNR and apparent resolution if not controlled by buffering, proper timing and layout.

For error budgeting, quasi-static mechanisms such as leakage and shared-path shifts are typically counted against offset, gain and INL, whereas dynamic mechanisms such as incomplete settling, crosstalk from large steps and charge injection are converted into equivalent LSB errors or RMS noise. A practical design reserve allocates only a fraction of one LSB to each error category, leaving sufficient margin for the converter’s intrinsic linearity and noise. The following sections translate these qualitative mechanisms into concrete front-end and timing design choices for multiplexed SAR systems.

Front-end design patterns for multiplexed sensors

In a MUXed SAR ADC system, the front-end network must simultaneously satisfy signal bandwidth, acquisition accuracy, channel-to-channel isolation and cost constraints. The effective source impedance seen by the sampling capacitor sets the required acquisition time, while RC filtering, buffering and protection devices shape noise and crosstalk behaviour. This section focuses on common RC and buffer topologies around the multiplexer, without entering into programmable gain stages or sensor-specific bridge and shunt circuits covered in dedicated topics.

One widely used pattern places a small RC filter on each channel directly in front of the multiplexer. Each sensor drives its own series resistor and shunt capacitor, providing per-channel noise reduction and basic anti-alias filtering. This approach offers low cost and simple layout, and it works well when sensor outputs are low to moderate impedance and channel bandwidth requirements are modest. However, the series resistor adds to the total resistance charging the sampling capacitor, so tighter resolutions or higher per-channel sampling rates require careful control of the RC values and acquisition time.

A second pattern keeps only basic protection components at each channel input, such as series resistors and clamp devices for surge and ESD, and moves the main RC filter and a buffer amplifier after the MUX. In this case the MUX switches selected channels onto a common low-pass network and a single buffer that drives the SAR ADC with low output impedance. This shared buffer approach provides a well-controlled anti-alias pole and robust drive for the sampling capacitor, while keeping op amp count and power moderate. The trade-off is that channels still share a common path through the buffer and reference nodes, so careful layout and routing remain important for isolation.

A third pattern adds a dedicated buffer amplifier for each channel, followed by a small RC filter before the MUX. Each sensor then sees a high input impedance and is isolated from the ADC by its own low-impedance driver. This structure is well suited to high-impedance sources such as NTC, pH and electrochemical sensors, as well as higher-resolution systems where acquisition time margins are tight. Individual RC networks can be tailored to each sensor’s bandwidth, and buffer stages reduce crosstalk by decoupling channels. The cost and power overhead per channel is higher, so this pattern is typically reserved for a limited number of precision or high-value inputs.

For high-impedance sensors, leakage and charge draw from the sampling capacitor can produce significant droop between updates, even when the apparent signal bandwidth is low. In such cases a per-channel buffer is often necessary to prevent MUX and ESD leakage currents from corrupting the reading. Protection elements such as series resistors and clamp diodes must also be considered as part of the effective source impedance; they protect against faults but lengthen acquisition time if sized too aggressively. Choosing between per-channel RC, shared RC plus buffer and per-channel buffering requires balancing bandwidth, settling time, crosstalk and cost for the specific mix of multiplexed sensors.

Throughput, latency & channel scheduling

A MUXed SAR ADC shares one conversion core across N input channels, so every design must convert the core sampling rate into per-channel throughput and update latency. The core cycles through acquisition and conversion intervals at an effective rate f_ADC. When N channels are scanned equally in a round-robin pattern, the ideal average sampling rate per channel is approximately f_CH,ideal = f_ADC / N. The time required to visit all channels once, the scan period T_SCAN, is roughly N · (t_ACQ + t_CONV + margin), where margin accounts for switching and digital overhead.

Many applications use oversampling and digital averaging to reduce noise and effective quantization error. If M samples are taken per channel and averaged before delivering a new result, the effective update rate becomes f_CH,eff = f_ADC / (N · M). The average interval between fresh values is set by this effective rate, while the worst-case latency from a change at the input to its appearance in processed data can approach a full scan period or multiple scan periods, depending on how channels are scheduled. Throughput budgeting must therefore consider both the average update frequency and the maximum acceptable delay.

Slow temperature and state monitoring channels typically require only a few samples per second, so they can tolerate large N and generous oversampling factors without stressing the core. In contrast, fast control loops for current, voltage or position may require per-channel rates in the tens of kilohertz with limited latency. In these cases the number of channels sharing the core must be restricted, oversampling factors must be modest, and scan scheduling must ensure that critical channels receive more frequent service than slow housekeeping channels. If the required per-channel rate or phase alignment exceeds what a single MUXed SAR can deliver, simultaneous-sampling or multi-core ADC architectures become more appropriate.

Channel scheduling provides a way to allocate conversion bandwidth according to priority. A typical strategy groups fast channels into a subset that is scanned every cycle, while slower channels are visited only every few cycles. This effectively increases f_CH for critical inputs at the expense of less frequent updates on non-critical ones. Simple numeric planning—starting from f_ADC, the number of channels in each group and the desired oversampling factors—helps verify whether a proposed schedule meets both throughput and latency requirements before hardware and firmware are fixed.

Calibration, diagnostics & robustness

A MUXed SAR ADC shares one conversion core across many channels, but each channel carries its own front-end and parasitics. Small differences in series resistors, protection networks and internal multiplexer paths create channel-to-channel gain and offset mismatches. Over temperature and time, these mismatches can drift further, undermining the assumption that readings from different channels are directly comparable. A structured calibration and diagnostics strategy is therefore essential to keep a channel set accurate and robust throughout its lifetime.

Per-channel gain and offset calibration for a multiplexed ADC typically starts from a small set of known reference points. By steering each channel to a known low point (ground or an internal ground reference) and to a known high point (VREF or an internal reference voltage), the system can measure two codes per channel and derive a simple linear correction. Many MUXed SAR converters provide internal shorting options to GND, VREF or internal channels, allowing this process to run without external relays or jumpers. The resulting per-channel scale and offset factors are stored in non-volatile memory and applied in firmware so that each raw code is converted to a calibrated engineering value before use.

Diagnostics build on the same infrastructure. Open-circuit detection can rely on biasing networks that pull a disconnected input to a recognisable level, combined with threshold and timing checks on the calibrated value. Short-circuit or overload conditions often drive the input toward rail voltages and can be detected when a channel remains pinned near its limits despite normal system operation. When internal short-to-GND or short-to-VREF modes are available, the ADC can perform sanity checks on each channel by temporarily switching away from the external sensor and confirming that the measured codes match the expected internal levels within a narrow tolerance window. Simple diagnostic flags such as open, short and out-of-range become part of the regular conversion pipeline.

Temperature drift and long-term ageing affect the ADC core, reference, resistors, buffers and sensor interfaces. Static, production-time calibration may not be sufficient for systems with tight accuracy requirements over wide temperature ranges. Robust designs schedule periodic background calibration sequences that remeasure internal GND and reference points and update channel coefficients when the board temperature or operating conditions change. Calibration data is versioned and checked for integrity, and firmware applies both gain/offset corrections and diagnostic flags consistently so that higher-level functions can react to degraded channels without compromising the entire MUXed SAR subsystem.

Application patterns for MUXed SAR ADC

MUXed SAR ADCs are most effective in systems that combine many channels, modest per-channel bandwidth and relaxed synchronisation requirements. A single SAR core and integrated multiplexer can service tens of inputs when each signal changes slowly relative to the available conversion rate. This architecture is attractive wherever board space, power and cost constraints favour one converter with channel sequencing over multiple dedicated ADCs or simultaneous-sampling devices.

PLC and DCS analog input cards are classic examples. These boards accept many 4–20 mA or 0–10 V field signals, each representing a relatively slow process variable. Per-channel update rates in the tens of hertz are usually sufficient, but the card must handle 8, 16 or more channels in a compact, insulated form factor. A MUXed SAR ADC paired with appropriate protection and front-end scaling networks can digitise all channels with one core, reducing component count and simplifying calibration. Channel protection and galvanic isolation are critical in this environment, so the MUXed SAR device is typically combined with isolated front-ends and surge-hardened input stages described in dedicated isolation and PLC-oriented topics.

Multi-sensor condition monitoring nodes and environment or IoT hubs also align well with multiplexed ADCs. These systems often aggregate vibration envelopes, temperature, current, pressure and humidity readings across many locations. Each channel may require a different sampling rate, but very few channels need simultaneous sampling. A MUXed SAR ADC with appropriate front-end buffers can schedule fast channels more frequently and slow housekeeping channels less often, achieving an efficient balance between throughput and power. High-impedance or low-level sensors use buffered front-ends to protect against leakage and acquisition errors, while low-impedance sensors can be connected through simpler RC networks.

Battery stack monitoring provides another important pattern. Cell voltages change slowly, so a MUXed SAR ADC can poll dozens of cells at moderate conversion rates and still meet the requirements of balancing and health monitoring algorithms. The main challenges shift from bandwidth to common-mode voltage range, isolation and functional safety, which are handled by dedicated BMS front-ends and protection devices. In such systems the multiplexed SAR core remains a good fit for the underlying acquisition pattern: many channels, relatively slow signals and strong pressure on board area and cost. Across PLC input modules, multi-sensor nodes, battery monitors and similar designs, careful matching of MUXed SAR capabilities to channel count, bandwidth and protection needs yields compact and efficient data acquisition solutions.

BOM & IC selection checklist for MUXed SAR ADCs

This section turns the previous architecture, timing, error, and front-end discussions into a practical datasheet checklist for MUXed SAR ADCs. Use it to drive parametric search and to sanity-check candidate parts before you commit them into your BOM.

1. Start from application requirements and back-solve ADC specs

Before looking at part numbers, lock down the system-level requirements that a MUXed SAR ADC must satisfy:

• Channel count N now, plus realistic expansion margin (for “spare” inputs).
• Required per-channel effective sampling rate f_CH,eff after multiplexing, averaging, and scheduling.
• Target system accuracy: required ENOB / SNR / THD / INL at the signal bandwidth of interest.
• Signal type and typical source impedance: low-ohmic shunts vs high-Z sensors (NTC, pH, bridge, etc.).
• Common-mode and absolute input range (0–5 V, ±10 V with front-end, high-side measurements, etc.).
• Mechanical and environmental limits: temperature range, radiation/EMC class, package constraints.

2. SAR core specifications (resolution, linearity, dynamic range)

These parameters define whether the ADC core itself can reach the accuracy you need before system-level imperfections from the MUX and front-end are added:

• Resolution & ENOB: 12/14/16/18 bits vs effective ENOB at your input frequency.
• SNR / SINAD / THD / SFDR at typical test frequencies (often 1 kHz or tens of kHz).
• INL / DNL limits and “no missing codes” guarantee.
• Noise floor: input-referred rms noise and 0.1–10 Hz noise if you care about drift.
• Reference architecture: on-chip reference vs external; reference input range and load.
• Power vs bandwidth: total current at your intended output data rate and resolution.

3. MUX-related parameters (what really matters for multiplexed sensors)

For MUXed SAR devices, the internal analog switch network sets the true limits on channel-to-channel performance and front-end design:

• Number of channels and input topology (single-ended, pseudo-differential, fully differential).
• On-resistance R_ON and its variation with voltage/temperature.
• Channel-to-channel crosstalk / isolation in dB across the bandwidth of interest.
• Input leakage current per channel and across temperature (critical for high-Z sensors).
• Allowed source impedance for specified accuracy and acquisition time.
• Overvoltage handling and input clamp behavior (e.g., per-channel surge tolerance).
• Input common-mode range vs supply and reference; headroom for protection networks.
• Channel sequencing: built-in sequencer, per-channel averaging, alert thresholds.

4. Timing, throughput and digital interface

Timing numbers in the datasheet must be reconciled with your channel scheduling model from the “throughput & latency” section:

• Maximum aggregate sampling rate f_S,ADC and guaranteed throughput at your resolution.
• t_ACQ (acquisition time) and t_CONV (conversion time) versus your RC front-end.
• Pipeline / group delay and any digital filtering latency.
• Interface type: SPI, LVDS, parallel, JESD-like serial, I 2 C for low-end parts.
• Maximum SCLK or interface clock and timing margins at your MCU/FPGA speed.
• Supply domains: separate analog/digital rails, I/O level compatibility, power-up sequencing.

5. System hooks, diagnostics and robustness

These features do not change raw ENOB, but strongly affect field reliability and debug effort:

• Internal test channels: short to GND/VREF, internal temperature sensor, reference nodes.
• Built-in self test, out-of-range flags, CRC on configuration or data words.
• Alert/interrupt pins for threshold crossings and watchdog events.
• ESD rating, input surge capability, latch-up immunity, radiation tolerance if relevant.
• Operating temperature range (industrial, automotive, aerospace-grade) and derating curves.

6. Quick BOM checklist for a MUXed SAR ADC

• Core specs: resolution / ENOB, SNR / THD, INL / DNL, noise, reference scheme.
• MUX network: channel count, R_ON, leakage, crosstalk/isolation, allowed source impedance, input range.
• Timing: max f_S,ADC, t_ACQ, t_CONV, pipeline delay, achievable f_CH,eff for your N and schedule.
• Digital interface: bus type, max clock, voltage levels, data framing, available modes (burst, sequencer).
• System hooks: calibration channels, diagnostics, watchdog/alerts, self-test options.
• Robustness: temperature range, ESD/EMC, radiation/ASIL class (if required), long-term availability.

7. Example MUXed / multi-channel SAR ADC part numbers

The table below lists representative multi-channel SAR ADCs with internal multiplexers from seven major vendors. They cover a range of resolutions, speeds and robustness levels; use them as concrete anchors when reading datasheets and building your own shortlist.

These devices span low-cost PLC inputs, precision instrumentation and space-grade designs. For your own BOM, focus first on the parameter groups above; then pick 2–3 candidate parts per vendor and run a detailed trade-off against front-end topology, layout constraints and lifetime availability.

Recommended topics you might also need

• SAR ADC (Successive Approximation)
• ADC with PGA
• Shunt/Bridge Front-Ends
• SPI/I²C (SAR/ΣΔ)
• Driver & Anti-Alias Filter
• Calibration & Self-Test

MUXed SAR ADC – Frequently Asked Questions

This FAQ consolidates common engineering questions around multiplexed SAR ADCs: when to choose them, how to size acquisition time and RC networks, how to deal with source impedance and crosstalk, and how to implement calibration, diagnostics and robust layouts.

1. Why use a MUXed SAR ADC instead of multiple single-channel ADCs? ▾

A MUXed SAR ADC typically reduces total cost, PCB area and power consumption when many slow or moderate-speed channels must be measured. One converter core and a built-in analog multiplexer often replace 4–32 separate single-channel ADCs, removing multiple references, drivers and digital interfaces from the BOM.

The trade-off is timing: channels are sampled sequentially instead of simultaneously. For process variables, housekeeping voltages and other signals with bandwidths in the Hz to low-kHz range, the extra scan latency (for example a few hundred microseconds to scan 16 channels at 1 MSPS) is usually acceptable. For systems that require tight phase alignment between channels, such as multi-phase current control or vibration analysis, multiple single-channel ADCs or a simultaneous-sampling / MxADC architecture is generally more appropriate.

2. How do I calculate the minimum acquisition time for each channel? ▾

Minimum acquisition time t_ACQ,min is set by the RC network seen by the internal sampling capacitor. The effective resistance is the sum of the source impedance, protection resistors and MUX on-resistance:

R_total = R_SRC + R_PROT + R_ON,MUX

For an N-bit SAR ADC, a common rule is to allow the sampling capacitor to settle within about 0.5 LSB of the final value. This leads to an acquisition time requirement approximately given by:

t_ACQ,min ≈ R_total × C_S × ln(2^N)

As a numeric example, assume a 16-bit converter, sampling capacitor C_S = 30 pF and total resistance R_total = 5 kΩ. Then:

ln(2¹⁶) ≈ 11.1   →   t_ACQ,min ≈ 5 kΩ × 30 pF × 11.1 ≈ 1.66 µs

In practice, acquisition time is often set with margin above this value, especially at high temperature or when external RC filters add extra capacitance. If the datasheet provides recommended maximum source impedance versus sampling rate, that curve should take precedence over rough calculations.

3. How does source impedance affect accuracy in a multiplexed SAR ADC? ▾

Source impedance affects accuracy in three main ways:

• Settling error: a higher source impedance increases R_total, slowing the charging of the sampling capacitor and increasing residual error at the end of t_ACQ.
• Static error due to leakage: with high-impedance sensors, the combination of input leakage, MUX leakage and ESD structures can generate microampere-level currents that translate into millivolt-level errors.
• Noise susceptibility: high-impedance nodes are more sensitive to capacitive coupling from digital lines and neighbouring channels, increasing effective noise and crosstalk.

As a guideline, if the effective source impedance exceeds the datasheet’s recommended limit for a given resolution and sampling rate, either the acquisition time must be increased, the sampling rate reduced, or a buffer amplifier should be inserted. For example, if a vendor recommends R_SRC,max ≤ 1 kΩ at 500 ksps and the actual source impedance is 10 kΩ, the system should not run at the full conversion rate without buffering or longer acquisition time.

4. What causes channel-to-channel crosstalk and how can it be reduced? ▾

Channel-to-channel crosstalk arises from parasitic capacitances inside the MUX, shared internal routing, package coupling and PCB-level coupling between input traces. Fast, large-amplitude transitions on one channel can couple into adjacent channels and appear as small steps or glitches on their sampled values.

Crosstalk is often specified in dB. For example, −80 dB crosstalk on a 10 V full-scale means approximately 1 mV of coupled error (10 V × 10^−80/20). For a 16-bit, 10 V-range ADC, 1 LSB is about 153 µV, so 1 mV corresponds to roughly 6–7 LSB.

To reduce crosstalk, good practice includes: grouping noisy and quiet channels apart in the pinout, routing sensitive inputs with clearances and guard traces, using differential signalling where possible, avoiding long parallel runs with digital clocks, and applying modest RC filtering at each input. For demanding applications, the datasheet crosstalk specification and typical test conditions should be reviewed against the required accuracy in LSBs.

5. How should RC filters be sized for each channel in a multiplexed front-end? ▾

RC filters in front of a MUXed SAR ADC must balance bandwidth control, noise reduction and acquisition time. A practical sizing flow is:

1. Define the required signal bandwidth f_SIG for each channel.
2. Choose the RC cutoff f_C in the range 3–10 × f_SIG, so that the passband is flat while higher-frequency noise and aliasing are attenuated.
3. Check that the resulting R value, combined with MUX R_ON and protection resistors, keeps R_total within the datasheet’s recommended source impedance at the intended sampling rate.
4. Verify that the acquisition time t_ACQ satisfies the RC settling requirement for the target resolution.

As an example, for a 1 kHz sensor channel, a single-pole RC with f_C around 5–10 kHz is often sufficient. With C = 1 nF and f_C = 8 kHz, R ≈ 1 / (2π f_C C) ≈ 20 kΩ. If the ADC datasheet recommends a maximum source impedance of 5 kΩ at the desired throughput, the filter should be adjusted to a lower R and higher C, or an op-amp buffer should be used.

6. How many channels can be realistically scanned at X kSPS with N-bit resolution? ▾

For a MUXed SAR ADC, the effective per-channel sampling rate depends on the aggregate conversion rate, the number of channels and any oversampling or averaging. A first-order estimate is:

f_CH,eff ≈ f_S,ADC / (N_CH × M)

where f_S,ADC is the total sample rate of the ADC core, N_CH is the number of channels, and M is the number of samples per channel used for averaging. Interface time and firmware overhead must also be accounted for.

As an example, with f_S,ADC = 1 MSPS, N_CH = 16 and no averaging (M = 1), f_CH,eff is roughly 62.5 ksps per channel. If each channel is averaged over M = 4 samples, the effective channel update rate drops to about 15.6 ksps. This simple estimate must then be checked against the required t_ACQ, conversion time, SPI clock frequency and any dead time between scans.

7. Do high-impedance sensors need an op amp buffer before the MUX? ▾

High-impedance sensors usually benefit from buffering before a MUXed SAR ADC. As a rule of thumb, if the sensor output impedance is more than a few kilohms at the intended throughput, or if datasheet guidance indicates a maximum source impedance that the sensor cannot meet, a buffer amplifier should be considered.

For example, a pH probe or electrochemical sensor can have source impedances in the 100 kΩ to megaohm range. Without buffering, a typical input leakage of a few tens of nA can create errors on the order of tens of millivolts, and the sampling capacitor may not settle within one acquisition window. A unity-gain buffer or instrumentation amplifier with low input bias current and adequate bandwidth isolates the sensor from the MUX and allows the ADC to operate close to its specified performance.

For low-impedance sources such as shunt resistors or conditioned 0–10 V signals with output impedance below 100 Ω, a direct connection through modest protection and RC filtering is often sufficient, provided that t_ACQ and crosstalk requirements are satisfied.

8. How can per-channel gain and offset calibration be implemented in firmware? ▾

A simple two-point calibration per channel is often sufficient for many MUXed SAR applications:

1. Measure each channel at a known low reference, typically ground or an internal GND node, to obtain Code_GND,i.
2. Measure each channel at a known high reference, for example VREF or a stable internal reference near full scale, to obtain Code_REF,i.
3. Solve for per-channel gain and offset coefficients a_i, b_i such that V = a_i × Code + b_i reproduces the known reference voltages.
4. Store these coefficients in non-volatile memory with versioning and integrity checks, and apply them to all subsequent measurements on channel i.

When an ADC provides internal short-to-GND or short-to-VREF modes, these internal points can be reused periodically in the field to refresh calibration and compensate for temperature and ageing effects, without external jumpers or relays.

9. How can open- and short-circuit faults be detected on MUXed SAR channels? ▾

Fault detection combines simple hardware biasing with firmware thresholds and timing rules:

• Open circuits: adding weak pull-up or pull-down resistors at the input causes a disconnected sensor to drift toward a known voltage. If a channel remains at this bias level for many consecutive samples while normal operation would vary, the firmware can flag an open-circuit condition.
• Short circuits or overloads: persistent readings near the supply rails, combined with appropriate time and amplitude thresholds, indicate possible shorts or heavy overvoltage events.
• Internal self-check: when the ADC supports internal short-to-GND or short-to-VREF modes, temporarily steering a channel away from its external sensor and verifying that measured codes match expected internal levels provides a further check on wiring and front-end integrity.

Diagnostic logic typically combines a voltage range window, a minimum duration (for example several scan cycles) and system context, so that transient events do not immediately trigger permanent fault states.

10. What layout practices help reduce crosstalk and settling issues? ▾

PCB layout has a strong impact on MUXed SAR performance. Helpful practices include:

• Keep analog and digital return paths separated and join them at a well-defined point near the ADC.
• Place the ADC, reference, and any input buffers close together to minimise loop areas and trace lengths.
• Route sensitive input traces away from fast digital clocks and data lines; avoid long parallel runs.
• Use ground guard traces or shielding around high-impedance and high-accuracy channels.
• Group high-swing, noisy channels physically away from low-level precision channels in the pinout and on the PCB.
• Keep the RC network and protection components close to the ADC pins to control parasitics and settling.

These measures help maintain predictable acquisition time, reduce parasitic coupling and allow the MUXed SAR ADC to meet its specified linearity and noise performance in the final system.

11. When is a simultaneous-sampling / MxADC architecture better than a MUXed SAR? ▾

A simultaneous-sampling or MxADC architecture is preferred whenever relative timing between channels is critical. Typical examples include multi-phase current and voltage feedback in motor drives, power converters and grid-tied inverters, as well as vibration and acoustic systems that need coherent sampling across axes.

In such applications, the allowed channel-to-channel sampling skew may be limited to tens of nanoseconds or a small fraction of a switching period. A MUXed SAR ADC, which samples channels sequentially, introduces inter-channel delays on the order of one conversion period per step, which can be microseconds at moderate speeds. This delay is acceptable for many monitoring tasks but not for tight control loops or precise phase-sensitive measurements.

Simultaneous-sampling architectures use multiple ADC cores or sample-and-hold stages in parallel to capture all channels at the same instant, at the cost of higher silicon area, power and often more complex digital interfaces.

12. How should crosstalk and leakage specifications be interpreted in the ADC datasheet? ▾

Crosstalk is usually specified as a ratio in dB between a large signal on one channel and the coupled signal seen on another channel, at a given test frequency. To convert this to a voltage error, multiply full-scale by 10^−CT/20. For example, with 10 V full-scale and −90 dB crosstalk, the coupled signal is roughly 316 µV, or about 2 LSB for a 16-bit converter.

Leakage is often given as input or channel leakage current, both typical and maximum, over temperature. In a 1 MΩ sensor, a 50 nA leakage current creates a 50 mV error, which is significant in many systems. For high-impedance sensors, leakage must therefore be treated as a primary error term, not a secondary effect.

When reviewing datasheets, it is important to pay attention to worst-case values and test conditions, including temperature, common-mode voltage and channel state. Interpreting crosstalk and leakage in terms of equivalent LSBs and percentage of full-scale helps determine whether a particular MUXed SAR ADC is suitable for the desired accuracy targets.