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Spread-Spectrum Clocking (SSC) for Peak EMI Reduction

Spread-Spectrum Clocking (SSC) for Peak EMI Reduction

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Spread-Spectrum Clocking (SSC) reduces peak EMI by applying controlled frequency modulation to a clock so its energy is spread across a wider band—without “removing” total energy. The practical trade-off is clear: more EMI peak reduction consumes more endpoint frequency/tracking margin, so SSC must be tuned (depth/rate/profile) and validated against link stability and tolerance.

Definition & scope: what SSC changes (and what it doesn’t)

30-second TL;DR
  • SSC is controlled frequency modulation applied to a clock (commonly a triangular profile).
  • It reduces peak EMI by spreading spectral energy over a wider band — energy is redistributed, not removed.
  • Peak reduction trades against endpoint frequency tolerance and tracking margin (PLL/CDR must follow the modulation).
In-scope (this page)
  • Why peak EMI drops with SSC (engineering intuition, not heavy math).
  • How down-spread / depth / rate consume endpoint margin.
  • What “good” looks like: peak ↓ with no new lock/BER failures.
Out-of-scope (link to sibling pages)
  • Full EMC “encyclopedia” and chamber procedures beyond SSC validation.
  • PLL loop theory / stability derivations (see PLL & jitter-cleaning pages).
  • Deep phase-noise/jitter math and integration-window theory (see the Phase Noise & Jitter page).
What SSC changes vs. what it does NOT change
SSC changes Does NOT change
  • Peak EMI at narrow RBW detectors can drop (energy spreads).
  • Clock instantaneous frequency sweeps within a defined range (depth).
  • Endpoints see a slow frequency wander that must be tracked.
  • Total energy is redistributed; average power may look similar.
  • SSC is not a substitute for return-path and termination hygiene.
  • SSC does not guarantee lower random jitter (metrics can appear worse if mis-measured).
Verification hook: compare peak-hold spectra (SSC off/on) and confirm endpoint stability. Pass criteria: peak reduction without new lock/BER/training regressions under corners.
Practical “pass” definition (keep it testable)
  • EMI goal met: the target peak(s) in the problem band visibly drop when SSC is enabled (same measurement settings).
  • Endpoint margin preserved: no new loss-of-lock, retraining, audio clicks, CRC/packet errors, or BER spikes across temperature/voltage corners.
  • Reproducible behavior: the SSC profile (mode/depth/rate) is identifiable, logged, and repeatable in production.
Diagram: peak reduction by spreading clock energy (conceptual)
SSC spectrum concept: narrow peaks vs spread energy A conceptual comparison showing a narrow spectral peak without SSC and a widened lower-amplitude band with down-spread SSC, illustrating peak EMI reduction by energy spreading. Before (SSC OFF) After (SSC ON) frequency amplitude Peak frequency amplitude Energy spread Peak ↓ Down-spread Conceptual view: SSC redistributes energy; verify peak and endpoint margin together.

Where SSC sits in the clock tree (source → synth → distribution → endpoints)

Architecture rule (prevents cross-domain regressions)
  1. Enable SSC only in domains that need peak-EMI reduction and whose endpoints tolerate frequency modulation.
  2. Assume any re-timing or narrow-band jitter-cleaning stage may attenuate or reshape SSC; confirm by measurement, not assumptions.
  3. Maintain a No-SSC domain for sensitive clocks (tight tolerance / deterministic phase / ultra-low jitter), isolated by the clock tree.
Clock-tree stages: where SSC can be injected and what to watch
Clock tree stage Can inject SSC? Pros Typical pitfalls (symptoms)
Source (XO / MEMS) Often yes Simple platform integration; minimal configuration complexity. SSC affects all downstream consumers unless domains are separated; endpoints that cannot disable SSC may fail intermittently.
Synth (PLL output) Common Flexible per-output control; profile/depth/rate can be SKU-specific. New narrow spurs can appear; certain modulation rates can expose measurement artifacts or endpoint tracking limits.
Jitter cleaner / attenuator Use caution Can isolate noisy references and stabilize downstream jitter profiles. SSC can be attenuated or reshaped (EMI improvement disappears); endpoints may see a different profile than expected.
Distribution (fanout / mux / crosspoint) Mostly pass-through Multi-domain routing and redundancy; per-branch enable/disable strategies. Retiming or poor termination can turn spread energy into unpredictable peaks; domain mixing causes “works on one board only” failures.
“Must-disable SSC” domains (use feature-based screening)
  • Deterministic phase / tight alignment requirements (phase window is part of the spec).
  • Ultra-low jitter sampling chains where the jitter budget is already near the limit.
  • Endpoints with narrow frequency tolerance or weak tracking (intermittent lock/training failures appear at corners).
Implementation note: keep SSC and No-SSC clocks as separate domains in the tree; avoid sharing buffers unless verified.
Diagram: SSC domain planning in a layered clock tree
Clock tree placement for SSC with SSC and No-SSC domains A layered clock tree showing source, PLL with SSC injection, optional jitter cleaner, and fanout splitting into SSC ON and SSC OFF domains feeding different endpoint classes. Source XO / MEMS Synth PLL output SSC inject Cleaner optional May attenuate SSC Fanout split domains SSC OFF Sensitive endpoints ADC / timing / align SSC ON Platform endpoints board / storage / ref Design intent: separate SSC and No-SSC domains; validate by EMI + endpoint lock/BER.

Mechanism: down-spread vs center-spread, modulation profile, and why EMI peak drops

What matters in practice
  • Peak EMI drops because clock energy is spread across a wider band (the analyzer’s narrow RBW captures less energy at any single point).
  • Down-spread is commonly preferred to reduce the risk of exceeding the upper-frequency tolerance of endpoints and masks.
  • Profile controls how “structured” the spread looks: triangle can show more visible sideband structure, while dither can look more noise-like.
Why “peak” drops (engineering intuition, SSC-specific)
  • Without SSC, energy is concentrated near a single carrier frequency, producing tall, narrow spectral peaks.
  • With SSC, the carrier moves within a defined range, so energy that used to sit at one frequency is distributed over many nearby frequencies.
  • As a result, the peak detector in a narrow measurement window often reports a lower maximum value—while average/total energy is largely redistributed rather than removed.
Boundary note: instrument settings strongly influence “how much” peak appears to drop; detailed measurement traps are handled in the Verification & Measurement chapter.
Down-spread, center-spread, and profile: what changes on the board
Spread mode defines where the swept band sits relative to the nominal clock. Down-spread shifts the center downward, which often reduces the chance of violating upper-frequency limits. Center-spread expands both up and down, which can improve peak reduction in some cases but consumes tolerance on both sides.

Modulation profile defines whether the spread looks more deterministic (triangle) or more noise-like (dither). This affects the visibility of narrow sideband structure (“comb-like” spurs) and how robust the peak reduction appears across different measurement windows.
Selection table: mode and profile (SSC-specific trade-offs)
Mode / profile Benefit Risk (symptoms) When to choose
Down-spread Peak reduction while lowering the chance of overshooting the upper-frequency limit. Can still consume endpoint tolerance; intermittent lock/training issues can appear at corners if margin is tight. Default choice for platform/board clocks and many interface refclks where SSC is permitted.
Center-spread Can provide strong peak reduction by distributing energy on both sides of nominal. Consumes tolerance on both sides; compatibility is more sensitive; failures may look like “only some boards” or “only cold start”. Consider only when endpoints and masks are clearly specified to tolerate the full spread range.
Triangle profile Predictable, easy to reason about; common implementation for down-spread. Narrow sideband/“comb” structure can become visible; a new spur may stand out even when average peak improves. Start here for debug-friendly rollouts; revisit if discrete spurs become the limiting issue.
Dither / pseudo-random Energy distribution can look more “noise-like,” often reducing the prominence of discrete sideband structure. Peak results can look inconsistent if measurement settings change; endpoint margin must still be verified across corners. Evaluate when a single visible spur is the compliance limiter or when triangle shows an objectionable comb.
Pass criteria (mechanism-level)
  • Peak reduced at the targeted problem frequencies with SSC enabled (same analyzer setup).
  • No new dominant narrow spur becomes the top peak (if it does, profile/rate/implementation must be revisited).
  • Endpoint behavior unchanged (no new lock loss, retraining, BER spikes, CRC bursts) across voltage/temperature corners.
Diagram: time-domain modulation and spectrum appearance (conceptual)
SSC mechanism: down-spread vs center-spread and profile effects Top panels show triangular frequency modulation over time for down-spread and center-spread with depth and rate annotations. Bottom panels show conceptual spectrum: SSC off narrow peak, triangle SSC comb-like spread, and dither SSC smoother spread. Time domain: f(t) Frequency domain (concept) Down-spread time freq Depth Rate Center-spread time freq Depth SSC OFF Peak Triangle SSC Comb-like Dither SSC Smoother Conceptual only: verify peak reduction and endpoint margin together.

Key knobs: spread depth, modulation rate, and “effective jitter” seen by endpoints

Core trade-off (always validate both sides)
  • Depth widens the spread band: higher potential peak reduction, higher frequency-tolerance consumption.
  • Rate shapes how energy is distributed in the spectrum and how hard endpoints must track the modulation.
  • Endpoints experience a combination of slow frequency wander and phase perturbation, which reduces tracking margin.
What each knob really controls
Spread depth (%) sets the maximum frequency deviation. It is the most direct control for peak reduction, but it also directly consumes endpoint tolerance. If endpoint tracking is marginal, failures often appear first at temperature/voltage corners, not on a comfortable bench setup.

Modulation rate (kHz) determines how fast the clock sweeps. It changes the “shape” of the spread in the frequency domain and can expose weak tracking behavior (e.g., lock becomes intermittent, training retries increase). Rate can also change how stable the measured peak appears across analyzer settings.

Profile (triangle vs dither) influences how “structured” the spread looks. If a single visible spur becomes dominant, profile and rate are typical first levers—without jumping into PLL math.
Boundary note: random-jitter and phase-noise budgeting belongs to the Phase Noise & Jitter page; SSC here focuses on depth/rate/profile and endpoint margin behavior.
Knob-to-outcome mapping (fast decision table)
Knob Increases EMI benefit? Increases compatibility risk? Quick rule-of-thumb
Depth (%) Usually yes Usually yes Start conservative, increase in small steps, and validate endpoints at corners after each step.
Rate (kHz) Depends Depends Fix depth first; sweep rate to find a stable peak reduction with the most robust lock/training behavior.
Profile (triangle/dither) Similar Similar If a new narrow spur becomes dominant, evaluate profile + rate changes before redesigning the clock tree.
“Effective jitter” as seen by endpoints (SSC framing)
  • SSC appears as a low-frequency wander plus phase perturbation that the endpoint PLL/CDR must track.
  • If margin is tight, failures tend to be intermittent: sporadic retraining, rare lock drops, or bursty BER under corners.
  • Therefore, “EMI peak ↓” is not sufficient; endpoint robustness must be validated alongside the EMI result.
Diagram: knobs drive a two-sided outcome (peak EMI vs endpoint margin)
SSC knobs: depth, rate, profile and trade-off between EMI peak and endpoint margin A control panel with three sliders labeled Depth, Rate, and Profile feeds two outcome cards: Peak EMI down and Endpoint margin down, highlighting the trade-off. SSC Controls Depth Rate Profile Triangle Dither Tune one knob at a time Trade-off Outcome A Peak EMI ↓ spread energy Outcome B Endpoint margin ↓ track wander Lock/BER stability is the margin indicator; peak-only wins are incomplete.

Compatibility map: who usually tolerates SSC and who often doesn’t

Quick takeaways
  • SSC tolerance is primarily about tracking capability (PLL/CDR) and frequency tolerance window (ppm margin).
  • Many platform/interface reference clocks often allow SSC, while precision sampling and deterministic timing chains are often sensitive.
  • When a clock is re-generated (PLL/cleaner/retimer), SSC can be altered or removed; compatibility becomes implementation-dependent.
3-step screening (no spec deep-dive)
  1. Tracking present? Does the endpoint rely on a PLL/CDR that can track slow frequency wander?
  2. ppm window available? Is there clear tolerance margin for the full spread range under voltage/temperature corners?
  3. Deterministic phase required? Is deterministic phase alignment or strict synchronization a requirement of the chain?
Interpretation rule: “No” on tracking or tolerance usually means SSC should be off by default; deterministic phase requirements increase risk and require explicit validation.
Risk symptoms (what failures look like)
  • Intermittent lock loss or increased retraining events.
  • Bursty errors (BER/CRC bursts) rather than a constant degradation.
  • Longer bring-up time or failures concentrated in cold start / hot corners.
  • Board-to-board variability (margin consumption exposed by process and routing differences).
Core table: endpoint class → typical SSC tolerance → symptom → preferred action
Endpoint class SSC tolerance (typical) Risk symptom Preferred action
Platform / board clocks Usually tolerates Rare issues unless ppm windows are tight or the tree is noisy. Prefer down-spread; start conservative depth; validate corners and freeze.
Interface reference clocks (PC / storage class) Often tolerates Training retries, occasional link-up variability when margin is consumed. Use down-spread; keep depth modest; validate with stress and corner sweeps.
High-speed SerDes domains (CDR-based) Depends on implementation Bursty BER/CRC, intermittent retraining, “works on bench, fails in system”. Confirm whether SSC survives through any regeneration; validate with worst-case patterns and corners.
Precision sampling chains (ADC/DAC/RF clocks) Often sensitive Performance spread, spur surprises, alignment failures, corner regressions. Default SSC OFF; enable only with explicit proof and tight endpoint validation.
Deterministic sync / timing domains Often sensitive Phase alignment drift, deterministic-latency assumptions break, sporadic sync alarms. Default SSC OFF; if needed, validate deterministic phase requirements explicitly.
Cleaned / re-timed / re-generated clocks Depends on implementation EMI improves but endpoint issues persist (SSC may be altered/removed); “inconsistent” results between branches. Identify the injection point; verify SSC presence at endpoints before tuning parameters.
Diagram: compatibility matrix (endpoint class vs depth/rate buckets)
SSC compatibility matrix by endpoint class and depth/rate buckets Matrix rows are endpoint classes. Columns are SSC buckets combining depth and rate. Cells show icons: check for usually OK, exclamation for verify, and stop for often sensitive. Legend ✓ Usually OK ! Verify ⛔ Often sensitive Columns: Depth (L/M/H) × Rate (L/H) D-L / R-L D-L / R-H D-M / R-L D-M / R-H D-H / R-L D-H / R-H Platform Interface refclk SerDes domains Sampling clocks Sync/Timing Cleaned clocks ✓ ✓ ✓ ! ! ⛔ ✓ ✓ ! ! ⛔ ⛔ ! ! ! ! ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ⛔ ! ! ! ! ! ! Typical guidance only: the pass/fail boundary depends on endpoint tracking and ppm window margin.

Practical selection workflow: choose down-spread depth & rate to hit EMI target with margin

The workflow that avoids “peak-only wins”
  • Start from an EMI target peak (frequency band + offending line), not from a random SSC setting.
  • Choose down-spread first, then sweep depth, then sweep rate—one knob at a time.
  • Every step must pass both: EMI peak ↓ and endpoint stability (lock/training/BER/CRC) across corners.
Why the order matters (mode → depth → rate)
Mode is selected first to manage tolerance risk; down-spread is typically preferred because it reduces the likelihood of exceeding the upper-frequency side of endpoint limits. Depth is the main lever that trades peak reduction against ppm margin consumption; it should be swept conservatively and validated at corners. Rate shapes spectral distribution and can expose tracking weaknesses; sweep rate only after a stable depth window is found.
Step table (change one variable; measure two outcomes)
Step What you change What you measure Pass criteria
0) Set goal Identify the offending peak and band; capture SSC-OFF baseline. Peak level at target frequencies; endpoint stability baseline. Repeatable baseline; endpoints stable across corners before SSC tuning.
1) Choose mode Prefer down-spread; use center-spread only when tolerance is clearly available. EMI peak direction; any immediate endpoint regressions. No new endpoint symptoms; EMI impact is directionally beneficial.
2) Sweep depth Increase in small steps from conservative to target; change only depth. Target peak reduction + endpoint lock/training/BER/CRC indicators. Peak reduction achieved without intermittent endpoint failures at corners.
3) Sweep rate Keep depth fixed; sweep rate to avoid unstable peak readings or endpoint-sensitive behavior. Peak stability across repeats + endpoint robustness across corners. Choose the window with stable EMI gain and the fewest endpoint symptoms.
4) Freeze + guardband Freeze mode/depth/rate/profile; add guardband for corners and variability. Re-run EMI and endpoint tests across corner sweeps and system modes. Repeatable pass with configuration recorded for production and field reproduction.
Diagram: end-to-end workflow (goal → sweep → validate → freeze)
SSC parameter selection workflow for EMI target and endpoint margin A vertical flowchart: Set goal, choose mode, sweep depth, sweep rate, validate endpoints, and freeze with guardband. Decision points show pass/fail loops. Set goal Identify offending peak + band Choose mode Prefer down-spread Sweep depth Small steps, check EMI + endpoints Endpoints stable? Yes No Sweep rate Find stable EMI gain with robust tracking Freeze + guardband Record config for production and field repro Measures EMI Lock BER

Implementation patterns: SSC from oscillator vs SSC in PLL vs platform-controlled SSC

What changes across patterns
  • Oscillator SSC: simplest integration and platform-friendly, but tuning options are limited to what the oscillator provides.
  • PLL SSC: flexible depth/rate/profile and multi-frequency support, but discrete sidebands and interaction with synthesis can become more visible.
  • Platform-controlled SSC: enables SKU/region/EMI-mode differentiation and field rollback, but switching policy and configuration traceability must be designed in.
Control plane and traceability
Treat SSC as a configurable system feature rather than a single register bit. Define where the SSC policy lives (strap/EEPROM/software), how configuration is versioned, and how the active mode is observable in production and field logs.
Switching policy (safe enable/disable)
  • Power-up default: choose SSC default ON/OFF based on the most sensitive endpoints and certification needs.
  • Runtime switching: define whether switching is allowed while links are active; if not, gate changes behind retraining windows.
  • Branch scoping: enable SSC only where needed; keep sensitive branches permanently SSC-OFF by design.
  • Rollback path: prioritize rollback order (disable SSC → reduce depth → change rate/profile) for fast recovery from marginal failures.
Pattern comparison (architecture decision asset)
Pattern Best for Typical pitfalls Test focus
Oscillator SSC (XO/MEMS with SSC) Simple platforms, single-mode systems, quick EMI peak reduction with minimal clock-tree complexity. Limited tuning choices; insufficient granularity when endpoints have tight margin; hard to align SSC policy across multiple branches. Confirm SSC presence at endpoints; validate corner stability; verify repeatability across boards and power cycles.
PLL SSC (SSC injected in synthesizer) Multi-frequency platforms, fine control of depth/rate/profile, centralized SSC policy in the clock generator. Discrete sidebands can become prominent; interactions with synthesis modes can create new spurs; some rates expose endpoint tracking weakness. Spur scan before/after enabling SSC; endpoint burst error checks; validate across temperature/voltage and training-heavy scenarios.
Platform-controlled SSC (strap/EEPROM/I²C policy) Multiple SKUs/regions, certification modes, field rollback, and branch-scoped SSC enable/disable. Unsafe switching (mid-link changes) causing retraining; configuration drift across firmware versions; unclear observability in field logs. Switching repeatability (many cycles); policy/version traceability; defined rollback triggers and recovery time.
Diagram: where SSC is generated and how it is controlled
SSC generation patterns across oscillator, PLL, and platform-controlled switching Three columns show topologies: oscillator with SSC into fanout, PLL with SSC into fanout, and platform-controlled glitch-free mux enabling SSC on/off per branch. Pattern A / B / C: SSC source + control plane + endpoints A) Oscillator SSC B) PLL SSC C) Platform-controlled XO / MEMS SSC inside Fanout Endpoints Branch-scoped ON/OFF Control: Pin / Strap XO PLL / Synth SSC injected Fanout Endpoints More tuning knobs Control: I²C/SPI regs XO PLL / Gen Glitch-free MUX SSC ON / OFF Endpoints Policy: EEPROM + I²C Limited tuning More knobs, more spurs SKU / mode switching

Design hooks & pitfalls: spurs, spectral regrowth, and “why my peak got worse”

What SSC can break (and how it shows up)
  • New discrete peaks can appear when modulation details create visible sidebands.
  • Board-to-board spread often points to layout/power coupling that converts benign modulation into a worse spectrum.
  • Intermittent lock/training failures usually indicate margin consumption at corners (temperature/voltage/cabling).
Root-cause buckets (keeps troubleshooting on scope)
Implementation
Profile/rate interactions, synthesis modes, and where SSC is injected or re-generated can create visible sidebands or move energy into sensitive regions.
Layout / Power
Return-path discontinuities and supply noise coupling can make buffers convert modulation into worse spectral artifacts (board-to-board variability is a strong signal).
Endpoint tracking
PLL/CDR tracking limits and tight ppm windows can turn SSC into intermittent failures under corner stress (temperature, voltage, cabling, training load).
Troubleshooting table: symptom → likely cause → quick check → fix → pass criteria
Symptom Likely cause Quick check Fix Pass criteria
New discrete peaks appear after enabling SSC Modulation rate/profile creates visible sidebands; implementation interactions make “spread” look more like lines than a smear. Sweep rate while keeping depth fixed; check if peaks move/spread with rate changes. Change profile or rate; reduce depth; consider moving SSC injection upstream/downstream. No new peaks that exceed the compliance margin; results repeat across multiple runs.
Target peak drops, but a nearby peak rises (“spectral regrowth”) Energy redistributed into a band that couples better to the board/cable/enclosure; layout/power paths dominate. Compare the “raised” band across different cable placements and chassis conditions; look for strong sensitivity. Improve return paths and shielding strategy; reduce supply coupling into buffers; then re-tune rate if needed. Overall peak set improves (no new exceedances) with stable behavior across mechanical setups.
EMI outcome varies widely between boards at the same SSC setting Return-path discontinuities and supply noise coupling create nonlinear conversion in buffers; small layout differences become large spectral differences. Correlate board spread with supply ripple/ground bounce and clock routing differences (length, reference plane continuity). Fix clock return continuity; strengthen local decoupling and isolation; reduce buffer supply injection paths. Board-to-board spread shrinks and stays bounded under the same test setup and corners.
Intermittent lock loss / retraining increases at corners SSC consumes ppm window; endpoint tracking hits limits under temperature/voltage/cable stress. Repeat tests at hot/cold and low/high supply; check if failures correlate with specific corners or training intensity. Reduce depth; adjust rate/profile; disable SSC on the sensitive branch; prioritize endpoint margin. Retraining/lock-loss rate returns to baseline across all defined corners.
EMI reduction is not repeatable (run-to-run drift) Configuration state is inconsistent (SSC not truly enabled/disabled), or measurement window interaction makes peak readings unstable. Verify active configuration state; repeat with identical setup and multiple captures; compare peak-hold vs average stability. Make SSC state observable and logged; choose a rate window that produces stable compliance results. Multiple repeats converge to a narrow result band with the same settings and corners.
SSC improves EMI but endpoint errors still occur (inconsistent branch behavior) SSC is altered or removed by re-generation in part of the tree; branches see different clock behavior. Identify whether SSC is present at the problematic endpoint; compare branches with and without regeneration/cleaning stages. Re-scope SSC enable to only the needed branches; adjust injection point; simplify regeneration path for consistency. Branches show consistent behavior; endpoint failures cease without sacrificing compliance.
Enabling SSC worsens certain peaks only under load/activity Activity-dependent power noise modulates buffers; coupling converts supply variations into spectral artifacts when SSC is present. Compare idle vs active EMI; correlate with supply noise measurements near the clock generator and fanout. Strengthen local supply isolation/decoupling; reduce shared return impedance; consider isolating fanout supply domains. Peaks remain controlled across operating modes and workload profiles.
Switching SSC ON/OFF causes transient failures or long recovery Switching policy is unsafe for active endpoints; timing of muxing or configuration changes forces retraining and exposes marginal conditions. Repeat switching cycles while monitoring link state counters; check whether failures occur only during switching events. Restrict switching to safe windows; use glitch-free switching; add explicit retraining sequence; keep sensitive branches fixed SSC-OFF. Switching is repeatable and bounded (no unexpected errors); recovery time is stable across corners.
Diagram: problem tree (symptom → root-cause bucket → example hooks)
SSC problem tree for worse peaks, new spurs, and unstable links Top symptoms branch into three root-cause buckets: implementation, layout/power, and endpoint tracking. Leaf nodes indicate typical hooks to investigate. Peak worse after SSC ON New spur discrete lines Link unstable retrain / drop Implementation profile / rate regen path Layout / Power return path supply coupling Endpoint tracking ppm window corner stress Check hooks rate sweep profile change injection point Fix hooks return continuity supply isolation buffer domain Endpoint hooks reduce depth rate window branch SSC OFF Use the table above: Quick check → Fix → Pass criteria, then freeze + guardband.

PCB & distribution specifics for SSC clocks (routing, fanout, terminations)

SSC-specific takeaway
  • SSC widens the occupied spectrum, so impedance discontinuities and reflections can turn “spread” into peak rebound or new discrete peaks.
  • Fanout/crosspoint blocks can add deterministic artifacts; judge by endpoint margin + measurement, not by headline jitter alone.
  • Routing rule (kept minimal): do not break return paths, avoid slots/splits, and keep differential references continuous.
Why SSC is more sensitive to reflections (engineering view)
SSC makes the clock behave like a signal that “visits” a wider set of frequencies over time. Any mismatch (termination placement, stubs, connectors, via transitions) can reinforce certain parts of that widened spectrum. The observed result is often not a smooth smear, but peak rebound, new lines, and run-to-run instability.
Distribution blocks: what to judge under SSC
  • Pass-through vs “shaped” SSC: some paths preserve SSC behavior; others reshape it (different artifact signatures at the endpoint).
  • Branch-to-branch consistency: different loads and routing can make the same SSC look different across branches.
  • Additive artifacts: deterministic components can become visible as discrete peaks after fanout/crosspoint stages.
Layout review table (SSC-focused)
Item Why SSC makes it worse What to do Quick check
Termination placement Reflections can re-concentrate spread energy into higher peaks or discrete lines. Place the termination at the intended receiver side per the selected signaling scheme; avoid “decorative” terminations in the middle of the link. Compare EMI and endpoint errors with termination enabled/disabled (or moved) while keeping SSC settings fixed.
Stubs (test points, branches, via stubs) A stub behaves like a frequency-selective reflector; SSC makes the “bad frequency” more likely to be visited. Minimize stubs; avoid long unused branches; use controlled test structures that do not create large discontinuities. If a small physical change (probe, clip lead, connector) produces large peak swings, suspect stubs and discontinuities first.
Connectors / cable launch Wider spectrum increases the chance of coupling to mechanical/cable resonances and imperfect launches. Keep launches symmetric, preserve return paths, and avoid abrupt geometry changes at connectors. Repeat measurements with consistent cable placement; if results drift with minor placement changes, focus on launch/return path.
Fanout / crosspoint additive artifacts Deterministic components can appear more visible after SSC, especially after buffering and re-shaping. Validate using endpoint pass/fail margin and spectrum comparisons across branches; avoid assuming “transparent” behavior. Compare branch spectra (same SSC source) before and after fanout/crosspoint; look for new discrete peaks.
Reference plane continuity (no splits/slots) Broken returns increase common-mode conversion; SSC makes compliance results less stable and more sensitive to setup changes. Keep a continuous reference plane under the clock path; avoid crossing plane splits; keep returns short and predictable. Near-field scan near split/slot crossings; if hotspots align with crossings, fix return continuity first.
Branch-to-branch consistency Small differences in loading and routing can amplify SSC sensitivity and produce branch-specific peaks and errors. Keep critical branches consistent; scope SSC only to the required branches; validate per-branch outcomes. Compare EMI peak and endpoint counters across branches under identical SSC settings and corners.
Diagram: reflections can turn “spread” into peak rebound
SSC clock routing, termination, fanout, and reflection-driven peak rebound A clock generator with SSC drives a fanout into a differential pair with termination. Stubs and plane splits are highlighted as reflection sources that can cause peak rebound or new peaks. SSC + discontinuities → reflections → peak rebound / new peaks Clock Gen SSC ON Fanout branching Diff Pair controlled Z Endpoint TERM Stub / Testpoint reflection source Wrong Term placement/value Plane Split return break Ideal (well-matched) lower peak, smoother spread With reflections peak rebound / new peaks

Verification & measurement: analyzer settings, peak/avg traps, and endpoint validation

Measurement rules that prevent wrong conclusions
  • Lock RBW / VBW / detector / trace mode / sweep time before comparing SSC OFF vs ON.
  • Use a two-phase workflow: locate hotspots (near-field) → quantify with fixed settings (A/B comparison).
  • Always validate endpoints in parallel: lock, training/retrain counters, and error counters for the relevant link type.
Phase 1 — Locate (find the coupling path)
Use a near-field probe to find where the clock couples into radiation (routing discontinuities, connectors, return breaks, fanout regions). The output is a ranked list of hotspots, not a compliance number.
Phase 2 — Quantify (A/B with fixed settings)
Freeze analyzer settings and compare SSC OFF vs ON at the same hotspots and geometry. Record the full settings and the SSC configuration state (mode/depth/rate/profile). Repeat runs to confirm stability.
Endpoint validation checklist (protocol-agnostic)
  • Lock: PLL lock status remains stable across corners.
  • Training / retraining: counters do not increase versus SSC-OFF baseline.
  • Error counters: BER/CRC/packet errors remain at baseline.
  • System symptoms: no dropouts/clicks/glitches in application-level signals.
Measurement table: goal → settings → mistakes → correct method
Measurement goal Instrument setting (lock these) Common mistake Correct method
A/B peak reduction (SSC OFF vs ON) RBW, VBW, detector, trace mode, span, sweep time, and number of sweeps. Changing settings between OFF/ON runs; comparing different trace modes without logging. Freeze settings first, then run OFF/ON at the same hotspot and geometry; repeat runs and report the range.
Avoid “fake improvement” from averaging Explicitly select peak-oriented vs average-oriented reading; keep detector consistent. Using average/averaging to claim peak reduction, then failing compliance-style peak checks later. Decide the goal (peak vs average) and use a consistent method; document it for repeatability.
Detect new discrete spurs Use a resolution that can separate lines; choose span that covers expected sidebands and images. RBW too wide (lines vanish into a blob) or RBW too inconsistent between runs (false differences). First scan for spurs with a consistent fine-enough RBW, then return to the compliance comparison setup for OFF/ON deltas.
Locate first (near-field) before quantifying Use near-field probe with relative comparisons; keep probe orientation and distance stable. Jumping to far-field/cable radiation results without knowing the dominant coupling path. Produce a hotspot list first, then quantify OFF/ON at the same hotspots with fixed analyzer settings.
Endpoint validation during EMI tests Log lock state and error counters concurrently with each EMI capture. Declaring success based on EMI alone while margin is silently consumed (intermittent errors at corners). Define pass criteria for both EMI and endpoint stability; freeze SSC only when both pass across corners.
Repeatability (run-to-run stability) Keep geometry stable (probe position, cable placement), keep analyzer settings fixed, capture multiple repeats. Reporting a single run as “the result” with untracked setup changes and unknown measurement variance. Record settings + geometry + SSC state; report min/max or percentile band across repeats.
Diagram: test bench + “wrong vs correct” analyzer setup
SSC measurement setup and analyzer traps A DUT is measured via near-field probe or antenna into a spectrum analyzer. Two side cards show wrong vs correct practices for RBW/VBW/detector/trace and sweep time consistency. Locate → Quantify (fixed settings) → Validate endpoints DUT SSC OFF / ON Probe / Antenna near-field first Spectrum Analyzer RBW VBW Detector Sweep Record settings + SSC state + geometry Wrong RBW mismatch Peak-hold trap Sweep too short Correct Fixed setup A/B compare Endpoint checks Repeatability

Engineering checklist: design review → bring-up → pre-scan → production (SSC-specific)

This section turns SSC into a repeatable process: define allowed links, sweep safely, measure correctly, then lock a stable profile for production. Every item is SSC-specific (compatibility margin, spread profile, measurement traps, and rollback paths).

A) Design review (before layout freeze)

Item Owner How to check Pass criteria
Identify SSC-allowed links (by endpoint class) SI + System Arch Endpoint tolerance: allowed ppm / tracking PLL or CDR / deterministic-phase requirement Clear allow/deny list + “needs validation” list; no ambiguous links
Decide default state & rollback (SSC ON/OFF) FW + Platform Boot strap / OTP / I²C policy; fail-safe state on reset; service-mode override One deterministic default + one deterministic safe fallback
Define allowed SSC envelope (mode/depth/rate/profile) SI + Clocking Choose down-spread first; set conservative depth; define rate sweep window Envelope documented + linked to validation plan; guardband reserved
Measurement plan (peak/avg traps handled) Test + Compliance Analyzer RBW/VBW/detector + peak-hold rules; baseline SSC OFF vs ON “Comparable-to-comparable” settings defined; no mixed settings across runs

B) Bring-up (sweep + record + rollback)

Record a stable baseline first, then sweep in a controlled order. Treat SSC as a configuration matrix: Mode → Depth → Rate → Endpoint validation.
Step What changes What to measure Pass criteria
1 SSC OFF baseline Peak EMI hotspots, endpoint lock/train/BER baseline Baseline saved; repeatability confirmed
2 Enable SSC (down-spread) Peak reduction at target bands; any new discrete spur Peak ↓ without “new dominant spur”
3 Sweep depth (small → target) Endpoint margin: training retries, lock events, BER/PER No stability regression vs baseline
4 Sweep rate (avoid “sensitive windows”) Spectrum appearance stability under fixed settings EMI gain retained; no measurement artifact
5 Freeze + guardband Temp/Vdd corners + long-run logging Profile stable across corners; rollback not triggered
Bring-up record fields (minimum set)
Board rev / clock source / SSC mode / depth / rate / profile / analyzer settings / peak delta / endpoint status (lock/train/BER) / corner condition / rollback events / final “locked profile” ID.

C) Compliance pre-scan (SSC OFF vs ON, apples-to-apples)

  • Lock instrument settings before comparison (RBW/VBW/detector/sweep/peak-hold).
  • Locate first (near-field probe), then quantify (repeatable setup + distance + cable routing).
  • Tag “new spur” candidates created by modulation artifacts and confirm by toggling SSC.
  • Verify endpoints during scan (no hidden retrain/lock loss while EMI looks “better”).

D) Production (lock profile + versioning + monitoring)

Configuration locking
Use strap/OTP/EEPROM to guarantee a deterministic SSC profile (mode/depth/rate/profile) and a deterministic safe fallback (SSC OFF or smaller depth).
Version label
Burn a readable profile ID into manufacturing logs (and optionally into a board EEPROM field) to correlate EMI results with field failures.
Monitoring
Add clock health signals to system telemetry: missing-pulse, loss-of-lock, unexpected spread state, and failover count.
Diagram — SSC workflow pipeline with “profile locked” gate
SSC engineering pipeline: design review to production profile lock A four-stage pipeline diagram: Design Review, Bring-up Sweep, Compliance Pre-scan, Production Lock & Monitor, ending with a Profile Locked stamp. Design Allowed links Default + rollback SSC envelope Bring-up Baseline OFF/ON Depth sweep Rate sweep Pre-scan Fixed RBW/VBW Peak-hold rules Spot new spurs Production Lock profile Version ID Monitor SSC profile locked mode/depth rate/profile STAMP CONFIG VERIFIED ROLLBACK READY

Applications & IC selection logic (board / PSU / storage friendly) — with material examples

SSC is most useful where peak EMI limits are tight and the endpoints tolerate controlled frequency modulation. Selection must be driven by: endpoint tolerance, spread envelope, and configuration control + rollback. Material numbers below are provided as datasheet starting points only.

A) Where SSC commonly pays off (stay in scope)

  • Board-level platform clocks: reduce dominant narrow peaks that fail pre-scan margins.
  • PSU / storage / IO ecosystems: clock-related peaks can couple into harnesses, connectors, and return paths.
  • Multi-output clock trees: SSC at the generator avoids “per-branch fixes” at each endpoint.
Scope guard
SSC reduces peak EMI by spreading energy; it does not replace clock-integrity or EMI-root-cause analysis.

B) Selection logic (no product-selling; decision hooks only)

Decision hook What to demand (datasheet fields) How to verify Pass criteria
Need SSC on this link? Enable pin / strap / I²C; default state; safe fallback state Toggle SSC under load; log endpoint behavior Deterministic ON/OFF; rollback always recovers
Spread envelope Mode (down/center), depth options, modulation rate, profile type Depth/rate sweep; watch EMI peak and “new spurs” Peak ↓ with no new dominant spur
Output standard LVCMOS/LVDS/HCSL/LVPECL; termination guidance; swing/CM Eye/clock integrity at endpoints; reflection sensitivity check No added jitter issues; no reflection-driven peak rebound
Configuration storage EEPROM/OTP/register map; multi-profile support; lock mechanism Power-cycle + brownout tests; confirm persistent profile Profile survives resets; no “random” SSC state

C) Vendor questions (RFQ field list)

Question Why it matters Verification method
Which SSC modes are supported (down/center)? Avoids upper-limit violations and endpoint incompatibility Mode toggle + pre-scan comparison
Depth options and how they are selected (pins/SMBus/I²C)? Defines endpoint frequency margin consumption Depth sweep with endpoint BER/training logs
Modulation rate range; profile type (triangle / dither)? Changes spectral appearance and “new spur” risk Fixed analyzer settings + rate sweep
How is SSC state defined at power-up and after reset? Avoids production escapes due to “unknown SSC state” Power-cycle/brownout tests + state readback

D) Concrete material numbers (starting points only; verify suffix/package/availability)

These examples exist to speed up datasheet lookup and shorten validation cycles. Final selection must be driven by: EMI target + endpoint tolerance + configuration control + measured margin.

Part number Vendor Where it fits SSC hooks to confirm
9FGL0641BKILF Renesas PCIe refclock generator (multi-output LP-HCSL) Pin/SMBus selectable spread states; CC/SRIS options
9FGL0841BKILF Renesas Higher fanout PCIe clock generator option Two spread levels + spread off (confirm exact levels)
PI6C557-03AQ Diodes Incorporated Spread-spectrum clock generator (2 outputs HCSL/LVDS) Down-spread options via pins; bypass option
PI6C557-05Q Diodes / Pericom Spread-spectrum clock generator (4 outputs HCSL/LVDS) Multiple down-spread depth selections via pins
PI6C557-01BQ Diodes Incorporated PCIe refclock style generator (HCSL/LVDS spread outputs) Confirm selectable spread vs no-spread modes
CDCE913 / CDCEL913 Texas Instruments Programmable clock generator family (EEPROM; SSC support) SSC enable + mode selection; profile persistence
CDCE925 / CDCEL925 Texas Instruments Multi-output programmable clock generator (SSC supported) Center vs down-spread; PLL assignment per output
CDCS502 / CDCS503 Texas Instruments Simple SSC-capable clock buffer / multiplier use cases SSC amount options + multiplication behavior
MAX31180 Analog Devices (Maxim) Spread-spectrum crystal multiplier (pin-programmable dither) Dither magnitude selection + disable mode
5P49V5935 (NRND) / 5P49V6975 Renesas Programmable clock generator (multi-format outputs; SSC per output pair) Independent SSC per output; config storage; switchover
Selection warning (prevents hidden cross-page drift)
“Supports SSC” is not enough. Confirm: (1) exact spread modes/levels, (2) deterministic power-up state, (3) endpoint stability at corners, (4) measurement repeatability (same analyzer settings).
Diagram — SSC selection decision tree (no selling; validation-driven)
SSC selection decision tree A flowchart guiding SSC selection: need peak EMI reduction, endpoint tolerance, choose mode/depth/rate, pick generator location, validate, then lock profile and define rollback. Need peak EMI reduction? Endpoint tolerates SSC? (ppm window / tracking PLL or CDR / deterministic phase) Choose SSC envelope mode / depth / rate / profile Choose generator location oscillator SSC / PLL SSC / platform-controlled Validate (must-do) EMI peak delta (fixed settings) Endpoint lock/train/BER at corners Freeze + guardband lock profile + rollback path version label + monitoring hooks EMI peak ↓ margin consumed

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FAQs: SSC troubleshooting (actionable, data-structured)

Each answer is a 4-line checklist: Likely cause → Quick check → Fix → Pass criteria. Keep comparisons apples-to-apples (same setup, same instrument settings, SSC OFF vs ON).

Why does SSC reduce peak EMI but the average/total power looks unchanged?
Likely cause: SSC spreads energy over a wider band, reducing narrow peaks while total/integrated energy is largely unchanged; analyzer averaging/detectors can hide peak reduction.
Quick check: With identical RBW/VBW/detector/sweep/trace mode, compare Peak-Hold vs RMS/Avg traces for SSC OFF and SSC ON; compute ΔPeak_dB = Peak_OFF − Peak_ON at the target frequency.
Fix: Use peak/quasi-peak targets (not “total power”) for SSC acceptance, and lock measurement settings and setup for every OFF/ON comparison.
Pass criteria: ΔPeak_dB ≥ Goal_dB at the target band, and Avg/RMS trace does not show an abnormal broadband lift beyond Repeatability_dB (same setup, repeated runs).
Why did a new narrow spur appear after enabling SSC?
Likely cause: SSC implementation creates discrete modulation artifacts (stepwise control, fractional interaction, or periodic dithering) that show up as narrow sidebands/spurs.
Quick check: Change only one knob at a time (rate or depth); if the spur moves with modulation rate or scales with depth, it is SSC-related; verify using narrower RBW without changing the physical setup.
Fix: Reduce depth, move rate away from the sensitive window, or switch profile (triangle vs dither) if available; if needed, change SSC injection point (oscillator SSC vs PLL SSC) to reduce discrete artifacts.
Pass criteria: New spur amplitude is below Spur_Limit_dBc and is not the dominant peak in the compliance band; endpoints remain stable with SSC ON (no retrain/lock events).
Why does EMI get worse at certain modulation rates (measurement artifact vs real)?
Likely cause: Rate-dependent “worse EMI” can be a spectrum-analyzer artifact (RBW/VBW/sweep/peak-hold interaction) or a real coupling sensitivity to that rate.
Quick check: Freeze the setup and instrument settings, repeat each rate point ≥ 3 times, and confirm whether the “worse” result persists; then change only sweep time to test artifact sensitivity.
Fix: If it is an artifact, standardize settings for SSC validation; if it is real, avoid that modulation-rate window and re-sweep rate while keeping depth constant.
Pass criteria: OFF/ON conclusion and ΔPeak_dB direction are consistent across repeats under locked settings; selected rate avoids the “worse” window with stable endpoints.
Why does the endpoint occasionally lose lock only when SSC is enabled?
Likely cause: SSC consumes tracking margin (PLL/CDR), and borderline conditions (PVT, cable, supply noise) push the endpoint over the lock threshold only when SSC is ON.
Quick check: Log endpoint counters (lock status, retrain count, error counters) for SSC OFF vs ON; reduce depth by one step and check if lock events disappear immediately.
Fix: Reduce depth, move rate, prefer down-spread, and enable SSC after link training where applicable; scope SSC only to tolerant branches and define automatic rollback (SSC OFF or smaller depth) on lock-loss events.
Pass criteria: Retrain_Count = 0 over N_Boots and N_Hours under defined stress corners, and BER/PER meets Spec_BER with SSC ON at the locked profile.
Down-spread chosen—why is the system still failing frequency tolerance?
Likely cause: Worst-case minimum frequency (nominal error + aging/temp drift + down-spread depth) falls outside the endpoint’s allowed tolerance even though the center looks correct.
Quick check: Compute f_min = f_nom × (1 − Base_Error − Depth) using worst-case bounds, and verify with a frequency counter/endpoint telemetry during SSC ON; compare against endpoint min-tolerance.
Fix: Reduce depth, calibrate/trim the nominal frequency, or disable SSC on that link; if SSC must stay, move the SSC point to a place where the endpoint re-clocks/regenerates within tolerance.
Pass criteria: Measured frequency excursion stays within endpoint tolerance across defined corners; no tolerance alarms or lock loss with the locked profile.
Why does SSC break only at temperature corners?
Likely cause: Temperature corners reduce tracking margin (endpoint PLL/CDR) and can worsen supply-noise-to-jitter conversion, making SSC-induced excursions fail only at extremes.
Quick check: During a controlled temperature sweep, log SSC profile readback, endpoint lock/retrain counters, and a supply-noise proxy (ripple measurement at the clock IC rails) for OFF vs ON.
Fix: Add guardband (smaller depth or different rate), improve clock-rail cleanliness, and apply a corner-aware policy (reduce depth or disable SSC at extremes) if required by system tolerance.
Pass criteria: No lock-loss/retrain events across the specified temperature range and soak conditions; EMI peak improvement remains present or degrades only under a controlled, logged fallback policy.
How do I validate SSC without a full EMC chamber test?
Likely cause: Early validation often lacks a chamber, but SSC benefit can still be confirmed using repeatable relative measurements (OFF vs ON) at the identified clock-related hotspots.
Quick check: Use near-field probing to locate the dominant clock-related peak, then lock probe placement, cabling, RBW/VBW/detector, and compare SSC OFF vs ON across ≥ 3 repeats.
Fix: Treat validation as a delta test (ΔPeak_dB) with strict setup control; reserve final absolute compliance decisions for the chamber while keeping endpoint validation running in parallel.
Pass criteria: ΔPeak_dB exceeds the measured setup repeatability (Repeatability_dB) at the target frequency, and endpoint counters show no regression compared to the SSC OFF baseline.
Why does SSC help radiated EMI but not conducted (or vice versa) on my board?
Likely cause: Radiated and conducted emissions are driven by different dominant coupling paths; SSC mainly changes clock spectral peaks and may not affect the non-clock-dominant path.
Quick check: Identify whether the failing peak is clock-correlated by toggling SSC (OFF/ON) and checking if the peak shifts/spreads; use near-field for radiated hotspots and supply-line measurement for conducted correlation.
Fix: Apply SSC where the dominant failure peak is clock-related; if the dominant path is not clock-related, prioritize coupling-path fixes and keep SSC as a secondary knob only.
Pass criteria: In the emission domain being evaluated, the clock-correlated peak shows a repeatable ΔPeak_dB improvement under locked settings; non-clock peaks do not become dominant after SSC.
Should SSC be enabled before or after link training / during boot?
Likely cause: Some links train more reliably with a steady reference; enabling SSC too early can reduce training margin depending on endpoint tracking behavior.
Quick check: Compare boot sequences (SSC ON before training vs SSC ON after training) while logging training retries, time-to-link, and error counters across ≥ N_Boots.
Fix: Default to enabling SSC after successful training/lock; if early SSC is required, reduce depth and add a policy to auto-disable SSC on training failure and re-attempt training.
Pass criteria: Training success rate and time-to-link do not regress vs baseline; with SSC ON, link remains stable (no retrain) over the defined runtime window.
How to implement a safe fallback (SSC off) without creating glitches?
Likely cause: Abrupt SSC state changes can introduce phase/frequency discontinuities (or mux glitches) that trigger retraining or clock-missing detection at sensitive endpoints.
Quick check: Observe endpoint behavior during SSC ON→OFF transitions (lock/retrain/missing-pulse flags) and confirm whether failures correlate only with the transition event.
Fix: Use glitch-free muxing where available, or stage the transition (reduce depth → disable SSC) during an endpoint-safe window (idle, retrain window, or controlled reset), and log every fallback event with profile ID.
Pass criteria: SSC fallback produces zero unexpected retrains and zero missing-pulse alarms across N_Transitions; system recovery is deterministic and traceable (Fallback_Count logged).
Why does SSC “improve the plot” but the assembled product still fails pre-scan?
Likely cause: Assembly changes the dominant coupling path (chassis, harness, shielding, return paths), so the pre-scan peak is no longer dominated by the original narrow clock component that SSC was targeting.
Quick check: Compare hotspot maps and peak frequencies between bare-board and assembled configuration; toggle SSC OFF/ON to confirm whether the failing peak is clock-correlated in the assembled setup.
Fix: Scope SSC to the links that still show clock-correlation in the assembled product, and update the validation setup and allowed-links map to match the final mechanical/electrical configuration.
Pass criteria: In assembled configuration, SSC ON produces a repeatable ΔPeak_dB improvement at the failing peak (under locked settings), and endpoints remain stable at the locked profile.
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