Supply & EMI for Clocking: PSRR, Filters, SSC Strategy
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Supply & EMI problems in clocking are rarely “mystery jitter”—they are usually a specific coupling path (conducted, radiated, or SSC-modulated) that can be isolated with a few fast A/B tests. This page turns those paths into measurable budgets and fixes, so improvements can be proven by repeatable pass criteria instead of guesswork.
Scope map: what this page covers (and what it doesn’t)
This page focuses on clock-chain Supply & EMI: how rail noise, return currents, and intentional modulation (SSC) turn into jitter, spurs, lock margin loss, and EMI failures—and how to design and verify fixes without expanding into generic power/EMC theory.
In-scope (answered here)
Result-driven + measurable
- Conducted (supply-driven): rail noise → phase noise floor lift, integrated jitter increase, or discrete spurs.
- Radiated / coupling: edge harmonics + imbalance → common-mode radiation (hotspots near connectors/cables/board edge).
- Modulated (SSC): EMI peak reduction vs timing margin loss; SSC enablement, partitioning, and rollback criteria.
- Isolation & filtering: clock-rail topology, damping, return-path control, and “quiet island” layout patterns.
- Verification: A/B tests, correlation checks, and pass/fail criteria placeholders (e.g., X fs rms, Y mVrms, N runs).
Out-of-scope (link out; no deep dive here)
Prevents sibling-page overlap
- Phase Noise & RMS Jitter definitions, integration windows, and SNR budgeting methodology → Phase Noise & Jitter (canonical)
- Output electrical standards (LVCMOS/LVDS/HCSL/LVPECL) including termination and common-mode details → Output Standards (canonical)
- Interface-specific “must-follow” clauses (PCIe/JESD/Video/SyncE…) → handled in interface clock pages; this page provides compatibility checks and engineering gates only.
Where to start (first-probe triage)
Conducted (rail → timing)
Start with rail FFT / noise PSD at the closest decoupling point. Check whether spur spacing aligns with fSW or digital activity.
Radiated (layout / return path)
Use a near-field probe to locate hotspots (connector/edge/cable). If shielding/return-path tweaks move the peak, radiated coupling dominates.
Modulated (SSC trade-off)
Run a clean A/B: SSC off vs SSC on. If EMI improves but lock/training margin degrades, proceed with SSC partitioning and rollback gates.
Default chain segmentation (used throughout this page):
Reference →
PLL/Cleaner →
Fanout →
Endpoint
Diagram: Clock chain × noise coupling map
The same three risk channels (conducted / radiated / modulated) will be used as a routing key in later sections:
identify the dominant path first, then apply targeted fixes with measurable pass criteria.
Why supply noise shows up as jitter, spurs, or lock issues
Clock problems rarely present as “rail noise” on the surface. They present as jitter numbers, specific spurs, or intermittent lock/training failures. The fastest path to a fix is to translate each symptom into a testable mechanism with a measurable signature.
Symptom
Random jitter / PN floor rises
Mechanism: broadband rail noise passes through the device’s supply sensitivity (effective PSRR/transfer),
lifting the phase-noise floor across a band that matters to the integration window.
Signature: a “floor lift” (wide-band change) rather than one discrete line; improvements track changes in local filtering/LDO behavior.
First probe
Measure rail noise PSD near the IC (short ground, closest decoupler), then compare A/B with a controlled change
(e.g., alternative LDO / added damping). Use placeholders:
X fs rms target (window [fL,fH]); rail noise limit Y mVrms in the dominant band.
Symptom
One or a few spurs (offset lines)
Mechanism: periodic ripple or periodic loading modulates the oscillator/PLL/VCO path, creating discrete sidebands.
Common culprits: DC/DC switching frequency (fSW) and its harmonics, burst modes, or synchronous digital activity.
Signature: spur spacing aligns with fSW (or a subharmonic); changing DC/DC mode or load pattern shifts the spur.
First probe
Overlay rail FFT peaks with spur offsets (same spacing). Verify correlation with a single sweep:
tweak fSW (or switch PWM/PFM) and check whether the spur moves accordingly. Pass criteria placeholder:
spur power below X dBc or below the system mask at the relevant offset.
Symptom
Lock flaps / training fails intermittently
Mechanism: transient ground bounce or return-path coupling modulates the clock edge at the worst moment
(activity bursts, link state changes, connector common-mode events). SSC can tighten margins if the endpoint tolerance is narrow.
Signature: failures correlate with activity (bursts / lane bring-up / hot-plug) and show a strong A/B response to
SSC enablement or return-path tweaks near the clock island.
First probe
Run N repeated bring-up attempts and log lock/training statistics. In parallel, capture rail droop / ground bounce at the closest points.
A quick discriminator: SSC off vs SSC on. Pass criteria placeholder:
failure rate < X per N attempts across temperature/voltage corners.
Symptom
EMI peak fail (narrowband)
Mechanism: clock harmonics radiate when differential balance is broken or when the return path is discontinuous.
Hotspots often appear near connectors/cables/board edges where common-mode currents “find an antenna.”
Signature: near-field scan shows strong peaks localized at a physical feature (connector, edge, cable). Supply changes have weak impact,
but routing/return/shielding moves the peak.
First probe
Do a near-field sweep to find the hottest physical region; then apply a single controlled change (temporary shield, improved return stitching)
and re-scan. Pass criteria placeholder: peak margin > X dB below the limit in pre-scan and final test.
Symptom
PN looks “low”, but system SNR/BER is worse
Mechanism: a spur or low-frequency modulation drives system degradation, but the default RMS jitter window
(or instrument settings) hides it. One line can dominate converter/SerDes performance while barely moving an RMS number.
Signature: the reported jitter changes dramatically with the integration band; system performance correlates with a specific spur/amplitude rather than the floor.
First probe
Re-run reporting with a clearly stated band ([fL,fH]) and track the dominant spur separately. Use a correlation check:
spur power change vs SNR/BER change. Pass criteria placeholder: spur below mask and jitter below budget simultaneously.
Diagram: Symptom → root-cause routing (with signatures & first probes)
Use the routing table to avoid “multi-variable debugging”: pick a single symptom, run a single A/B discriminator test, then lock a measurable pass criterion before iterating.
Coupling mechanisms in clock devices: where PSRR is real vs where it lies
Supply noise does not enter a clock device through one “VDD → PSRR” pipe. It enters through specific sensitive blocks (frequency-setting, phase-setting, and output/return), and each block responds to a different noise type (LF drift, HF floor lift, transient bounce, harmonic current). Correct filtering starts by identifying the dominant entrance, not by adding parts.
A) Sensitive blocks (what actually converts rail noise into timing errors)
Frequency-setting loop (XO / TCXO / OCXO / MEMS)
Rail noise can “push” frequency directly through the resonator loop and its compensation/oven control paths, appearing as LF modulation (wander-like),
or as a broadband floor lift depending on the device and bias conditions.
Phase-setting loop (PLL / cleaner: VCO / CP / loop filter / digital)
VCO sensitivity tends to dominate HF timing noise; charge pump and loop filter paths often dominate LF modulation inside the loop bandwidth.
Digital-core activity can inject switching noise and create discrete spurs when correlated with internal clocks.
Output / return (fanout / driver: current pulses → bounce → mode conversion)
Output stages draw harmonic current at clock edges. With imperfect return paths, this becomes ground bounce and common-mode current,
turning into EMI peaks and intermittent margin loss even when a “PSRR curve” looks good on paper.
B) Noise types (map the symptom to the entrance)
LF
drift / slow modulation
Often tied to compensation/oven loops, loop bandwidth interactions, or low-frequency rail variation; shows up as slow wander or periodic anomalies.
HF
floor lift / integrated jitter
Broadband rail noise converts to phase noise through supply sensitivity; appears as “everything gets worse” rather than one line.
Transient
bounce / droop
Activity-correlated ground bounce or rail droop tightens lock and training margins; shows up as intermittent failures.
Harmonic
edge current / CM
Output driver current pulses excite return-path inductance and convert to common-mode radiation near connectors and cables.
C) Why PSRR curves mislead on real boards
- Band mismatch: the dominant rail noise lives outside the published PSRR band (or the band where the device is sensitive).
- Operating-point mismatch: output level, drive strength, and load change current spectra and internal coupling.
- Multiple entrances: noise couples through VDD, ground, reference pins, control pins, and common-mode paths—not one transfer function.
- Layout dominance: decoupling loop inductance, return discontinuities, and via placement can override “device-only” PSRR.
Practical takeaway
Treat PSRR as a context-dependent hint. Start by identifying the sensitive block and noise type,
then validate the entrance with a single A/B discriminator test before adding filters.
Diagram: Inside the clock IC — sensitive blocks & entrances
The diagram highlights why “one PSRR curve” is insufficient: timing errors depend on which block is sensitive, which noise type dominates, and whether return paths convert current pulses into modulation or common-mode radiation.
PSRR & transfer functions: turning rail noise into jitter/spur budgets
This section converts rail measurements into acceptance-ready budgets. The goal is not a long derivation, but a workflow that produces clear pass criteria (jitter, spurs, and rail limits) tied to a stated reporting window and measurement method.
Chain #1
Supply noise PSD → PN floor / integrated jitter
- Measure rail noise PSD at the closest decoupling point (short ground, consistent bandwidth/RBW).
- Apply an effective transfer / PSRR profile (device + layout) as a frequency-shaped weighting.
- Overlay the result against the reporting window [fL,fH] used for integrated jitter.
- Convert the dominant overlap band into a rail limit: rail noise must be below Y mVrms (or equivalent) in that band to keep jitter below X fs rms.
Acceptance template (placeholders)
Integrated jitter < X fs rms @ window [fL,fH], under stated conditions (V/T/load/mode), with measurement settings recorded.
Chain #2
Supply ripple at f → spur at offset
- Identify discrete ripple tones on the rail (often fSW, harmonics, burst envelopes, or activity clocks).
- Check whether spur spacing matches the ripple frequency (fast “spacing ≈ f” sanity check).
- Prove causality with one controlled sweep: change fSW / mode (PWM↔PFM) or load pattern and verify the spur moves or changes coherently.
- Set a spur budget: spur power below X dBc (or below the mask) at offsets of interest, while keeping integrated jitter within budget.
Acceptance template (placeholders)
Spur mask passes with margin > X dB; dominant spur < X dBc; verified by a single-cause sweep (frequency or mode) with correlation logged.
Dominant-term engineering (avoid over-modeling)
If the symptom is “floor lift / RJ ↑”
Start with Chain #1. The dominant overlap band between rail PSD and transfer profile sets the rail limit Y for meeting jitter budget X.
If the symptom is “one spur / spacing ≈ f”
Start with Chain #2. Prove causality with one sweep before adding filters that could create resonant peaks.
If the symptom is “intermittent lock/training”
Treat it as transient / return-path first. Express acceptance as a statistics gate:
failure rate < X per N attempts across corners, with correlated bounce capture.
Diagram: Noise transfer overlay (rail PSD × transfer × output PN)
The overlay is a practical budgeting tool: identify the dominant overlap between rail PSD and transfer, then set a rail limit (Y) that protects the timing budget (X) for a clearly stated reporting window [fL,fH]. Treat discrete ripple tones separately as spur risks.
Power-tree architecture for clocks: DC/DC + LDO + local filtering done right
A clock power tree is a noise-shaping chain. The objective is to keep switching ripple, digital activity noise, and output-driver current pulses from reaching supply-sensitive blocks (XO core, VCO/CP/LF, and high-edge-rate drivers). Good results come from matching topology + target band + impedance, then adding damping to avoid resonance peaks.
A) Common building blocks (how they divide responsibilities)
Main DC/DC (energy efficiency)
Dominates conducted ripple and harmonic content around fSW. Treat it as the “noise source” that must be isolated and shaped before reaching sensitive rails.
Low-noise LDO (LF / mid-band cleanup)
Useful when the dominant risk is floor lift / integrated jitter. Ensure headroom and thermal margins; confirm PSRR where the device is actually sensitive.
Local filtering (π / RC / bead + C) + damping
Strong for HF spikes and discrete ripple tones, but only when impedance and resonance are controlled. Add damping (ESR or small R) to avoid narrow peaks.
B) When “bead + capacitors” beats “one more LDO”
Prefer bead/π
dominant risk is HF spikes or fSW-related spur lines
Impedance isolation can reduce high-frequency injection without the headroom/thermal cost of another LDO.
Always verify the bead’s DC bias behavior and add damping to prevent resonance peaks.
Prefer LDO
dominant risk is broadband floor lift (integrated jitter)
A low-noise rail with strong suppression in the dominant band is often the cleanest path.
Confirm headroom, thermal, and that PSRR is valid in the frequency region that matters.
Avoid
stacking filters without resonance control
Multiple LC sections can create a narrow impedance peak that amplifies ripple and produces a spur.
Require an explicit “no-peak” check (impedance or rail FFT) after every added stage.
C) Rail partitioning: analog vs digital vs output (when it helps, when it backfires)
Must split (strongly recommended)
When VCO/CP/LF sensitivity and digital switching are both strong, and the output driver draws harmonic current.
Use separate analog/digital LDO rails, and consider an output rail separation for high-edge-rate fanout.
Optional split (layout-dependent)
When digital activity is light and return paths are already controlled, splitting may add complexity with limited benefit.
Prefer fewer domains with excellent local decoupling and short return loops.
Backfires (common real-board failure)
Splitting rails without controlling ground/return forces currents to detour (large loop area), raising common-mode noise and intermittency.
Domain boundaries must be paired with return-path control (covered next).
D) Engineering rules for local filters (band, impedance, damping, verification)
- Declare the target band: LF drift, HF floor lift, fSW spur lines, or transient droop. Design to one dominant risk first.
- Match impedance: filters work by shaping impedance; avoid creating a high-Q peak at a “bad” frequency.
- Add damping: use ESR or a small series R to flatten the impedance peak; require a “no-peak” check.
- Verify with a single-variable A/B: rail FFT near the load, spur check at the output, and a stated jitter window [fL,fH].
- Acceptance placeholders: rail noise < Y mVrms in the dominant band; spur < X dBc; intermittent failures < X/N.
Diagram: Clock power tree cookbook (three typical topologies)
The three topologies cover most clock rails: use an LDO when the dominant risk is broadband floor lift, use impedance isolation for HF spikes and discrete tones,
and split analog/digital rails only when return paths are controlled and verified.
Isolation & grounding: stopping digital return currents from modulating the clock
“Isolation” in clocking is not about cutting copper into disconnected islands. It is about controlling return paths so that noisy digital currents do not flow through the clock reference region, and minimizing loop area so common-mode current and ground bounce cannot convert into phase modulation.
A) Correct isolation model (what to control)
- Return path proximity: return current should follow the signal path closely, not detour around gaps and voids.
- Coupling area: larger loop area increases common-mode radiation and susceptibility.
- Controlled bridge points: connect domains at a deliberate location near the controlled endpoint, not “somewhere convenient.”
B) Real-board traps (why rails look clean but intermittency persists)
Trap 1: split ground with a crossing return
A trace crosses a gap; the return is forced to detour, creating a large loop. This raises common-mode current and can convert into phase modulation near the clock path.
Trap 2: via inductance / stitching scarcity
High di/dt currents across insufficient stitching vias produce ground bounce. Activity-correlated bounce tightens margin and drives intermittent lock/training events.
Trap 3: reference plane discontinuities
Layer transitions, voids, and cutouts break the reference plane. Return currents spread and the common-mode loop grows, especially near board edges and connectors.
C) Practical strategies (layout actions that directly reduce modulation)
Clock “quiet island”
Keepout around the source/cleaner, short decoupling loops, and a via fence that prevents return currents from cutting through the reference region.
Place the domain “bridge” at the controlled point
If a boundary is used, connect it near the sensitive endpoint so the return does not detour. The bridge is a return-path control tool, not a symbolic separator.
Connector region: common-mode loop hotspot
Stitch grounds near shields, shrink the exposed loop from driver to connector, and prevent the clock return from sharing the connector’s common-mode loop.
D) Fast verification method (one A/B change, measurable outcome)
- Locate hotspots with near-field scanning and capture local ground bounce near the clock island and connector region (consistent probe reference).
- Apply one controlled change (temporary bridge, added stitching vias, tightened return path) and record: EMI peak delta, spur delta, and intermittent failure rate gate (< X/N).
Diagram: Return-path control map (wrong vs right)
The map shows why “splitting” can backfire: if return currents detour across gaps, loop area grows and common-mode current rises.
A quiet island with stitching and a controlled bridge keeps return paths tight and reduces modulation of the clock reference.
SSC strategy: when it helps EMI, when it breaks timing margins
Spread-spectrum clocking (SSC) trades peak spectral lines for a broader energy distribution. It can rescue a narrowband EMI peak, but it can also consume frequency/jitter tolerance in sensitive links. A correct strategy answers four questions: should SSC be enabled, where in the chain, which outputs, and how to verify pass criteria.
A) SSC controls (engineering meaning only)
depth
spread depth (frequency deviation)
Higher depth tends to reduce narrow peaks more, but consumes more margin in frequency-sensitive endpoints.
Treat depth as a direct “margin spender”.
rate
modulation rate (how fast it sweeps)
Rate determines where the “energy spreading” lands versus system response. A poor rate can surface as periodic errors or lock flapping.
profile
profile (how it sweeps)
Profile shapes the distribution: some patterns reduce discrete line prominence better, others are friendlier to lock loops. Choose by A/B verification.
B) When SSC is a good tool
best fit
narrowband EMI peak dominates
- EMI failure is driven by one/few discrete peaks (not a broad noise floor).
- The endpoint has verified timing margin: error/lock failures < X/N, and key performance metrics retain margin > X.
- SSC can be applied selectively on the radiating segment (typically fanout outputs to connectors/cables).
C) High-risk checklist (common ways SSC breaks margins)
Narrow tracking loops / sensitive lock chains
Risk: modulation becomes a visible phase/frequency perturbation → periodic errors or lock flaps.
Quick check: vary modulation rate and observe whether the failure periodicity follows (single-variable).
Interfaces with tight frequency tolerance / jitter tolerance
Risk: SSC consumes tolerance budget.
Quick check: enable/disable SSC and compare training/lock statistics and endpoint alarms across temperature and load states.
Mixed-clock systems (some outputs are “timing-critical”)
Risk: spreading “everything” pollutes a sensitive chain.
Quick check: apply SSC only on radiating outputs; keep sensitive outputs non-SSC and verify both EMI and margin gates.
D) Practical SSC strategy (placement + output split + pass gates)
Where to spread
- Prefer fanout stage: enable SSC only on outputs that route to connectors/long traces.
- Avoid upstream spreading: do not spread a reference that feeds multiple sensitive consumers unless verified per consumer.
- Output split: keep timing-critical outputs non-SSC; spread only the radiating path outputs.
Parameter tuning (single-variable steps)
- Start with small depth (Depth: X–Y%) and verify margin.
- Then adjust rate (Rate: A–B) to avoid sensitive system response regions.
- Change profile only after depth/rate are stable in A/B testing.
Verification gates (must pass together)
- EMI: peak margin improved by X dB at the failing frequency band.
- Timing: error/lock failures remain < X/N across temperature and operating states.
- Spurs/jitter: no new dominant spurs; jitter window [fL,fH] remains within budget.
Diagram: SSC decision flow (enable/disable + placement + placeholders)
Use SSC primarily to address narrowband peaks, apply it at the fanout/output stage when possible, and always require A/B gates that protect timing margin.
EMI reduction toolkit for clocks: edge control, routing, and mode conversion
Clock EMI is rarely “just differential”. Radiation and susceptibility are dominated by common-mode current, and common-mode is often created by imbalance (length/impedance mismatch) and reference discontinuities. The most reliable path is to reduce harmonics at the source, prevent differential-to-common-mode conversion, and harden the connector/edge segment.
A) Edge control (harmonics vs margin)
Slew / drive strength
Reducing edge rate can reduce harmonic content and near-field peaks. It must be bounded by timing margin:
slower edges can reduce eye opening and increase sensitivity to noise around thresholds.
Series-R at the driver
A small series resistor can reduce ringing and high-frequency energy, especially in short-to-mid runs.
Confirm amplitude and jitter after the change, and verify that termination strategy remains correct.
Fast verification gate
A/B (one knob at a time): near-field peak improves by X dB while error/lock failures remain < X/N.
B) Differential ≠ no EMI (imbalance creates common-mode)
- Mismatch (length/impedance/via geometry) converts differential energy into common-mode.
- Reference plane gaps force return current to spread, increasing loop area and common-mode current.
- The connector/edge segment is often the dominant radiator; minimize exposed loop and stitch grounds aggressively.
C) Routing checklist (most leverage near connectors)
Differential pair symmetry
Match lengths and geometry, keep both traces on the same reference plane, and use symmetric via transitions.
Continuous reference plane
Avoid gaps and voids under the pair. If a crossing is unavoidable, add stitching vias to provide a short return path.
Connector segment hardening
Shorten exposed runs, keep the pair tight to its reference, stitch to shield/ground near the connector, and prevent common-mode loops from growing.
D) Shielding & isolation tools (board-level actions)
Via fence / stitching
Adds a low-inductance return boundary and reduces field leakage. Most effective at edges, connector regions, and around the clock island.
Guard / keepout
Keepouts prevent coupling into sensitive analog regions. Guard structures must still preserve a continuous reference plane and controlled returns.
Diagram: Differential pair → common-mode conversion (faults + fixes)
The fastest EMI wins come from preventing differential-to-common-mode conversion and hardening the connector/edge segment, not from “differential” assumptions.
Measurement & compliance: how to prove improvements (pre-scan to final)
Effective clock EMI work is evidence-driven: each change must produce a repeatable before/after delta across conducted, timing, and radiated metrics. The goal is not more measurements, but a tighter loop that preserves causality (single-variable changes) and produces unambiguous pass gates.
A) Verification loop (always keep causality)
- Pre-scan: capture failing peaks/offsets (Top N) + screenshots + conditions.
- Localize: align evidence across near-field hot spots, rail FFT, and timing spurs.
- Fix: change log (single-variable), BOM/layout/parameter delta.
- Re-test: differential comparison (Δ dB / Δ spur / Δ fail rate) under same conditions.
- Final: pass gates recorded (thresholds + screenshots + run logs).
Rule: single-variable changes
One change per iteration preserves causality. Multi-change “shotgun fixes” invalidate evidence even if the symptom improves.
B) Conducted evidence: rail ripple FFT + injection (cause confirmation)
FFT
rail ripple spectrum
- Measure at the device near-end (post-filter / decap array), then compare upstream.
- Report Top spurs: frequency + amplitude, and tag the rail (VDD_A / VDD_D / VDD_OUT).
- Look for frequency alignment between rail peaks and timing spurs (correlation anchor).
inject
small-signal injection sweep
- Inject a controlled tone/noise at < X mVrms, sweep f1–f2 to map sensitivity bands.
- Observe spur amplitude and lock/fail statistics; confirm linearity vs injection level.
- Pass gate (placeholder): spur increment < Y dB and fail rate < X/N.
C) Timing evidence: spur ID + jitter window + lock statistics
Spur identification (correlation-ready)
- Track spur frequency/offset stability before/after changes (same RBW/span).
- If spur frequency stays fixed and amplitude drops, the coupling path was reduced.
- If spur shifts with SSC rate/profile changes, treat SSC as a margin consumer.
Random jitter reporting (window anchored)
- Always report RJ as: RJ([fL,fH]) and keep [fL,fH] fixed for before/after.
- Do not accept “RJ improves” if a new dominant spur appears in the same window.
Lock/Training statistics (turn flakiness into numbers)
- Log lock time (mean / 99%), unlock events, training fail rate (X/N) under tagged conditions.
- Pass gate (placeholder): failures < X/N across temperature and operating states.
D) Radiated evidence: near-field localization + pre-scan deltas
Near-field scan (hot-spot map)
- Scan connector/edge first, then via clusters and bends, then the clock island.
- Capture Top hot spots with the peak frequency annotated (correlation-ready).
Pre-scan delta (before/after must be comparable)
- Keep probe position/orientation/height fixed; compare Δ dB at the same frequencies.
- Pass gate (placeholder): peak reduction > X dB while timing gates still pass.
E) Practical compliance path (engineering cadence only)
path
pre-scan → localize → fix → re-test → final
Keep the loop short and evidence-based. Final testing should be attempted only after the pre-scan deltas and timing gates are stable across operating conditions.
Diagram: Verification loop (Design → Pre-scan → Fix → Re-test → Final)
Keep the loop causal: single-variable changes, comparable setups, and explicit pass gates that protect timing while reducing radiated peaks.
Debug playbook: fastest isolation tests for supply- vs EMI-driven failures
Fast debug is about isolating the dominant mechanism with minimal edits. The highest-yield approach uses three reversible tests (injection, near-field, and SSC toggles) to map failures to either conducted coupling, radiated/common-mode paths, or SSC margin consumption.
A) One-knife triage rules (quick discriminators)
Move/replace LDO or local filter
If the symptom follows the power-tree topology or filter placement, conducted coupling is likely dominant.
Near-field peak aligns with spur/offset
If the hot-spot peak frequency matches the timing spur/offset or the failing band, an EMI/common-mode path is likely involved.
Disable/adjust SSC and watch “inverse” behavior
If EMI improves while link margin degrades (or vice versa), SSC is consuming tolerance and must be segmented or disabled on sensitive outputs.
B) The three fastest experiments (reversible, single-variable)
Test 1
Power injection → spur/lock response
- Action: inject < X mVrms, sweep f1–f2 at the target rail.
- Observe: spur delta, RJ([fL,fH]), lock/unlock and training fail rate.
- Conclusion: sensitivity band appears and tracks injection → conducted coupling confirmed.
Test 2
Temporary shielding / distance → radiated delta
- Action: shield the connector/edge region or increase cable distance (one change).
- Observe: near-field peak Δ dB and pre-scan peak deltas at the failing band.
- Conclusion: large Δ dB with minimal timing change → radiated/common-mode path dominant.
Test 3
Return-path hack (foil/strap) → symptom shift
- Action: add a reversible foil/ground strap to provide a shorter return or bridge a suspected gap.
- Observe: hot-spot movement, peak delta, and spur/fail changes.
- Conclusion: strong improvement indicates return-path/reference discontinuity as the root driver.
Unified pass gate (placeholder)
Accept a “win” only if: EMI peak improves by X dB, failures remain < X/N, and no new dominant spur appears (Top spur < X dBc).
C) Avoid false conclusions (minimum-change discipline)
- Keep operating conditions fixed (temperature, load, mode, cable geometry) for before/after comparisons.
- Use the same spans/RBW and the same probe setup for spectrum and near-field comparisons.
- Record each iteration in a consistent log: change → setup → measurement → result → conclusion → next action.
D) Result mapping (what to do next)
Conducted-dominant
Prioritize power-tree segmentation, local filtering, and rail impedance shaping. Validate with injection sensitivity bands.
Radiated/common-mode dominant
Prioritize connector/edge hardening, symmetry, continuous reference planes, and stitching/via fences. Validate with near-field deltas.
SSC margin consumption
Segment outputs: keep sensitive consumers non-SSC and spread only radiating outputs. Tune depth/rate with single-variable A/B gates.
Diagram: 3-test triage tree (inject / near-field / SSC toggle)
Use three reversible tests to isolate the dominant mechanism quickly, then commit fixes only after the unified pass gate remains stable.
Engineering checklist (design review + bring-up gates)
This checklist turns supply/EMI work into stage gates. Each item is phrased to be reviewable, measurable, and recordable, with explicit evidence outputs and placeholder pass criteria (X/Y/N) that must be filled by the system budget.
Plan
Power-tree gate
Noise targets are defined per rail and per band
Evidence: rail FFT
Pass: noise_rms < X mVrms
LDO headroom is valid at worst-case VIN/load/temp
Evidence: DC budget
Pass: margin > X mV
Filters are damped (no impedance peaking)
Evidence: injection sweep
Pass: peak < X dB
Supply domains match sensitivity (A / D / OUT)
Evidence: domain map
Pass: Δspur < X dB
Layout
Placement & return-path gate
Clock island exists (keepout + short decap loops)
Evidence: layout markups
Pass: keepout > X mm
Reference planes are continuous (no split-crossing returns)
Evidence: plane review
Pass: no gap in critical path
Connector segment is hardened (CM control + stitching)
Evidence: near-field map
Pass: ΔdB > X
Via fence / stitching forms a real barrier
Evidence: via pitch
Pass: pitch < X mm
Configure
SSC & output policy gate
SSC is segmented by output group (sensitive outputs stay non-SSC)
Evidence: group table
Pass: SSC=OFF for sensitive
depth/rate/profile are validated with A/B gates
Evidence: before/after logs
Pass: ΔdB>X & fail<X/N
Rollback path exists (one-step restore)
Evidence: config snapshot
Pass: recover < X s
Verify
Evidence & statistics gate
Before/after is comparable (same setup, single-variable)
Evidence: test log card
Pass: single-variable = yes
Sample size supports the conclusion
Evidence: N runs
Pass: N ≥ X
Unified pass gate holds (no new dominant spur)
Evidence: spur list
Pass: Top spur < X dBc
Starter BOM (reference materials; verify suffix/package/availability)
The parts below are common starting points for clock power conditioning and EMI hardening. Final choices must be validated using the gates above.
Low-noise LDO (post-reg)
- Analog Devices LT3042
- Analog Devices LT3045
- TI TPS7A4700
- TI TPS7A3301
Buck prereg (upstream)
- TI TPS62130
- Analog Devices LT8609S
Pair with post-LDO + damped local filtering for sensitive rails.
Ferrite bead (local isolation)
- Murata BLM18AG102SN1D (0603 class)
- Murata BLM21PG221SN1D (0805 class)
MLCC decoupling (local)
- Murata GRM188R71C104KA01D (0.1µF, 0603)
- Murata GRM188R60J106ME47D (10µF, 0603)
Damping resistor (anti-peaking)
- Yageo RC0603FR-070R22L (0.22Ω, 0603)
Used as series damping in RC/π networks when impedance peaking shows up in injection sweeps.
Diagram: Stage-gated checklist board (Plan / Layout / Configure / Verify)
Applications & IC selection notes (Supply/EMI-centric)
This section maps application types to supply/EMI requirements and lists selection fields that directly affect conducted coupling, radiated peaks, SSC margin consumption, and observability. It avoids fundamental timing theory and focuses on implementation and selection impact.
A) Application slices (only supply/EMI pain points)
SerDes / PCIe
Dominant risk
Connector-edge common-mode radiation and SSC consuming link margin (training flaps or intermittent lock).
Control points
Segment SSC by output group (sensitive outputs non-SSC). Harden connector segment (stitching, plane continuity, symmetry).
Proof
Near-field ΔdB at failing band + training fail rate < X/N under tagged conditions.
JESD / ADC clocks
Dominant risk
Supply ripple maps into discrete spurs and reduces timing margin even when integrated jitter looks acceptable.
Control points
Identify the sensitive rail band via injection sweep; shape rail impedance with damped local filtering and short decap loops.
Proof
Spur list delta + fixed RJ([fL,fH]) report + stable lock/training statistics.
Video / SDI
Dominant risk
Narrow EMI peaks fail pre-scan; SSC parameter changes can destabilize downstream locking on sensitive paths.
Control points
Enable SSC only on radiating outputs; keep genlock/sync-sensitive outputs non-SSC; enforce connector hardening near the exit path.
Proof
EMI peak reduction > X dB while lock stability holds across operating states.
SyncE / PTP
Dominant risk
Supply-induced events trigger alarms (LOL/missing pulse); connector and shield returns dominate radiated coupling.
Control points
Prefer parts with built-in monitoring/alarms; use rail monitors and stable configuration rollback.
Proof
Alarm counters drop + pre-scan peaks improve with no regression in timing gates.
B) Selection fields (only what directly affects supply/EMI outcomes)
PSRR / sensitivity vs band
Prefer devices that tolerate rail noise in the bands identified by injection sweeps; validate with spur/lock response.
Supply domains & isolation
Look for true A/D/OUT domain separation and pins that allow real impedance shaping near sensitive blocks.
SSC controllability
Require depth/rate/profile control and output grouping so SSC can be enabled only where it reduces radiation without consuming margin.
Output driver control
Adjustable slew/drive strength helps reduce harmonics and edge-driven EMI when it does not violate endpoint timing requirements.
Monitoring & alarms
Missing-pulse / loss-of-lock / rail monitors turn intermittent issues into trackable events and speed up triage.
C) Reference IC examples (clocking parts that commonly support supply/EMI strategies)
These are starting points to speed up datasheet lookup. Confirm output standards, monitoring features, and configuration granularity per SKU.
Jitter cleaners / attenuators
- Silicon Labs Si5341, Si5345
- Silicon Labs Si5391, Si5392
- TI LMK05318
PLL + distribution
- TI LMK04828
- Analog Devices HMC7044
Programmable clock generators (SSC often available)
- Silicon Labs Si5338
- Silicon Labs Si5351
Practical rule
Choose clock ICs that allow output grouping, monitoring, and rollback. Then spend effort on rail impedance shaping and connector-segment hardening; those are the fastest ways to move EMI and intermittent failures.
Diagram: Application → Supply/EMI requirement matrix (card matrix)
Use the matrix to decide where to spend effort first: rail impedance shaping for “Noise High”, connector-segment hardening for “EMI High”, and strict SSC grouping whenever “SSC needs control” appears.
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FAQs (Supply & EMI): fast triage with measurable pass criteria
Each answer is intentionally short and executable: Likely cause → Quick check → Fix → Pass criteria. Fill X/Y using the system budget and keep A/B tests single-variable.
EMI pre-scan fails at a narrow peak: clock harmonic or supply spur?
Expand for 4-line triage (conducted vs radiated vs modulated)
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EMI pre-scan fails at a narrow peak: clock harmonic or supply spur?
Expand for 4-line triage (conducted vs radiated vs modulated)
Likely cause: A discrete spur is being upconverted into radiation (harmonic path) or injected into the clock device rail (conducted path).
Quick check: (1) Near-field probe: does the hot spot sit on the clock trace/connector edge? (2) Rail FFT on the sensitive rail: is there a tone at the same spacing/offset?
Fix: If radiated: harden connector segment (stitching + plane continuity + symmetry) and reduce edge energy (series-R / lower drive). If conducted: add damped local filtering and shorten decap loop.
Pass criteria: Peak at f0 drops by ≥ X dB (same RBW/VBW/probe geometry) and the related rail tone drops by ≥ Y dB (same bandwidth window).
Near-field shows a strong peak, but the phase-noise plot looks clean: what “spur vs window” mismatch is happening?
Expand for spur-centric measurement sanity checks
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Near-field shows a strong peak, but the phase-noise plot looks clean: what “spur vs window” mismatch is happening?
Expand for spur-centric measurement sanity checks
Likely cause: A narrow discrete spur exists outside the PN integration window or is being averaged/smoothed away by settings (RBW/VBW/offset span).
Quick check: Switch to “spur list” mode: narrow RBW, wider span, and mark offsets where EMI peak appears; compare with the jitter window [fL,fH].
Fix: Report both: (1) integrated jitter over [fL,fH], and (2) top-K spurs with offsets and levels; then drive fixes by the dominant spur, not RMS alone.
Pass criteria: Dominant spur at offset Δf is ≤ X dBc (or improves by ≥ Y dB) while RJ([fL,fH]) stays ≤ X fs (fixed window).
Ripple frequency equals spur spacing: confirm DC/DC coupling vs reference leakage within one hour
Expand for “single sweep proves it” steps
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Ripple frequency equals spur spacing: confirm DC/DC coupling vs reference leakage within one hour
Expand for “single sweep proves it” steps
Likely cause: The spur is either (A) rail ripple modulating a sensitive block, or (B) reference/clock leakage creating a deterministic tone at the same spacing.
Quick check: Move one knob at a time: (1) shift DC/DC switching frequency by ΔfSW; (2) change reference frequency by ΔfREF (or disable one reference path).
Fix: If spur tracks fSW: improve rail impedance shaping (damped filter + local decaps). If spur tracks fREF: improve isolation (routing/return control, shielding, reduce coupling area).
Pass criteria: Spur offset follows only one knob (fSW or fREF), and after the fix the spur level reduces by ≥ X dB (repeatable across N runs).
After adding a ferrite bead, the spur gets worse: is the filter resonating?
Expand for resonance detection + damping actions
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After adding a ferrite bead, the spur gets worse: is the filter resonating?
Expand for resonance detection + damping actions
Likely cause: Bead + MLCC creates an impedance peak (anti-resonance) in the sensitive band, amplifying ripple instead of attenuating it.
Quick check: Injection sweep (small-signal) across the rail: look for a peak of ≥ X dB around the spur offset/band; verify with rail FFT before/after.
Fix: Add damping (e.g., small series R such as RC0603FR-070R22L 0.22Ω reference or equivalent), adjust capacitor mix (e.g., GRM188R71C104KA01D 0.1µF + GRM188R60J106ME47D 10µF class), or change bead class (e.g., BLM18AG102SN1D / BLM21PG221SN1D class) to move/dampen the peak.
Pass criteria: Impedance peak reduces to < X dB (relative) and the dominant spur drops by ≥ Y dB across N repeated measurements.
Same clock IC, very different EMI across boards: top three return/plane checks
Expand for the “three checks first” list
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Same clock IC, very different EMI across boards: top three return/plane checks
Expand for the “three checks first” list
Likely cause: Radiated EMI is dominated by return-path geometry and mode conversion, not the clock source itself.
Quick check: Check three items: (1) reference plane continuity under the clock route; (2) any plane split crossing (return detour); (3) stitching density near connector/edge.
Fix: Restore continuous reference, add via stitching/edge fence, and remove asymmetries (length/impedance/connector pin mapping) that convert differential energy into common-mode.
Pass criteria: Hot-spot near-field level at failing band reduces by ≥ X dB and far-field/pre-scan peak reduces by ≥ Y dBµV with identical setup.
After splitting grounds, jitter gets worse: prove “split-crossing return” quickly
Expand for the fastest “proof-by-bridge” test
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After splitting grounds, jitter gets worse: prove “split-crossing return” quickly
Expand for the fastest “proof-by-bridge” test
Likely cause: The split forces return currents to detour, increasing loop area and converting noise into timing modulation.
Quick check: Temporary “bridge test”: add a controlled ground bridge (copper tape / short braid) near the crossing point and re-measure spur/jitter and near-field hot spot.
Fix: Remove critical split crossings; keep planes continuous under clock routes; if separation is needed, control the bridge at the quiet boundary (single, intentional return path).
Pass criteria: With the proper return path, dominant spur reduces by ≥ X dB and RJ([fL,fH]) improves by ≥ Y% (or ≤ X fs) across N repeats.
SSC OFF makes the link stable, but EMI fails: the smallest change to enable SSC only on some outputs
Expand for output-group SSC strategy + rollback
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SSC OFF makes the link stable, but EMI fails: the smallest change to enable SSC only on some outputs
Expand for output-group SSC strategy + rollback
Likely cause: SSC reduces narrow-peak EMI, but the modulation consumes margin on sensitive endpoints (PLL/CDR tolerance).
Quick check: Identify which outputs radiate (connector segment) vs which outputs are margin-sensitive (training/lock). A/B test: SSC only on the radiating group.
Fix: Use output grouping: keep sensitive outputs non-SSC; enable SSC only on the external/radiating outputs; start with conservative depth/rate and log the change set for rollback.
Pass criteria: EMI peak reduces by ≥ X dBµV while link failure rate stays ≤ Y/N (same temperature/state), and rollback restores baseline within X s.
Routing away from the connector improves EMI but jitter gets worse: where did impedance/reflection get introduced?
Expand for reflection + return-plane sanity checks
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Routing away from the connector improves EMI but jitter gets worse: where did impedance/reflection get introduced?
Expand for reflection + return-plane sanity checks
Likely cause: Added length/branches/vias or a reference-plane discontinuity increased reflection and mode conversion, degrading timing quality at the endpoint.
Quick check: TDR or fast-edge probe at the endpoint: identify reflection steps; verify consistent reference plane under the new route and no stubs at tees.
Fix: Remove stubs, restore controlled impedance, add proper termination, and ensure continuous reference; if needed add small series-R at the driver to tame edge energy without violating timing.
Pass criteria: Reflection amplitude reduces to < X% of swing (or < Y mV) and RJ([fL,fH]) returns to ≤ X fs (same window).
Lower drive strength improves EMI, but some ports intermittently fail training: the first margin check
Expand for endpoint margin validation steps
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Lower drive strength improves EMI, but some ports intermittently fail training: the first margin check
Expand for endpoint margin validation steps
Likely cause: Reduced slew/drive lowered EMI but also reduced timing/edge margin at the receiver (threshold crossing and jitter tolerance).
Quick check: At the receiver, measure edge rate and eye/threshold margin under worst-case load/temperature; compare “training fail” ports vs “pass” ports.
Fix: Keep reduced drive on radiating outputs only; for sensitive ports restore drive or add controlled termination/impedance cleanup to recover margin without re-introducing peaks.
Pass criteria: Receiver edge/eye margin ≥ X% (or ≥ Y ps) and training fail rate ≤ X/N while EMI peak remains improved by ≥ Y dBµV.
LDO noise is very low, but the system is still bad: how to check “ground bounce / output current pulsation” paths
Expand for OUT-rail and return-path checks
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LDO noise is very low, but the system is still bad: how to check “ground bounce / output current pulsation” paths
Expand for OUT-rail and return-path checks
Likely cause: Timing is modulated by ground/return impedance and output-driver current pulses, not by DC rail noise at the LDO output pin.
Quick check: Probe close to the output-driver supply/return loop (OUT rail + local ground) with short ground spring; compare to LDO output pin measurement.
Fix: Shorten the output-driver decap loop, strengthen local return (stitch vias), and if needed isolate domains (A/D/OUT). For sensitive rails, a post-reg LDO class (e.g., LT3042/LT3045/TPS7A4700/TPS7A3301) can help only if the loop/return is correct.
Pass criteria: Local OUT-rail ripple at the driver loop reduces by ≥ X% (or ≥ Y mVrms) and dominant spur/jitter improves by ≥ X dB (or ≤ X fs).
EMI or lock gets worse only at hot/cold: what two rails / which monitor should be logged first?
Expand for minimal logging set (temperature correlation)
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EMI or lock gets worse only at hot/cold: what two rails / which monitor should be logged first?
Expand for minimal logging set (temperature correlation)
Likely cause: Temperature shifts rail headroom/impedance and changes coupling, pushing the system over a margin edge (lock/EMI).
Quick check: Log (1) sensitive analog rail (VCO/PLL_A) ripple and DC level, and (2) output-driver rail (OUT) ripple; also log device status: LOL/LOS/missing-pulse/alarm counters.
Fix: Increase worst-case headroom, stabilize rail impedance vs temperature (damping + capacitor mix), and ensure alarms are enabled to correlate events with rail/temperature.
Pass criteria: Across the temperature range, rail DC margin ≥ X mV, ripple ≤ Y mVrms in the sensitive band, and alarm rate ≤ X/N.
After “changing the filter”, results aren’t comparable: eliminate bandwidth/RBW/probe-ground fake improvements
Expand for measurement normalization checklist
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After “changing the filter”, results aren’t comparable: eliminate bandwidth/RBW/probe-ground fake improvements
Expand for measurement normalization checklist
Likely cause: Instrument settings or probe grounding changed the measurement transfer function, producing a false delta.
Quick check: Freeze settings: same RBW/VBW/span/averaging, same probe type/ground spring, same probe height/location; take “before” and “after” back-to-back.
Fix: Create a measurement card: settings snapshot + photos + exact coordinates; only accept deltas that reproduce across ≥ N runs with the same geometry.
Pass criteria: Improvement ≥ X dB (or ≥ Y dBµV) repeats across ≥ N runs with identical setup; no new dominant peak appears within the target band.
