EMI & SSC (Spread-Spectrum Clocking) for Timing Clocks
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SSC is a peak-EMI tool, not a free EMI win: it reshapes spectral energy and can break sensitive clock chains if applied blindly. This page turns SSC into an engineering loop—choose depth/rate/profile and enable points, validate with A/B + pass criteria, and partition clocks so EMI improves without sacrificing system stability.
Focus: parameters, insertion points, partitioning, and measurable pass/fail gates.
Scope & non-scope (EMI peak control vs clock-chain integrity)
Spread-Spectrum Clocking (SSC) is a peak-EMI shaping tool: it reduces narrow discrete clock harmonics by distributing energy over a small band. It does not guarantee “all EMI goes down”—the noise floor or sidebands can rise, and clock-sensitive endpoints may lose margin.
- Parameterization: spread depth, modulation rate, and profile (when available).
- Enable placement: where SSC is injected in the chain (source / cleaner / fanout / per-domain).
- Sensitivity classification: which endpoints are typically safe / verify / default-off.
- Verification: EMI peak delta plus clock-link health (lock events, periodic errors, margin).
- Phase-noise integration to RMS jitter budgets: Key Specs & Selection (this page only consumes the final limits as pass/fail inputs).
- PLL loop stability / bandwidth math: Jitter Attenuators / PLL (this page focuses on enable placement and verification outcomes).
- Interface rulebooks (JESD204/PCIe/SyncE): Interface-Focused Clocks (this page provides a practical decision flow, not protocol clauses).
Engineering rule (keeps SSC changes predictable)
- Change one variable at a time (only depth, only rate, or only enable point).
- Record two outputs: EMI peak delta + link health (lock/BER/CRC/periodic anomalies).
- If failures are periodic, correlate timestamps to the modulation rate (or its harmonic) before chasing random noise.
What SSC really changes (frequency/phase trajectory, not “random jitter”)
SSC introduces a low-frequency modulation that makes the clock’s instantaneous frequency sweep over a small range. In the spectrum, a tall narrow harmonic peak is redistributed into a wider band: peak drops, while sidebands / noise floor may rise. Treat SSC as deterministic modulation first; only then consider it through “jitter-like” symptoms.
Down-spread (common in practice)
- Instantaneous frequency shifts downward from nominal.
- Often easier to satisfy “do not exceed maximum refclk” constraints.
- Good starting point for peak-EMI reduction on non-sensitive branches.
Center-spread (verify carefully)
- Frequency sweeps above and below nominal.
- Can stress both sides of frequency tolerance windows.
- May shift risk from “peak EMI” to “tolerance/lock margin” if overused.
- Random-looking errors often track power/thermal/noise sources.
- Periodic errors (frame slips, training retries, sync jumps) often correlate to the SSC modulation rate (or its harmonic).
- If a failure disappears when SSC is disabled (with all else unchanged), treat SSC as the primary variable and proceed with single-variable A/B.
Verification checklist (minimum set)
EMI instruments: spectrum / EMI receiver
- Confirm the targeted harmonic peak becomes a wider band.
- Measure peak delta at the prior worst frequency.
- Scan neighbors: ensure the fix did not “move” the problem into another constrained band.
Clock/link health: lock + error logging
- Log lock/unlock events and error counters with timestamps.
- If anomalies are periodic, align the interval to the modulation rate (or its harmonic).
Pass criteria template: (1) EMI: peak reduction ≥ X dB at worst harmonic and no new exceedance bands; (2) Link: no new lock loss / no periodic error bursts under the same operating conditions.
Parameters that matter (Depth · Rate · Profile)
SSC is not a binary switch. Three knobs determine how energy is redistributed in frequency and how much tolerance is consumed downstream: spread depth sets the maximum instantaneous frequency deviation, modulation rate sets where the deterministic sweep lives in the low-frequency domain, and profile shapes sideband structure and repeatability. The engineering goal is to maximize EMI peak reduction without collapsing link margin.
- Larger depth typically improves peak reduction by spreading harmonics over a wider band.
- Larger depth also increases instantaneous frequency deviation, reducing margin for endpoints and tracking loops.
- Safe sweep: start from a small depth, increase until diminishing EMI returns or link symptoms appear.
Symptom fingerprint: depth-induced issues often appear as loss-of-lock, repeated training, or margin shrink under temperature/voltage corners.
- Too low: the sweep can land in system-sensitive bands (control loops, audio/video artifacts, sampling-window interactions), creating periodic anomalies.
- Too high: the spread can be less effective for a given measurement setup, or stress tracking behavior in some paths.
- Diagnostic rule: if anomalies are periodic, correlate the interval to the modulation rate (or its harmonic) before chasing random noise.
Safe sweep: pick a candidate rate away from known sensitive bands, then adjust rate while holding depth/profile fixed.
- Triangle / sawtooth sweeps can produce different sideband structures even at the same depth/rate.
- Pseudo-random profiles may reduce visible “comb” patterns, but do not assume improved compatibility without verification.
- Single-variable rule: when changing profile, keep depth and rate constant to preserve attribution.
When to try another profile: peak improves but new narrow spurs/sidebands appear, or periodic artifacts become visible.
Minimum record (enables fast iteration)
- SSC setting: depth (%), rate (kHz), profile.
- Enable point: source / clean out / fanout branch.
- EMI: worst harmonic frequency and peak delta (dB).
- Link: BER/CRC, lock/unlock count, periodic anomalies (yes/no).
- Conditions: temp/voltage/load state for reproducibility.
Keep a single-variable sweep sequence (only depth, only rate, or only profile) to preserve attribution.
Where SSC is allowed vs forbidden (enable placement strategy)
SSC placement defines the blast radius. A safe start is enabling SSC only on SSC-friendly branches and keeping sampling/alignment-critical chains clean. When SSC is necessary in a tracking path, verification must prove that the receiver can tolerate the deterministic sweep without periodic faults.
- System / MCU clocks and non-synchronous branches with generous frequency tolerance.
- Board-level clocks that dominate radiated peaks and are not used for sampling alignment.
- Preferred placement: per-branch enable (localize modulation instead of global injection).
- Paths where the receiver must track the deterministic sweep.
- High risk of periodic training retries, frame slips, or lock oscillation if margin is tight.
- Required approach: single-variable A/B at fixed depth/rate/profile and timestamped error logging.
- ADC/DAC sampling clocks (especially RF/high-IF): deterministic sweep directly consumes timing margin and can create artifacts.
- JESD204 subclass alignment chains (SYSREF/LMFC): phase-relationship and alignment windows are sensitive to low-frequency modulation.
- SerDes refclks when SSC support is not guaranteed for the specific device/mode.
- Precision sync chains (e.g., SyncE-style references): enable only with strict system validation and alarms.
Enable-point A/B procedure (segment-by-segment)
- Fix SSC settings (depth/rate/profile) and vary only the enable point.
- Start from a green branch; measure EMI peak delta at the prior worst harmonic.
- Log lock/unlock + error counters with timestamps (BER/CRC/frame events).
- If failures are periodic, shift SSC to a more localized branch (reduce blast radius) before adjusting depth/rate.
- Freeze a safe default configuration; keep field knobs within validated guardbands.
Risk taxonomy (why SSC can break systems)
SSC failures are rarely “EMI problems.” Most are deterministic interactions between the frequency sweep and system margins. Classifying symptoms into a small set of failure modes prevents blind tuning and makes verification repeatable.
Universal first action (do this before tuning)
- Freeze variables: keep depth/rate/profile fixed and change only one factor at a time (enable point OR one knob).
- Timestamp logs: lock/unlock events, error counters (BER/CRC), sync alarms, and operating state.
- Check periodicity: if anomalies repeat, correlate the interval to the modulation rate (or its harmonic).
- Symptoms: loss-of-lock, retraining, or sudden margin collapse at corners (temp/voltage/link loss).
- Root cause: depth-driven sweep pushes refclk outside tolerable instantaneous offset.
- First probe: SSC OFF A/B with identical conditions; then reduce depth or localize SSC to a branch.
- Symptoms: periodic lock oscillation, bursty errors, repeated training cycles.
- Root cause: tracking loop cannot follow the deterministic sweep under current depth/rate.
- First probe: align event timestamps to the modulation rate; sweep rate while holding depth/profile fixed.
- Symptoms: periodic error bursts, audible tones, periodic video jitter or frame anomalies.
- Root cause: modulation rate lands in a sensitive band and “beats” against system timing rhythms.
- First probe: compute anomaly period; sweep rate (only rate) and confirm the period shifts accordingly.
- Symptoms: domain-local checks pass, but cross-domain alignment fails intermittently.
- Root cause: inconsistent modulation policy creates relative drift between domains.
- First probe: build an “SSC matrix” (which domain spreads); A/B by unifying policy or partitioning.
Decision flow (repeatable engineering checklist)
The flow below prevents scope creep and reduces risk: SSC targets peak EMI, then validates device/mode support, classifies sensitivity, selects the smallest blast radius enable point, and closes with controlled A/B validation.
Step 1 — Confirm the problem is peak EMI
- Target: narrow harmonic peaks or discrete exceedance bands.
- If the issue is broadband floor/noise, treat SSC as non-primary and keep scope on EMI system-level work.
Step 2 — Check whether the chain is allowed to spread
- If device/mode does not support SSC: disable SSC on that path.
- If SSC is required for EMI: use partition + re-shape to keep sensitive endpoints clean.
Step 3 — Classify sensitivity (Green / Yellow / Red)
- Green: system clocks, wide tolerance → preferred SSC candidates.
- Yellow: tracking-dependent paths → verify with timestamped logs.
- Red: sampling/alignment/sync critical → default OFF unless proven.
Step 4 — Choose the enable point (minimize blast radius)
- Prefer per-branch SSC at fanout outputs when possible.
- Avoid global injection at the source unless all downstream endpoints tolerate modulation.
- If cross-domain alignment exists, keep policy consistent or isolate domains.
Step 5 — Define a controlled sweep plan (single variable)
- If anomalies are periodic: sweep rate first to move away from sensitive bands.
- If failures look threshold-like (sudden lock loss): reduce depth first.
- Change profile only after depth/rate are bounded.
Step 6 — A/B validation (EMI + function)
- EMI: peak delta at the prior worst harmonic and scan adjacent bands.
- System: lock/unlock counts, BER/CRC, sync alarms with timestamps.
- If it fails: prefer partition + re-shape rather than global SSC.
Deliverable outcomes: (1) ENABLE with validated guardbands; (2) DISABLE on sensitive paths; (3) PARTITION + RE-SHAPE (SSC branch for EMI, clean branch for sampling/sync).
Partitioning strategy (SSC domain vs clean domain)
In complex clock trees, “disable SSC on sensitive chains” typically means partitioning: keep SSC on the EMI-friendly branch, while preserving a clean branch for sampling, SerDes, and synchronization. Isolation/re-shaping devices are placed between the branches to prevent deterministic modulation from leaking into performance-critical endpoints.
Practical rules (strategy-only, no formulas)
- EMI-friendly branch: enable SSC where peak EMI is the constraint (digital clocks, general-purpose references).
- Performance branch: keep SSC OFF for sampling clocks, alignment-critical timing, and sensitive refclk consumers.
- Isolation / re-shaping: place a cleaner/PLL/retiming stage so modulation does not propagate into the clean domain.
- Blast-radius control: prefer per-branch SSC enable (fanout output level) over global injection at the source.
Trade-offs (the cost of partitioning)
- BOM & power: extra buffers/cleaners and their supply filtering.
- Latency & alignment: added delay through re-shaping blocks increases cross-domain alignment complexity.
- Validation scope: both domains must run simultaneously under corners (temperature/voltage/load).
Partitioned verification (two KPIs must pass)
- EMI domain: peak delta meets target at the original worst harmonic (and neighbor bands).
- Clean domain: jitter/spur and lock stability remain within system limits while the EMI domain is active.
Measurement plan (EMI result + clock-chain health)
SSC is successful only if it delivers a repeatable peak EMI reduction without harming lock stability or increasing functional errors. The plan below standardizes what to measure, what to log, and how to iterate with single-variable changes.
Track A — EMI (peak-focused)
- Peak delta (dB): compare SSC OFF vs ON at the original worst harmonic.
- Neighbor bands: check skirts/sidebands around the original peak (peak can flatten while skirts rise).
- Repeatability: run multiple sweeps and confirm consistent deltas (avoid one-off “good” captures).
Track B — System / link health (timestamped)
- Error metrics: BER/CRC, frame errors, retraining events.
- Lock stability: lock/unlock counts with timestamps.
- Corner stress: temperature/voltage disturbances and load transitions (record conditions).
- Periodicity check: if errors are periodic, correlate event intervals to the modulation rate (or harmonics).
Minimum logging template (to enable repeatable decisions)
- SSC settings: depth / rate / profile.
- Enable point: source / cleaner output / fanout branch.
- Hardware context: board revision + clock-tree variant.
- Test conditions: temperature, supply, cables, load state.
- EMI result: worst peak frequency + peak delta + neighbor band notes.
- Health result: errors/lock events with timestamps.
Decision + iteration (single-variable rule)
- Change one variable per iteration (enable point OR one knob).
- Periodic issues: adjust rate first; threshold-like failures: reduce depth first.
- When both tracks pass, freeze a default configuration and document guardbands.
Pass criteria (what “SSC success” means)
SSC is successful only if all criteria pass: peak EMI improves without relocating failures, link health remains within limits without rate-synchronous anomalies, and robustness holds across temperature/voltage/load corners. Use the placeholders below to plug in project-specific thresholds.
A) EMI (peak + no relocation)
- Peak reduction: worst peak at the key frequency improves by ≥ X dB (X = compliance or mitigation target).
- No relocation: neighbor bands and related bands must not create a new exceedance (peak cannot “move” to another limited region).
- Repeatability: multi-sweep delta remains consistent under identical setup.
B) Link / function (errors + lock stability)
- Errors: BER/CRC/frame errors are 0 or ≤ LIMIT (LIMIT = system error budget per interval).
- Lock events: lock/unlock or retraining events are 0 or ≤ LIMIT.
- No periodicity: no anomaly is time-synchronous to the modulation rate (or its harmonics).
C) Robustness (corners + disturbance)
- Temperature: criteria A/B still pass at cold/hot endpoints of the operating range.
- Voltage: criteria A/B still pass under supply disturbances within the defined limits.
- Load/state: criteria A/B still pass during load transitions and state changes.
Threshold placeholder method (how to fill X / LIMIT)
- X dB: set by mitigation target (margin needed to pass compliance with guardband).
- LIMIT: set by system error budget per test interval (use the same interval across A/B runs).
- Corner limits: define temperature/voltage/load ranges before testing, then keep them fixed across iterations.
Common pitfalls (why SSC can make things worse)
Most SSC failures come from wrong insertion points and unbounded knobs. Use the checklist below to avoid predictable mistakes: localize SSC, bound depth, sweep rate away from sensitive bands, keep cross-domain policy consistent, and never judge EMI by peak-only.
Pitfall 1 — SSC enabled on performance chains
- Why it hurts: deterministic modulation enters sampling/sync endpoints and reduces margin.
- Fix: partition + re-shape; keep a clean branch for sensitive consumers.
- Quick check: A/B by enable point only (no knob changes).
Pitfall 2 — Depth too large (instant deviation exceeds tolerance)
- Why it hurts: larger depth increases instantaneous offset and triggers tracking/tolerance limits.
- Fix: bound depth by system margin; localize SSC instead of increasing depth globally.
- Quick check: reduce depth while holding rate/profile constant; watch for threshold-like recovery.
Pitfall 3 — Modulation rate lands in a sensitive band (beating)
- Why it hurts: rate can beat with sampling windows, frame cadence, or control loops → periodic artifacts.
- Fix: keep depth/profile fixed and sweep rate to avoid sensitive regions.
- Quick check: anomaly period shifts with rate (strong fingerprint).
Pitfall 4 — Inconsistent SSC policy across clock domains
- Why it hurts: relative drift grows between domains and breaks cross-domain alignment.
- Fix: unify SSC policy or isolate domains with partitioning.
- Quick check: build an SSC matrix; unify settings and compare cross-domain stability.
Pitfall 5 — Peak-only EMI judgement (skirts cause new failures)
- Why it hurts: peak can drop while skirts/neighbor bands rise, relocating exceedance.
- Fix: always check neighbor bands + repeatability, not only the single peak.
- Quick check: compare multiple sweeps and track neighbor-band deltas.
Engineering checklist (Design / Bring-up / Production)
SSC is an engineering control loop: it must be observable, switchable, and rollback-safe. The checklist below is organized by lifecycle stage to prevent “EMI win, system loss”.
A) Design stage — make SSC controllable
- Grade every consumer: classify endpoints as Green (allowed), Yellow (validate), Red (default forbidden).
- Reserve enable granularity: per-output / per-domain enable is preferred; avoid “global-only” SSC when possible.
- Reserve partition slots: leave footprint options for a clean branch (bypass/clean output path or an isolation device).
- Expose probe points: source → after generator/cleaner → after fanout → near sensitive endpoints (at least one node per segment).
- Add health hooks: missing-pulse / frequency offset / lock status / error counters must be readable by firmware.
- Guarantee rollback: any SSC-ON policy must have a fast SSC-OFF fallback path (strap, register, or mux).
B) Bring-up — single-variable A/B + timestamped evidence
- Single-variable rule: change only one knob (depth/rate/profile) or one enable point per run.
- Lock the template: record {depth, rate, profile, enable point, board rev, conditions, EMI delta, error counters}.
- Timestamp anomalies: lock/unlock, retraining, CRC spikes, frame slips—always log time for rate-correlation.
- Fingerprint periodicity: treat any anomaly synchronous to modulation rate (or harmonics) as fail-until-proven-safe.
- Localize first: prefer enabling SSC on EMI-friendly segments before expanding scope.
C) Production — freeze safe defaults, bound field tuning
- Default policy: SSC enabled only on the EMI-friendly branch; sensitive chains remain SSC-OFF by default.
- Guardband limits: hard-limit field-adjustable depth/rate ranges (max depth, allowed rate window, fixed profile).
- Rollback strategy: define a deterministic fallback (SSC-OFF or clean-output selection) for any field issue.
- Version binding: tie SSC configuration to board revision and BOM variant to avoid mis-application.
- Feedback loop: collect counters + environment metadata to improve the next default policy.
Concrete BOM hooks (for controllability and bring-up)
Part numbers below are reference materials for typical strap/decap/test needs. Verify package, voltage rating, dielectric, and approved vendor list.
- 0 Ω option link (0402): Panasonic ERJ2GE0R00X (strap/rollback routing options).
- 10 kΩ pull resistor (0402, 1%): Yageo RC0402FR-0710KL (enable straps / address straps).
- 0.1 µF decap (0402, X7R): Murata GRM155R71C104KA88D (local supply decoupling near clock IC).
- Bring-up EVK (clock generator): Renesas 5P49V6965-EVK (quick register experiments; not a production BOM item).
Applications & IC selection notes (SSC/EMI-only)
Selection here is restricted to SSC and EMI control: spread mode, max depth, rate/profile, enable granularity, partition-friendly outputs, and health monitoring. Details of jitter-cleaning design belong to the jitter-attenuator / PLL pages.
A) SSC-only selection fields (what matters + why + test hook)
Spread mode: down-spread / center-spread
Why: mode choice sets instantaneous frequency offset direction and tolerance risk. Test hook: confirm register setting + verify sideband shape around the original peak.
Max depth / depth step
Why: larger depth improves peak EMI but increases tolerance/tracking risk. Test hook: hold rate/profile constant, sweep depth, watch for threshold-like lock errors.
Modulation rate range + resolution
Why: rate must avoid sensitive bands (sampling windows, frame cadence, control loops). Test hook: hold depth/profile constant, sweep rate; periodic anomalies shifting with rate indicate beating.
Profile options (triangle / saw / pseudo-random)
Why: profile changes spectral distribution (skirts/sidebands) and can alter neighbor-band risk. Test hook: switch profile under identical depth/rate; compare neighbor bands + system error counters.
Enable granularity (per-output / per-domain) + runtime switching
Why: granularity localizes risk; runtime switching is treated as high-risk unless proven safe. Test hook: A/B by enable point only; log timestamped lock/errors during any switching attempt.
Partition support: bypass/clean outputs + monitoring hooks
Why: partition enables SSC on EMI-friendly branches while keeping sensitive chains clean; monitors catch intermittent failures. Test hook: run dual-domain validation (EMI delta + link health) with unified logging.
B) Typical patterns (restricted to EMI/SSC strategy)
- EMI mitigation first step: enable SSC on non-sensitive clock branches before touching performance clocks.
- Multi-domain systems: partition into SSC domain (EMI goal) and clean domain (performance goal), then validate both gates.
- Knob order: fix insertion point → sweep rate to avoid beating → bound depth within tolerance → lock profile.
C) Reference material numbers (SSC/EMI-focused starting points)
These part numbers are provided to speed up datasheet lookup and bring-up. Selection must be driven by the SSC-only field list above. Verify output standard (LVCMOS/LVDS/HCSL), spread mode, max depth/rate, and package/suffix.
Programmable clock generators with SSC capability (general platform clocks)
- Renesas: 5P49V6965A000NLGI (VersaClock 6E programmable clock generator).
- Skyworks / Silicon Labs: Si5338 (any-rate, any-output programmable clock generator).
- Renesas: 9FGV1002 (PhiClock family; spread-spectrum copies + reference copies).
PCIe clock generators (commonly used for selectable spread levels)
- Renesas: 9FGV0631 (PCIe Gen1–4 clock generator family member).
- Renesas: 9FGV0641 (PCIe Gen1–4 clock generator family member).
- Microchip: ZL30282 (6-output PCIe clock generator).
Programmable MEMS clock generator (configurator-based material numbering)
- Microchip: DSA613 (factory-configured MEMS clock generator; final orderable code depends on configuration tool).
Note: configurator-based families generate the final orderable suffix from output type, frequencies, stability, and options.
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FAQs (EMI & SSC troubleshooting)
All answers follow the same 4-line, actionable structure: Likely cause / Quick check / Fix / Pass criteria. Scope is strictly limited to SSC knobs (depth/rate/profile), enable point, partitioning, and pass/fail gates.
Peak EMI drops after SSC, but another band fails—why?
Likely cause: SSC redistributed energy (skirts/sidebands) and “relocated” the problem into a different limited region.
Quick check: Compare full sweep traces (same setup) around the original peak and neighboring bands; confirm the new exceedance tracks SSC settings.
Fix: Reduce depth, adjust rate/profile, or localize SSC to the EMI-friendly branch; avoid enabling SSC on chains that couple into the failing band.
Pass criteria: Key peak improves by ≥ X dB and no new exceedance appears in any monitored neighbor band (repeatable across ≥ 3 sweeps).
Same depth, different modulation rate—why do periodic errors start?
Likely cause: The SSC rate landed in a system-sensitive band, creating beating with sampling windows, frame cadence, or control loops.
Quick check: Change only the SSC rate and verify the error periodicity shifts with it (strong fingerprint).
Fix: Sweep rate to find a “quiet window”, then re-tune depth only after rate is parked; keep enable point unchanged during the sweep.
Pass criteria: Error counters stay ≤ LIMIT and no rate-synchronous anomaly is observed over ≥ T hours.
Works on the bench, but fails in the chassis/long cables when SSC is on—why?
Likely cause: System-level coupling (return path changes, additional aggressors, supply/ground noise) reduced margin; SSC pushed tracking/tolerance over the edge.
Quick check: A/B SSC OFF vs ON with identical conditions; log lock/unlock counters + timestamps and compare short vs long interconnect.
Fix: Localize SSC to EMI-friendly branches, reduce depth, shift rate, and/or partition (clean branch for sensitive endpoints).
Pass criteria: Zero (or ≤ LIMIT) lock events across the worst-case cable/chassis configuration, while EMI gate remains met (≥ X dB at target peaks).
A device claims SSC support, but training still fails—what is the first check?
Likely cause: “Supports SSC” often means only specific mode/depth/rate windows; the current configuration exceeds that window or is applied at the wrong insertion point.
Quick check: Confirm spread mode (down/center), max depth, allowed rate/profile from the receiving device constraints; verify actual register settings match the intended configuration.
Fix: Start from the most conservative SSC setting (min depth, safe rate, fixed profile), then expand one knob at a time under A/B logging.
Pass criteria: Training passes repeatedly (≥ N cycles) with stable counters, while EMI improvement remains measurable (≥ X dB).
Enable SSC at the source or after the cleaner—how to decide fastest with A/B?
Likely cause: The insertion point determines blast radius—SSC placed too upstream can contaminate sensitive chains that should stay clean.
Quick check: Hold depth/rate/profile constant; toggle only the enable point (source vs post-cleaner) and log EMI delta + lock/error counters.
Fix: Choose the point that achieves EMI target while keeping sensitive endpoints on a clean branch (often via partitioning or per-output enable).
Pass criteria: Both gates pass: EMI ≥ X dB improvement and link counters ≤ LIMIT (no rate-synchronous events).
Errors are periodic (not random) after SSC—what class of “beating” is most likely?
Likely cause: Deterministic modulation is interacting with a periodic system process (sampling window, frame boundary, control loop cadence, or cross-domain alignment).
Quick check: Change only SSC rate; if the periodicity tracks the rate (or a harmonic), beating is confirmed.
Fix: Move rate away from sensitive bands, unify SSC policy across related domains, or partition to keep sensitive chains clean.
Pass criteria: No periodic artifact remains over ≥ T hours and counters remain ≤ LIMIT at worst-case conditions.
Why is down-spread more common? When is center-spread better?
Likely cause: Down-spread avoids upward frequency excursions that can violate an upper-tolerance edge; center-spread swings both directions and can stress margins on both sides.
Quick check: Compare min/max instantaneous frequency (effective tolerance usage) and link stability under identical depth/rate for both modes.
Fix: Prefer down-spread by default; use center-spread only when both-side tolerance is proven and it reduces EMI without neighbor-band failures.
Pass criteria: Selected mode meets EMI gate (≥ X dB) and link gate (≤ LIMIT, no periodicity) across corners.
Depth too small does nothing; too large breaks things—how to find the sweet spot?
Likely cause: EMI benefit scales with depth, while system risk often has a threshold (tolerance/tracking limit) that appears suddenly.
Quick check: Fix enable point + rate + profile; sweep depth in small steps and chart {EMI peak delta, counters, lock events}.
Fix: Choose the lowest depth that meets EMI target with guardband; if EMI target cannot be met safely, localize SSC or partition instead of increasing depth globally.
Pass criteria: EMI ≥ X dB and link metrics ≤ LIMIT with ≥ G% margin to observed failure threshold.
Some clock domains have SSC and others don’t—cross-domain alignment breaks. How to locate it?
Likely cause: Relative drift increases between domains due to inconsistent SSC policy; CDC/phase relationships that assumed static clocks become invalid.
Quick check: Temporarily unify SSC policy (all OFF, then controlled ON) and observe whether alignment errors disappear; check if errors correlate with SSC rate.
Fix: Unify SSC settings across coupled domains or isolate with a clean domain for alignment-critical paths (partition + re-shape).
Pass criteria: Cross-domain alignment errors remain 0 (or ≤ LIMIT) over ≥ T hours and across corners.
EMI improves, but audio/video shows low-frequency wobble/stripes—how to confirm SSC rate is the cause?
Likely cause: The SSC modulation rate is coupling into a baseband-sensitive process (audio PLL, video timing, frame cadence), creating visible/audible low-frequency artifacts.
Quick check: Change only SSC rate; if the artifact frequency/period shifts accordingly, the rate is implicated.
Fix: Move rate away from the sensitive band or disable SSC on the affected clock chain; keep SSC limited to non-sensitive branches.
Pass criteria: No audible/visible artifact over ≥ T hours while EMI and link gates still pass (≥ X dB, ≤ LIMIT).
Switching SSC ON/OFF causes glitches or short pauses—how to do safe switching/rollback?
Likely cause: Runtime SSC switching introduces a transient that forces re-lock/retraining or violates a timing assumption during the transition.
Quick check: Correlate the pause with lock/unlock flags and error counters at the switch moment (timestamped).
Fix: Switch only in a defined safe window (idle state), or route through a glitch-free mux/clean branch; keep a one-command rollback to SSC-OFF or clean output.
Pass criteria: No functional interruption beyond X ms and no burst of errors/lock events during ≥ N repeated switch cycles.
How to lock SSC into production-safe limits but still allow field tuning?
Likely cause: Unbounded field tuning can push depth/rate into a beating band or beyond tolerance/tracking margins, causing intermittent failures.
Quick check: Verify firmware enforces hard limits: max depth, allowed rate window, fixed profile, and controlled enable points (no hidden overrides).
Fix: Define guardbanded ranges (Depth ≤ Dmax, Rate ∈ [R1,R2], Profile fixed), require rollback capability, and bind configuration to board/BOM revision.
Pass criteria: Field tuning cannot exceed bounds and remains stable (≤ LIMIT) across corners; rollback restores stability immediately if limits are violated.
