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PCIe PHY/SerDes Engineering: EQ, Jitter & SRIS/SRNS

PCIe PHY/SerDes Engineering: EQ, Jitter & SRIS/SRNS

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This page turns PCIe PHY/SerDes bring-up into an executable workflow: build a channel + jitter + clocking (SRIS/SRNS/common) budget, map symptoms to measurable observables, then converge EQ/training with clear pass/fail criteria.

Outcome: fewer “mystery” link failures—each decision is tied to a check, a knob, and a quantified acceptance window (X/Y) that survives lab-to-backplane and temperature-to-traffic changes.

One-line Takeaway + Scope Map (PCIe PHY/SerDes)

Turn PCIe PHY/SerDes bring-up into an executable loop: budget → clocking choice → EQ/training → measurable pass criteria.
The focus is engineering closure: repeatable decisions, observable checkpoints, and verifiable margins for boards and backplanes.
In-scope (this page covers)
  • PHY/SerDes anatomy: PCS vs PMA, TX/RX blocks, and where the knobs live.
  • Budget fields & metrics: channel loss, jitter tolerance, lane skew/deskew, and margin definition (X/Y placeholders).
  • Clocking choices: Common Clock vs SRNS vs SRIS, plus engineering consequences and required observables.
  • EQ & training: presets/coefficients, adaptation boundaries, and when firmware overrides are needed.
  • Bring-up playbook: symptom → first check → fix path → pass criteria, using counters and margining hooks.
Out-of-scope (handled by sibling pages)
  • Retimer/Redriver selection & internals: only a “when-to-use” gate is stated here; details live on the Retimer/Redriver page.
  • Switch/Bifurcation topology planning: routing of lanes/ports and resource slicing are handled on the Switch/Bifurcation page.
  • Cabled PCIe specifics: external cable standards, connector specs, and enclosure design are handled on the Cabled PCIe page.
  • Compliance workflows: test program details belong to the Compliance & Test Hooks page; this page only defines observables and hooks.
Cross-scope rule: this page defines methods, metric definitions, and debug order. Protocol-module specifics stay on their sibling pages (linked below).
What this page delivers (engineer-usable outputs)
  • Budget Fields Sheet: loss/jitter/ppm/deskew fields with pass-criteria placeholders.
  • Knob-to-Symptom Map: which block and which knob to touch first for each failure pattern.
  • Clocking Decision Card: Common vs SRNS vs SRIS, and what observables must be checked.
  • Bring-up Decision Tree: train/fail/flap/under-load/temp branches with first checks.
  • 3-Gate Checklist: Design → Bring-up → Production acceptance gates.
Sibling pages (links only; no expansion here)
  • Retimer/Redriver — long-channel cleanup & re-timing decisions.
  • Switch/Bifurcation — topology, lane fan-out, ACS/ARI, bandwidth slicing.
  • Cabled PCIe — external extensions, hot-plug, end-to-end SI budgeting.
  • Compliance & Test Hooks — loopback/PRBS/margining workflows and compliance prep.
  • Controller / Endpoint / Root Complex — LTSSM ownership and system integration.
Scope Solar Map Center node is PCIe PHY/SerDes; surrounding nodes are sibling pages linked by dotted lines. PCIe PHY/SerDes EQ Jitter Clocking Retimer / Redriver Switch / Bifurcation Cabled PCIe Compliance / Test Hooks Controller / EP / RC
Scope is intentionally locked: this page focuses on PHY/SerDes engineering closure; sibling topics remain link-only to avoid cross-page overlap.

SerDes PHY Anatomy: PCS vs PMA, TX/RX Block-Level View

The coordinate system for debugging
PCS is where lanes align, buffers absorb clock differences, and training state becomes observable. PMA is where waveforms are shaped, clocks are recovered, and jitter tolerance is realized. Every failure pattern should map to a block boundary and a knob category.
TX knobs (what can be tuned, and what it usually changes)
  • Swing / amplitude: increases eye height, but can amplify EMI and crosstalk sensitivity on dense backplanes.
  • De-emphasis / FIR taps: compensates channel high-frequency loss; over-boost can increase ringing and noise pickup.
  • Presets / coefficients: training-friendly configurations; may require clamping/locking when adaptation becomes unstable.
  • Validation observable: does BER improve without new burst errors under traffic and temperature variation (pass criteria X/Y)?
RX knobs (what adapts, what can overfit, and what to watch)
  • VGA/AGC: lifts small signals, but also lifts noise; use margining/counters to confirm net benefit.
  • CTLE: tilts frequency response for insertion-loss channels; can expose crosstalk if pushed too hard.
  • DFE: cancels post-cursor ISI; can become noise-sensitive (“overfit”) when the channel is unstable over time.
  • CDR/PLL: defines tracking boundary for low-frequency wander and ppm; critical for SRIS/SRNS clocking scenarios.
  • Offset cancel: mitigates comparator bias; a common culprit when scope waveforms look fine but errors persist.
Observables (where the truth shows up first)
  • LTSSM state: indicates whether failure is at detection, training, recovery, or stable operation.
  • Equalization status: shows convergence and whether presets/coefficients are being overridden.
  • Error counters (windowed): CRC/replay/burst patterns must be evaluated with a defined window and denominator.
  • Margining hooks: quantify remaining headroom; use as shared language from bring-up to production.
Boundary reminder: retimer internals, switch topology, and compliance procedures remain on their sibling pages. This section only maps blocks, knobs, and observables.
Quick mapping: symptom → first block to suspect → first check
  • Train fails early → PMA/clock capture → check refclk validity + PLL/CDR lock status.
  • Trains then flaps → margin boundary → correlate errors with temperature/power noise and EQ convergence.
  • Idle OK, traffic fails → noise sensitivity → check burst-error windows, SSO/crosstalk exposure, and DFE stability.
  • Width downshifts → lane skew/one-lane collapse → check per-lane counters + deskew buffer pressure.
PCIe SerDes Block Diagram Diagram shows PCS and PMA regions, TX FIR, channel discontinuities, RX CTLE/DFE/CDR, and observation points. PCS PMA TX FIR Channel RX CTLE DFE CDR Observables LTSSM EQ status Counters Margining
Use this block map to bind every symptom to a knob category and an observable, before touching training presets or layout assumptions.

Channel & Loss Budget: From Stackup to Backplane

Budget fields (fill-in sheet, numeric thresholds as X/Y placeholders)
A stable link is usually limited by channel loss and discontinuities before any advanced EQ tuning. Use the following fields to keep analysis consistent across boards, backplanes, and revisions (avoid hard-coded spec numbers).
  • IL(f): insertion loss vs frequency (track low/mid/high bands; watch slope and notches).
  • RL(f): return loss vs frequency (identify discontinuities and reflection bands).
  • NEXT/FEXT: near/far-end crosstalk (routing density zones, connector fields, backplane regions).
  • Via stubs: stub length / backdrill status (resonant notches and ripple risk).
  • Connector discontinuity: pin-field transitions, breakout geometry, impedance steps.
  • Skew: lane-to-lane skew (deskew buffer pressure) and intra-pair skew (mode conversion risk).
  • Return-path breaks: reference plane gaps, stitching via density, layer transitions.
Output format: keep a single spreadsheet-style view (fields + measurement method + pass criteria placeholders X/Y) to avoid cross-version conflicts.
The three common killers (mechanism → first check → highest-leverage fix)
1) Via stub (uncontrolled resonance)
  • Mechanism: stub resonance creates notches/ripple that defeats EQ assumptions.
  • First check: backdrill presence and remaining stub length consistency across lanes.
  • Fix: shorten/remove stubs; align via strategy across the full lane group.
2) Connector transition (impedance step + reflection band)
  • Mechanism: discontinuity introduces frequency-selective reflections (RL bands) and mode conversion.
  • First check: RL(f) banding and TDR reflection location alignment with the connector region.
  • Fix: refine breakout geometry, reference transitions, and pin-field symmetry.
3) Reference plane gap (return-path discontinuity)
  • Mechanism: broken return path raises common-mode, increases crosstalk, and destabilizes margins.
  • First check: layer transitions, plane splits/slots, and stitching via spacing at every crossing.
  • Fix: restore continuous reference or add stitching/bridges to close the return loop.
Decision gate: when the budget points to Retimer/Redriver (link-only)
Use a form-only gate to avoid cross-page overlap. Retimer internals and selection remain on the sibling page.
  • If IL(f) > X in the critical band or notch/ripple dominates (via/connector resonance), and EQ is already near its safe boundary → consider retiming.
  • If RL(f) < Y shows strong reflection bands that move margins with minor assembly variance → treat as structural (layout/connector/retimer decision).
  • If margin < Z after best-known presets and stable power/clocking → escalate to Retimer/Redriver page for placement and verification strategy.
Rule: this page stops at the gate (X/Y/Z placeholders). Retimer details belong to the Retimer/Redriver sibling page.
Loss Budget Ladder Five-step ladder: die, package, board trace, connector, backplane; each segment shows key risk labels and measurement points. Die PLL / CDR Package Escape / Via Board Trace IL / XTALK Connector RL / Step Backplane Long Loss Measurement hooks (field → method) TDR VNA (IL/RL) XTALK scan Margining
Treat channel behavior as a segment-by-segment budget. Notches, reflection bands, and return-path breaks often dominate before EQ becomes the limiting knob.

Jitter Tolerance: What You Must Budget and What You Can Measure

Jitter budget fields (group by source; thresholds as X/Y placeholders)
Jitter should be managed as a budget + measurement mapping, not as abstract terms. Use source grouping to avoid mis-attribution (a common reason “eye looks OK but the link is unstable”).
  • Refclk: phase-noise/spurs, SSC state, and clock-tree coupling; verify lock stability and spectrum cleanliness.
  • TX: PLL/driver noise floor and sensitivity increase under strong pre-emphasis; confirm no new burst-error windows under traffic.
  • Channel: ISI-induced deterministic components (DJ) and periodic pickup (SJ) from coupling/EMI; correlate to IL/RL/XTALK fields.
  • RX: CTLE/DFE noise amplification and CDR tracking boundary (low-frequency wander/ppm); validate with margining and counters.
Typical “looks fine but fails” root causes: low-frequency wander, refclk spurs, or CDR tracking limits—often invisible in a single static eye snapshot.
Measurement mapping (scope vs BERT vs on-chip margining)
Scope (time-domain)
Best for spotting periodic jitter (SJ), coupling events, supply-induced spurs, and “only fails when something switches” clues.
BERT (statistics / BER)
Best for Tj@BER-style acceptance and long-run stability. Use as the arbiter when short captures look misleading.
On-chip margining (system-reproducible)
Best for repeatable production language. Track margin trends across temperature, traffic, and clocking modes (SSC on/off).
Pass/Fail template (metric definition + conditions + thresholds as X/Y)
  • Metric definition: specify window length, denominator, and whether SSC is enabled (avoid “counter looks clean” ambiguity).
  • Test conditions: temperature range, traffic pattern/load, and clocking mode (Common/SRNS/SRIS as applicable).
  • Pass criteria: BER < X over Y time and/or margin > Z across required corners.
  • Regression guard: repeat N runs under the same condition; reject if margins drift beyond ΔX.
Design goal: make jitter acceptance measurable and comparable across revisions (no hard-coded numbers; only stable metric definitions).
Jitter Budget and Transfer Left: jitter source groups; middle: PLL/CDR transfer; right: eye closure and BER output. Sources Refclk TX Channel RX PLL / CDR Transfer RJ DJ SJ Outcome Eye closure BER Measure + decide with consistent definitions (SSC state + window + denominator + X/Y thresholds)
Budget jitter by source, then interpret it through PLL/CDR transfer and tracking limits. Combine scope clues, BER statistics, and margining for a comparable acceptance language.

SRIS vs SRNS vs Common Clock: Board/Backplane Clocking Choices

When to use each mode (decision guide; thresholds as X/Y placeholders)
This section focuses on choice → consequence → observables. Specification clauses and compliance procedures remain on sibling pages.
Common Clock (shared refclk)
  • Best fit: same board/enclosure with a controllable clock tree; simplify relative frequency tracking.
  • Primary risk: clock-tree noise injection, skew distribution, and common-mode coupling paths.
  • Must-watch: refclk cleanliness (spurs/noise) and distribution skew consistency.
  • Acceptance hint: treat “clock tree state” as a test condition variable; results are not comparable without it.
SRNS (separate refclk, no SSC)
  • Best fit: endpoints must use separate refclk sources while keeping measurement templates simpler (no SSC).
  • Primary risk: ppm / low-frequency wander budget becomes more sensitive to corners and recovery behavior.
  • Must-watch: ppm tracking indicators and any drift of buffer-level metrics over time.
  • Acceptance hint: lock test conditions (temperature, refclk sources) to avoid corner-dependent “pass/fail flips.”
SRIS (separate refclk, independent SSC)
  • Best fit: separate refclk is required and SSC cannot be shared; endpoints must tolerate independent modulation.
  • Primary risk: treating SRIS as “anything goes clocking” often causes buffer pressure, drift, and incomparable measurements.
  • Must-watch: elastic buffer level (mean/peak) and buffer event counters (under/over events).
  • Acceptance hint: explicitly capture SSC state + measurement template; otherwise BER/margin data is not comparable.
Stable decision language: define windowed metrics, SSC state, and pass thresholds (X/Y/Z) before comparing modes or revisions.
Bring-up must-watch indicators (minimal set; mode emphasis differs)
Startup (before and during link training)
  • PLL/CDR lock status: lock stability across time and environmental corners.
  • Training progress: whether training repeats or stalls; treat as a boundary locator.
Steady state (link up)
  • Buffer level (mean/peak): primary health indicator for SRIS/SRNS; also useful for any drift detection.
  • Windowed error rate: use a defined time window and denominator to avoid “looks clean” ambiguity.
  • Margin trend: track across temperature and traffic; flat margin is the goal.
Exceptions (flaps, drops, and business failures)
  • Burst signature: burst length distribution often indicates clocking/noise events rather than uniform random noise.
  • Recovery cycles: count retrain/recovery events; repeated recovery indicates a structural boundary.
  • Corner correlation: temperature/traffic/SSC changes that shift stability should be treated as root-cause hints.
Common misconceptions (and the corrective action)
  • SRIS means “clock can drift freely.” Corrective action: treat buffer level and buffer event counters as primary acceptance metrics; record SSC state.
  • Common clock is always the easiest. Corrective action: validate clock-tree noise and common-mode coupling; record distribution topology.
  • SRNS has no SSC, so measurement is always simpler. Corrective action: enforce temperature/ppm corners; monitor drift rather than single snapshots.
  • Average error rate is enough. Corrective action: use windowed metrics and burst signatures to detect event-driven failures.
  • Static eye snapshots prove stability. Corrective action: confirm low-frequency tracking boundaries via buffer/counter correlation.
Clocking Topologies Three stacked diagrams show common clock, SRNS, and SRIS with refclk sources, SSC indicators, and endpoint PLL/CDR blocks. Common Clock Refclk Source SSC Endpoint A PLL/CDR Endpoint B PLL/CDR SRNS Refclk A Refclk B Endpoint A PLL/CDR Endpoint B PLL/CDR SRIS Refclk A Refclk B Endpoint A PLL/CDR Endpoint B PLL/CDR SSC SSC
Choose clocking by engineering consequences: common clock shifts risk into clock-tree noise paths; SRNS/SRIS shift risk into ppm tracking and elastic-buffer pressure, with SRIS requiring SSC-aware measurement templates.

Equalization & Training: Presets, Adaptation, and “When Auto Isn’t Enough”

Training as a controllable loop (input → output → verification)
Training can be treated as a loop: it senses channel conditions, chooses a preset/coefficients, applies settings, and must be verified with repeatable observables. Training success indicates “link can start,” not “margin is sufficient.”
  • Sense: capture a coarse view of channel stress (loss / ISI / noise exposure) using training probes.
  • Decide: choose TX preset/coefficients and RX adaptation boundaries within device capability.
  • Apply: enforce settings (and optional clamps) to prevent unstable adaptation.
  • Verify: confirm stability using windowed counters and margining trends (X/Y acceptance placeholders).
Failure archetypes (signature → boundary → first check → stabilization move)
Fail early (training does not converge)
  • Signature: training repeats/stalls; link does not stabilize.
  • Boundary: structural channel stress (loss/discontinuity) or clock lock validity.
  • First check: lock status + training progress + obvious IL/RL notches.
  • Move: resolve structural issues before pushing aggressive EQ settings.
Fail under load (idle OK, traffic breaks)
  • Signature: burst errors appear when throughput rises; margin collapses under activity.
  • Boundary: crosstalk exposure, power-noise coupling, or DFE noise sensitivity.
  • First check: compare idle vs traffic using windowed error bursts and margin trends.
  • Move: reduce over-compensation and stabilize noise paths before increasing gain/taps.
Fail after warmup (time/temperature drift)
  • Signature: stable for minutes, then flaps or degrades with temperature.
  • Boundary: drift in channel behavior, low-frequency wander, or temperature-driven noise coupling.
  • First check: correlate temperature to margin/buffer/counters (drift is the clue).
  • Move: lock a more conservative preset and include corners in acceptance conditions.
Fix path (a convergence order that avoids “EQ guessing”)
  1. Define measurement language: window + denominator + SSC state + test corners (avoid incomparable data).
  2. Structural first: if IL/RL or return-path breaks dominate, fix channel structure before tuning.
  3. Clocking before EQ: confirm lock/tracking boundaries; unstable refclk/noise invalidates EQ conclusions.
  4. Tune with a single objective: each change must improve a measurable margin/counter metric (X/Y placeholders).
  5. Clamp/lock when needed: restrict adaptation if it causes drift (especially noise-sensitive DFE behavior).
  6. Verify convergence: margin > Y and burst errors disappear for X time across required corners.
Principle: automated training is a starting point. Stability requires measurable margins under traffic and corners, not a single successful training event.
EQ Control Loop Loop shows Channel → Measure → Choose preset/coef → Validate → Lock, with a manual override branch feeding back into validation. Channel loss Measure status Choose preset/coef Validate margin Lock freeze Manual override clamp Observables Counters Margin Burst Auto training is a starting point; stability requires measurable margin under traffic and corners (X/Y).
Treat EQ as a control loop: measure, decide, validate, and lock. Use a manual override path only when it improves windowed counters and margin trends across required corners.

Lane Bonding, Skew, Polarity, and Deskew Buffers

Lane-level parameters and limits (budgets as X/Y placeholders)
Multi-lane failures often look like SI issues, but the boundary can be lane-to-lane skew, lane mapping, or deskew-buffer pressure. Treat these as measurable fields instead of “mystery instability.”
  • Lane-to-lane skew: track lane_to_lane_skew_ps against a budget X.
  • Deskew buffer headroom: monitor deskew_level_mean/peak and deskew_event_count.
  • Lane order / reversal: record lane_order_map and lane_reversal to avoid “accidentally works” wiring.
  • Polarity inversion: confirm polarity_inversion per lane; isolate “one bad lane” quickly.
  • Per-lane margin: keep per_lane_margin to identify a single-lane bottleneck inside a bonded link.
Practical rule: if x1 is stable but x4/x8 is unstable, prioritize skew/deskew and lane mapping before blaming insertion loss.
Symptom → checks (fast boundary isolation)
Single-lane OK, multi-lane fails (x1 stable, x4/x8 unstable)
  • Likely boundary: lane-to-lane skew exceeding deskew headroom.
  • Quick check: read deskew level/peak and deskew events; compare per-lane margin.
  • Fix direction: reduce lane asymmetry (layer changes/via count/connector path) and re-validate deskew headroom.
  • Pass criteria: deskew level stable with headroom > X and no deskew events across Y minutes.
Intermittent CRC and burst errors (average rate looks “clean”)
  • Likely boundary: deskew pressure spikes, lane-specific margin collapse, or mapping/polarity edge cases.
  • Quick check: compare windowed bursts vs deskew events; isolate to a single lane using per-lane margin.
  • Fix direction: remove the “weak lane” asymmetry and clamp unstable adaptation if it amplifies noise.
  • Pass criteria: burst signature disappears and per-lane margin stays within X of each other under traffic.
Link width downshift (negotiates x4 then drops to x2/x1)
  • Likely boundary: one lane fails margin/training; mapping/polarity mistakes can mimic SI problems.
  • Quick check: identify the failing lane via per-lane status/margin; verify lane order and polarity flags.
  • Fix direction: correct mapping/polarity first, then repair the “single lane” physical discontinuity.
  • Pass criteria: negotiated width remains stable with downshift count = 0 across corners.
Layout guidance (lane-bonding focused; strong constraints)
  • Keep lane strategy consistent: same layer policy, same via count, same layer-change points within a lane group.
  • Preserve return-path consistency: avoid lane-specific reference-plane transitions that create differential skew and common-mode stress.
  • Avoid “late serpentine fixes”: last-minute meanders can add loss/crosstalk; plan matching early.
  • Connector breakout symmetry: treat one “special lane” as a risk multiplier; enforce symmetrical breakout rules.
  • Validate per-lane margins: a bonded link is only as strong as its weakest lane; keep per-lane margin spread < X.
4-lane Skew and Deskew Buffers Four differential lanes feed deskew FIFOs and then lane bonding into PCS. One lane has extra delay and triggers a skew warning. Lanes Delay Deskew FIFO Deskew FIFO Deskew FIFO Deskew FIFO Lane Bonding merge PCS status Skew If deskew headroom collapses, the link may downshift or show burst errors even when single-lane looks fine.
Deskew buffers hide lane skew until headroom collapses. Use deskew level/events and per-lane margin to identify the “weak lane” before blaming overall loss.

Board/Backplane Implementation: Routing, Return Path, Power Integrity

Top 10 layout rules (strong constraints; each rule is checkable)
  1. Preserve continuous return path: add stitching vias at every reference transition; avoid plane gaps under the pair.
  2. Impedance control first: lock stackup geometry before “length tuning”; matching cannot fix wrong impedance.
  3. Keep lane-group symmetry: same via count and layer-change strategy across lanes to avoid hidden skew.
  4. Manage via stubs: record stub length as a budget field; backdrill when the notch becomes dominant.
  5. Connector transitions must be symmetric: breakout patterns should not create a “special lane.”
  6. Avoid plane splits and slots: if unavoidable, bridge the return path with stitching structures.
  7. Control common-mode paths: minimize mode conversion by keeping pair geometry and reference consistent.
  8. Power integrity near PLL/CDR is critical: reduce loop area and keep decoupling current return compact.
  9. Separate noisy di/dt sources: distance + return-path isolation prevents PI-to-jitter coupling.
  10. Design for verification: include test entry points to make TDR/VNA/near-field and margining actionable.
Causality chain to keep in mind: return-path breaks and PI noise can become common-mode stress, then appear as jitter, margin loss, and burst errors.
Backplane-specific risks (connector density and board seams)
  • Connector pin-field transitions: more likely to create RL bands and mode conversion; verify with VNA (IL/RL) and TDR for location.
  • Return path across seams: gaps at board edges increase common-mode paths; reinforce with stitching strategies and validate with near-field scans.
  • Segment inconsistency: one segment with different via/stackup policy becomes the weakest link; track per-segment risk fields.
  • Tolerance sensitivity: assembly and connector variance can shift margin; confirm margin stability across temperature and load corners.
Verification methods (tool → question answered → common pitfall)
  • TDR: “Where is the reflection?” Pitfall: treating a location result as a full margin verdict.
  • VNA (IL/RL): “Is the loss/return budget feasible across frequency?” Pitfall: ignoring notch regions that dominate training stability.
  • Near-field scanning: “Where is the coupling/hot spot?” Pitfall: measuring without a consistent traffic pattern and grounding setup.
  • On-chip margining + counters: “Is margin stable under traffic and corners?” Pitfall: comparing results without the same window/denominator/SSC conditions.
Return Path Continuity Map Differential pair transitions layers above a ground plane; stitching vias bridge return path. A plane gap is highlighted as a break that can create common-mode noise and jitter. Return Path GND plane Gap Diff pair Via Stitching Return continuity Return break CM → Jitter
Return-path breaks create common-mode stress that can show up as jitter and burst errors. Stitching strategies and consistent reference transitions keep the return path continuous across layer changes and seams.

Bring-up & Debug Playbook (Lab → Root Cause)

Card A · Debug flow (layered evidence chain)
Use a layered path to avoid random knob-turning: protocol state → training/EQ status → windowed counters → physical measurements. Each step produces a boundary decision and a “next action.”
  1. Classify the symptom entry: fails to train / trains then flaps / idle OK, fails under traffic / temperature-dependent.
  2. Layer 1 — Protocol boundary: capture LTSSM / link state and the “stuck point” or “retrain loop” signature.
  3. Layer 2 — Training/EQ boundary: read equalization status and whether adaptation converges or oscillates.
  4. Layer 3 — Error evidence: use windowed counters (X-second windows) and burst signatures to separate “event bursts” from “uniform errors.”
  5. Layer 4 — Physical measurement: choose scope/BERT/VNA/TDR based on the boundary: eye/jitter for stability, IL/RL for feasibility, TDR for location.
  6. Close the loop: map the result to one root-cause family: structure / clock/SSC / EQ/training / lanes/thermal/PI, then re-test under the same window/SSC conditions.
Measurement discipline: compare results only when window length, traffic pattern, and SSC conditions are identical (X/Y placeholders).
Card B · Tools & observables (tool → question → common pitfall)
  • On-chip margining + status: answers “Is margin stable under traffic and corners?” Pitfall: mixing windows/denominators/SSC states makes data incomparable.
  • Counters (windowed + burst): answers “Uniform noise vs event-driven bursts?” Pitfall: averaging hides burst triggers (door open, fan spin-up, load step).
  • Scope (eye/jitter): answers “Is jitter shaping or low-frequency wander dominating?” Pitfall: a “nice eye” can still fail when CDR/PLL boundaries are stressed.
  • BERT (bathtub/BER): answers “Is the error floor improving with speed/preset changes?” Pitfall: relying on a single average BER without burst distribution.
  • VNA (IL/RL): answers “Is the channel feasible across frequency?” Pitfall: ignoring RL bands/notches that dominate training stability.
  • TDR: answers “Where is the reflection/discontinuity?” Pitfall: using location alone as a margin verdict.
Card C · Fast isolation moves (3 levers that cut search space)
  • Swap endpoint or segment: isolates “endpoint-specific” vs “channel-structure” issues. Pass: failures follow the endpoint (or stay with the channel) consistently across X trials.
  • Swap refclk source / clamp SSC state (if applicable): isolates clock/SSC template sensitivity. Pass: jitter/burst signatures change with refclk/SSC changes under identical traffic.
  • Downshift speed / lock preset (freeze adaptation): separates “margin not enough” from “training drift.” Pass: stability improves at lower speed or with locked preset without changing the physical channel.
Root-cause efficiency rule: change only one axis at a time (endpoint / clock / speed-preset), and keep the same measurement window (X/Y).
Debug Decision Tree A four-layer decision tree: Train? Flap? Under load? Temperature-dependent? Leaf nodes suggest first checks such as LTSSM, EQ status, counters, refclk noise, IL/RL notch, deskew. Decision Tree Train? No Yes First check LTSSM · Link state Flap? Yes No EQ status · Windowed counters Under load? First check Counters · PI/Refclk Thermal · Deskew IL/RL notch · TDR
A layered decision tree keeps debugging bounded. Start with state and status, then use windowed counters for burst signatures, and only then pick the measurement tool that answers the boundary question.

Failure Patterns & Design Traps (12 Mistakes That Cost Weeks)

These are repeatable failure patterns, not Q&A. Each trap is written in the same evidence-driven style: Symptom → Likely cause → Quick check → Fix.
Trap #1 · Via Stub
STRUCTURE
Symptom: trains at lower speed, fails at higher speed; errors cluster near transitions.
Likely cause: stub-induced notch and reflection dominating the usable band.
Quick check: TDR location + VNA IL/RL for a notch signature (X frequency band placeholder).
Fix: backdrill or reduce stub length; re-validate margin under the same window/SSC conditions.
Trap #2 · Plane Gap / Return Break
STRUCTURE
Symptom: burst errors that correlate with specific system events (door open, motor start, load step).
Likely cause: return-path discontinuity converts to common-mode stress and jitter.
Quick check: near-field hot spot + compare bursts with windowed counters; inspect reference transitions.
Fix: add stitching strategy and keep reference consistent through transitions and seams.
Trap #3 · Connector Discontinuity
STRUCTURE
Symptom: works on bench, fails in chassis/backplane; sensitivity to connector insertion/pressure.
Likely cause: RL bands and mode conversion at dense pin-field transitions.
Quick check: VNA IL/RL and compare segments; TDR to pinpoint the transition.
Fix: enforce symmetric breakout and reference strategy; re-verify margin across temperature/load corners.
Trap #4 · Noisy Refclk Injection
CLOCK
Symptom: eye looks acceptable but stability collapses under certain system noise conditions.
Likely cause: refclk phase noise or coupling into PLL/CDR boundaries.
Quick check: swap refclk source; correlate burst errors with refclk/PI events using the same window (X/Y).
Fix: improve refclk routing/isolation; harden return paths and reduce coupling from di/dt sources.
Trap #5 · SSC Condition Mismatch
CLOCK
Symptom: lab results cannot be reproduced; “same setup” behaves differently across runs.
Likely cause: SSC state/template differs between endpoints or measurement runs.
Quick check: log SSC state and window definitions; compare only when SSC and traffic are identical.
Fix: standardize SSC and measurement window (X/Y) as a project-wide “metric contract.”
Trap #6 · CTLE Over-Boost
EQ
Symptom: training passes, but error bursts appear under noisy conditions or certain workloads.
Likely cause: CTLE amplifies noise along with signal, shrinking effective jitter tolerance.
Quick check: lock a conservative preset and compare windowed bursts (X/Y) under the same traffic.
Fix: reduce CTLE boost; validate margining stability across temperature and load corners.
Trap #7 · DFE Overfit / Drift
EQ
Symptom: works for minutes, then degrades; errors appear after warm-up or workload transitions.
Likely cause: DFE adapts into noise and becomes unstable at boundaries.
Quick check: freeze adaptation and compare stability; watch EQ status for oscillation signatures.
Fix: constrain adaptation or use a stable preset; remove noise sources that trigger overfitting.
Trap #8 · Deskew Headroom Collapse
LANES
Symptom: x1 stable, x4/x8 unstable; link width downshifts or shows burst errors.
Likely cause: lane-to-lane skew exceeds deskew buffer headroom in traffic or corners.
Quick check: deskew level/peak and deskew events under the same window (X/Y).
Fix: enforce lane symmetry (layer/via/connector path) and re-test per-lane margin spread < X.
Trap #9 · Thermal Margin Collapse
THERMAL
Symptom: stable at cold start; fails after warm-up or sustained traffic.
Likely cause: temperature shifts reduce margin; adaptation hits boundaries under heat.
Quick check: correlate errors with temperature/time; run margining snapshots at fixed thermal points.
Fix: improve thermal path; validate stability at temperature corners (X/Y) rather than only at ambient.
Trap #10 · PI Noise → Jitter Coupling
PI
Symptom: errors appear during load steps; stability depends on system activity.
Likely cause: supply ripple injects into PLL/CDR and becomes effective jitter.
Quick check: correlate windowed bursts with power events; compare stability when reducing di/dt sources.
Fix: tighten decoupling loop and return path near SerDes; isolate noisy loads and re-check margining.
Trap #11 · Lane Mapping / Polarity Mix-up
LANES
Symptom: “sometimes trains” or trains only in certain widths; one lane behaves as the bottleneck.
Likely cause: lane order map or polarity inversion mismatch across endpoints.
Quick check: verify lane map and polarity flags; compare per-lane status to isolate the failing lane quickly.
Fix: correct mapping/polarity first, then re-run training to avoid chasing false SI symptoms.
Trap #12 · Crosstalk Hot Spot
STRUCTURE
Symptom: errors spike only when neighboring lanes/buses are active; idle looks fine.
Likely cause: NEXT/FEXT hot spot near a bend, via field, or connector breakout.
Quick check: toggle aggressor activity and watch windowed bursts; use near-field to locate the hot region.
Fix: increase spacing or change reference strategy locally; retune routing symmetry and re-verify margins.
Trap Gallery 3×4 icon matrix representing common PHY/SerDes traps with one-word labels. Trap Gallery Stub Plane gap Refclk Connector SSC CTLE DFE Deskew Thermal PI noise Crosstalk Mapping
A visual index of 12 repeatable traps. Keep the labels minimal; use the 12 trap cards for evidence chain and fixes.

H2-11 · Engineering Checklist (Design → Bring-up → Production)

A gate-based checklist to make PCIe PHY/SerDes work repeatable, measurable, and shippable. Each line item requires evidence and a pass criterion (use X/Y placeholders to fit the exact generation / spec target).
Design Gate “Build it so it can run, be measured, and be tuned.”
  • Channel budget template complete (IL(f), RL, NEXT/FEXT, via stub, connector discontinuity, skew, return-path breaks).
    Evidence: budget sheet + assumptions captured.
    Pass: all required fields present; unknowns flagged with owner/date.
  • Channel segmentation documented (die/pkg/trace/connector/backplane), including “worst segment”.
    Evidence: annotated path diagram + stackup notes.
    Pass: worst segment identified; mitigation knob mapped (routing/backdrill/EQ).
  • Lane-level constraints locked (skew budget = X ps; polarity / reversal plan; deskew headroom strategy).
    Evidence: layout constraint set + review sign-off.
    Pass: constraints are tool-enforced; waiver process defined.
  • Via strategy fixed (stub length ≤ X; backdrill or alternative) and validated by SI review.
    Evidence: via table + backdrill notes + TDR plan.
    Pass: stubs stay within budget across all layers/variants.
  • Return-path continuity rules enforced (reference-plane transitions, stitching vias, anti-split routing).
    Evidence: “return-path map” markup + DRC screenshot.
    Pass: no uncontrolled plane gaps under the diff-pair route.
  • Clocking choice recorded (Common / SRNS / SRIS) with engineering consequences (ppm tracking, buffer behavior, test method).
    Evidence: decision note + bring-up observables list.
    Pass: “what changes in validation” is explicitly stated.
  • Refclk distribution parts locked (example chain: clock gen → fanout buffer → endpoints) with configuration method (pin/I²C/EEPROM).
    Evidence: schematic snippet + BOM line items + config file.
    Pass: outputs meet format/load; startup state deterministic.
  • Clock/PLL rail noise plan set (local low-noise regulation, decoupling, isolation from switching nodes).
    Evidence: placement note + PDN target + rail measurement plan.
    Pass: rail ripple/noise within X across load/temperature.
  • Observability hooks guaranteed (LTSSM, EQ status, per-lane error counters, deskew level, margining interface).
    Evidence: register-map checklist + firmware readout demo.
    Pass: all signals readable at runtime; logging window defined.
  • Test access reserved (probe/launch points, controlled test coupons, “known-good” swap path).
    Evidence: board review checklist + coupon drawing.
    Pass: at least one low-risk test insertion point per link.
Bring-up Gate “Make it stable under traffic, stress, and corners.”
  • LTSSM evidence collected across target rates and widths (success + failure captures).
    Evidence: LTSSM logs + timestamped traces.
    Pass: no unexpected retrain loops beyond X per Y minutes.
  • EQ/training status captured per lane (preset/coef/adaptation result) with a repeatability window.
    Evidence: EQ status dump + lane histogram.
    Pass: training converges within X attempts; coefficients stable.
  • Deskew buffer headroom verified (no saturation at nominal + worst-case skew).
    Evidence: deskew level readout under traffic.
    Pass: buffer level stays within [L..H] with margin ≥ X.
  • Idle stability and traffic stability verified as separate tests (avoid “idle-only success”).
    Evidence: two run logs (idle / load) + counters.
    Pass: error bursts ≤ X per Y window in both modes.
  • Margining snapshot taken (on-chip margining or external) at nominal + “worst segment”.
    Evidence: margin plot + raw settings.
    Pass: margin ≥ X at BER target Y (placeholders).
  • A/B isolation: swap endpoint, swap refclk source, lock presets, reduce rate (one variable at a time).
    Evidence: test matrix + results table.
    Pass: root-cause class narrowed to one layer (clock/SI/EQ/thermal).
  • Thermal sweep performed (cold → hot) with continuous counters and “event tagging”.
    Evidence: temp vs error plot + fan profile log.
    Pass: no margin collapse beyond X across operating range.
  • Supply disturbance check near clock/PLL rails (load step / noise injection) correlated to errors.
    Evidence: rail waveform + correlated counter bursts.
    Pass: jitter/error response stays within X under defined disturbance.
  • Golden configuration created (auto vs manual overrides), stored, and reproduced after power cycles.
    Evidence: config dump + power-cycle replay log.
    Pass: stable link achieved within X seconds for Y cold boots.
Production Gate “Make it scalable: traceable, testable, and diagnosable.”
  • Golden config is versioned and locked (hash/ID; change-control process defined).
    Evidence: version tag + stored dump + release note.
    Pass: every unit can report config ID at runtime.
  • Unit identity for traceability (example: I²C EEPROM with EUI-64) integrated and logged.
    Evidence: manufacturing log contains unique ID + timestamp.
    Pass: ID readable in-field; no duplicates (X = 0).
  • Thermal telemetry strategy defined (board sensor, sampling interval, alarm thresholds).
    Evidence: temp log + threshold table.
    Pass: alarms trigger at defined X; false positives ≤ Y.
  • Production screening includes a short “traffic + counter window” test (not link-up only).
    Evidence: tester script + golden log for “good”.
    Pass: error bursts ≤ X per Y window.
  • Sampling plan defined (AQL/lot sampling) and failure routing (retest, quarantine, RCA).
    Evidence: QA doc + escalation tree.
    Pass: time-to-quarantine ≤ X; repeatability proven.
  • Incoming inspection defines critical parts (clock tree ICs, connectors) and acceptable alternates.
    Evidence: AVL list + marking/photo examples.
    Pass: alternates are validated against X/Y criteria.
  • Field debug package defined (counters snapshot, EQ status, temperature, config ID) with one-button export.
    Evidence: exported report + parsing tool.
    Pass: “first report” generated in ≤ X minutes on-site.
  • “Golden swap” method preserved (known-good board/cable/refclk module) to isolate issues fast.
    Evidence: spare kit list + validation procedure.
    Pass: isolation to layer achieved within X steps.
Reference parts (examples for clocking / observability)
Use as recognizable anchors for schematics and checklists (not a mandate; validate against generation and board constraints).
  • Clock generator (multi-output, EEPROM): TI LMK03328
  • PCIe fanout / HCSL-style distribution: Renesas 9DBV0841
  • Programmable low-phase-noise (non-SSC) clock generator: Renesas 9FGV1001C
  • Jitter attenuator / clock generator: Skyworks/Silicon Labs Si5341
  • Jitter attenuator (DPLL-based timing): Microchip ZL30721
  • Low-noise LDO (clock/PLL rails): TI TPS7A47 / TPS7A47-Q1
  • Traceability EEPROM with unique ID (EUI-64): Microchip 24AA02E64
  • Board temperature telemetry (for correlation): TI TMP117
Diagram: 3-gate funnel — the project narrows from “design-ready” to “ship-ready”.
3-Gate Funnel Three gates (Design, Bring-up, Production) narrow toward Ship Criteria; each gate has three short tags. Design Gate Bring-up Gate Production Gate Budget Layout Clocking Observability Margin Corners Golden Sampling Fail Contract Ship Criteria

H2-12 · Applications & System Placement (Boards / Backplanes / Accelerators)

System placement patterns for PCIe PHY/SerDes. Each scenario card lists the goal, the dominant constraints, the must-watch observables, and an example refclk chain (with recognizable part numbers).
Server motherboard + backplane
  • Goal: stable high-throughput across connector + backplane discontinuities.
  • Key risks: connector IL/RL, plane transitions, multi-slot crosstalk hotspots, thermal drift.
  • Must-watch observables: EQ convergence, burst-error counters, deskew level, margin snapshots.
  • Example refclk chain: Si5341 (cleanup) → LMK03328 (gen) → 9DBV0841 (fanout).
Sibling links (no expansion): Retimer/Redriver · Compliance & Test Hooks · Controller / Endpoint
Storage (NVMe / HBA / riser)
  • Goal: “under-traffic” robustness (avoid idle-only success).
  • Key risks: load-triggered bursts, temperature rise near dense drives, reference noise coupling.
  • Must-watch observables: traffic-correlated bursts, LTSSM retrain count, margin vs temperature.
  • Example refclk chain: ZL30721 (jitter attenuate) → LMK03328 → 9DBV0841.
Sibling links (no expansion): Jitter · EQ & Training · Compliance
Accelerator card (GPU/NPU/FPGA-class add-in)
  • Goal: keep margin under heat density and aggressive power transients.
  • Key risks: PLL/CDR sensitivity to rail noise, thermal gradients, lane-to-lane skew under routing pressure.
  • Must-watch observables: margin drift over warm-up, deskew headroom, error bursts during load steps.
  • Example support parts: clock/PLL rails with low-noise regulation (e.g., TPS7A47) + refclk chain (LMK03328 → 9DBV0841).
Sibling links (no expansion): Lane Skew/Deskew · Routing/Return/PI · Retimer/Redriver
FPGA card / prototyping platform
  • Goal: fast iteration without losing repeatability.
  • Key risks: inconsistent presets, measurement drift, “works today” configs that cannot be replayed.
  • Must-watch observables: preset/coef history, LTSSM retrain signature, margin snapshots per build.
  • Example traceability parts: unique ID EEPROM (e.g., 24AA02E64) + deterministic clock startup (LMK03328 EEPROM mode).
Sibling links (no expansion): Bring-up Playbook · Failure Patterns · Test Hooks
Dense multi-slot chassis (many links in parallel)
  • Goal: avoid system-wide “correlated failures” (multiple links flap together).
  • Key risks: shared refclk contamination, shared PDN events, EMI coupling, airflow non-uniformity.
  • Must-watch observables: time-correlation across links, burst timing vs rail/clock events, temperature gradients.
  • Example architecture anchor: centralized cleanup (Si5341/ZL30721) + fanout buffering (9DBV0841).
Sibling links (no expansion): Channel/Loss Budget · Jitter Tolerance · Retimer/Redriver
Diagram: system placement map — motherboard ↔ connector/backplane ↔ add-in card (highlight discontinuities and observability points).
System Placement Map Motherboard on the left, connector/backplane in the middle, add-in card on the right. A differential path crosses discontinuities; refclk distribution and thermal icons are shown. Motherboard Root / RC SerDes Refclk Tree Si5341 / LMK03328 Connector + Backplane Discontinuity IL / RL / XTALK Add-in Card EP SerDes Deskew / EQ LTSSM / Counters Margin Snapshots Thermal 9DBV0841 Fanout

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H2-13 · FAQs (10–12) — fixed 4-line answers + JSON-LD

Scope: only on-site troubleshooting for PCIe PHY/SerDes (clocking SRIS/SRNS/common clock, channel/loss, jitter, EQ/training, lane/deskew, thermal/PI correlation). Each answer is a measurable loop with placeholders (X/Y) to match the exact generation / target.
SRIS configured but the link still flaps periodically — first check ppm tracking or buffer level?
Likely cause: ppm drift is being absorbed until an elastic/deskew buffer hits a boundary and triggers retrain/reset behavior.
Quick check: log buffer level/headroom + ppm tracking status + retrain counters in a fixed window (Y minutes) and correlate flap timestamps.
Fix: validate SRIS mode end-to-end; tighten refclk ppm/jitter at the source; confirm buffer policy (no silent saturation); re-test with a known-good clock source as A/B.
Pass criteria: retrain events ≤ X per Y minutes; buffer level stays within [L..H] with headroom ≥ X (units/format per silicon); error bursts ≤ X per window.
Eye looks OK, but BER spikes at high temperature — check refclk phase noise first or RX DFE overfitting?
Likely cause: margin collapses with temperature due to refclk noise/PLL sensitivity or adaptive EQ (DFE) pushing into a noisy operating point.
Quick check: run a controlled thermal sweep while capturing margin snapshots, EQ coefficients/adaptation state, and error bursts; compare “DFE on vs limited” modes if available.
Fix: stabilize clock/PLL rails and refclk source (reduce injected noise); constrain adaptation (lock a known-good preset/coef) and re-validate; ensure airflow/thermal path meets the link budget assumptions.
Pass criteria: BER ≤ Y (target) across [Tmin..Tmax]; margin ≥ X at temperature corners; coefficient spread stays within X band; burst rate ≤ X per window.
Same channel: Gen4 stable, Gen5 unstable — insertion loss first or jitter budget first?
Likely cause: the Gen5 margin is limited by a combined loss+jitter boundary where training “barely passes” but long-run stability fails.
Quick check: take a margin snapshot at Gen5 and compare against Gen4; capture EQ convergence quality and error burst signature under traffic (not idle-only).
Fix: if loss-driven: shorten/clean the worst segment (via stub/backdrill/connector breakout/return-path); if jitter-driven: improve refclk/rails/PI coupling and retest; keep variables isolated (one change per run).
Pass criteria: Gen5 margin ≥ X at target BER=Y; retrain ≤ X per Y minutes; under-traffic burst errors ≤ X per window; EQ convergence within X attempts.
Training passes but real traffic CRC spikes — underrun/elastic buffer or locked EQ preset first?
Likely cause: a “traffic-only” failure mode: buffer/credit/elastic behavior or adaptation mismatch that does not show up in a short training pass.
Quick check: correlate CRC spikes with buffer/deskew levels and traffic load; compare “auto EQ” vs “locked known-good preset” runs; check for burst periodicity (Y ms / Y s).
Fix: isolate the layer: (1) lock a stable preset/coef; (2) verify buffer headroom and no saturation under load; (3) re-enable adaptation gradually and validate repeatability; keep a golden config for replay.
Pass criteria: CRC errors ≤ X per Y window at full load; buffer headroom ≥ X; no periodic burst pattern above X amplitude; link stays at target width/rate for Y minutes.
Only fails on one backplane — connector discontinuity or return-path gap first?
Likely cause: a board-specific discontinuity (connector/breakout) or a reference-plane discontinuity causing mode conversion and reduced margin.
Quick check: compare margin/EQ coefficients between “good” and “bad” backplanes; run TDR/VNA on the failing path segment if available; look for correlated failures across multiple links on that backplane.
Fix: prioritize mechanical/electrical discontinuities: connector footprint/breakout symmetry, plane stitching at transitions, controlled impedance through the seam; re-validate after a single physical change to confirm causality.
Pass criteria: failing backplane reaches margin ≥ X at target BER=Y; EQ coefficients stay within X of the golden backplane; burst errors ≤ X per window; no rate/width downshift in Y minutes.
x1 works but x4/x8 fails — skew/deskew headroom first or SI loss first?
Likely cause: lane-to-lane skew or deskew buffer saturation (a “multi-lane mechanism” failure, not pure single-lane SI).
Quick check: read deskew level/headroom per lane during traffic; check for width negotiation/downshift and per-lane error asymmetry; verify lane reversal/polarity settings match the board.
Fix: reduce skew by layout correction (symmetry, consistent reference plane, matched via patterns); ensure deskew policy and lane mapping are correct; then re-tune EQ with a stable deskew condition.
Pass criteria: deskew headroom ≥ X (per silicon format) in all lanes; negotiated width stays at target for Y minutes; per-lane error bursts ≤ X per window.
Link width downshifts under load — deskew FIFO saturation or correlated noise event?
Likely cause: under-load bursts push either deskew/buffer mechanisms to a boundary or expose shared noise (refclk/PDN) that hits many lanes together.
Quick check: timestamp width changes and correlate with buffer/deskew level, rail events, and temperature; check if multiple links change width at the same time (system correlation).
Fix: if boundary-driven: restore headroom (skew control, buffer policy, stable preset); if correlated: clean refclk distribution/rails and isolate aggressors; re-test with one variable removed (fan profile, rail load step, clock source).
Pass criteria: width remains at target across Y minutes of worst-case traffic; correlation rate across links ≤ X events; bursts ≤ X per window; buffer/deskew never touches hard limits.
Trains successfully, then flaps every few minutes — is it re-training triggered by bursts or slow drift?
Likely cause: a slow drift (clock/thermal) or periodic disturbance drives margin below the retrain threshold, producing a repeating signature.
Quick check: capture a repeating window: error burst timing, temperature slope, refclk/rail monitor, and EQ re-convergence markers around each flap.
Fix: lock a known-good EQ configuration to test drift sensitivity; then address the dominating drift source (clock/rail/thermal). Avoid simultaneous changes—verify causality with A/B runs.
Pass criteria: no periodic flap over Y minutes; retrain count ≤ X; drift of margin/coefficients ≤ X over Y minutes; burst rate ≤ X per window.
Counters look clean, but application-level errors still happen — first accounting check?
Likely cause: metric window/denominator mismatch or counters sampled/reset in a way that hides short bursts.
Quick check: standardize a fixed observation window (Y seconds) and collect: raw counters, reset points, traffic volume, and timestamp alignment; verify “burst visibility” with shorter windows.
Fix: implement windowed/burst-aware accounting (peak window + rolling window); keep counter reset logic deterministic; align logs with traffic phases and temperature/rail events.
Pass criteria: measured error rate stable within X per Y window; burst detection coverage ≥ X%; no “silent windows” longer than Y seconds with missing samples.
SSC enabled but jitter/margin measurements look inconsistent — what is the first sanity check?
Likely cause: the measurement method is not SSC-aware (wrong bandwidth/windowing), mixing wander with jitter or misreading tracked components.
Quick check: confirm SSC is actually enabled at the intended node; verify the tool setup (bandwidth, acquisition time, trigger) matches SSC behavior; compare “SSC on vs off” in identical conditions.
Fix: switch to SSC-appropriate measurement settings; treat slow components as tracked/wander; re-baseline pass/fail templates for the chosen clocking mode (SRIS/SRNS/common clock).
Pass criteria: measurement repeatability within ±X across Y runs; margin metric stable within X; no tool-dependent pass/fail flips for the same physical condition.
SRNS chosen (no SSC), but recovery/retrain behavior looks worse than expected — what to check first?
Likely cause: ppm/jitter assumptions are violated or refclk distribution injects noise, causing borderline operation that appears as “worse recovery”.
Quick check: validate refclk ppm/jitter at the endpoints; check for rail events coupling into PLL/CDR; compare recovery signature at reduced rate/locked preset to classify loss vs jitter.
Fix: clean refclk distribution and clock/PLL rails; stabilize EQ (known-good preset) to remove adaptation variance; re-run with a controlled disturbance matrix (one variable at a time).
Pass criteria: recovery time ≤ X; retrain ≤ X per Y minutes; no clustered bursts after recovery; margin ≥ X at target BER=Y.
Bench looks stable, but the chassis system shows “correlated failures” (multiple links fail together) — first check?
Likely cause: a shared dependency (refclk tree, shared PDN event, airflow/thermal zone) creates synchronized margin drops across links.
Quick check: timestamp-align failures across links and correlate with clock-tree monitors, rail telemetry, and fan/thermal events; confirm whether the same burst signature appears on multiple links.
Fix: isolate shared sources (swap clock source/fan profile/rail load step); harden clock distribution and PI isolation; verify each link independently after removing the shared stressor.
Pass criteria: cross-link correlation rate ≤ X per Y hours; no multi-link simultaneous retrain; per-link burst ≤ X per window; stable operation for Y minutes at worst-case load.
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