Protect the port without breaking the channel.

The goal is connector-side ESD robustness (IEC-level events) while preserving differential symmetry and keeping added insertion-loss / mode-conversion within budget for high-resolution camera and display links.

• External camera or panel ports with frequent human handling and ESD exposure.
• Long FPC / coax / connector transitions where eye margin is already tight.
• “Passed ESD once” but the link becomes more fragile over time (leakage drift / layout parasitics).
• TVS vendor swap causes BER/frame errors even though clamp ratings look similar.

• Selection rubric: ultra-low-C budget, symmetry constraints (ΔC/ΔL), leakage budget, and “must-have” datasheet fields.
• Placement rules: connector-side geometry, shortest return path, via-fence guidance, and “no hidden stub” routing rules.
• Verification loop: IEC ESD → SI checks (TDR/S-params) → system eye/BER or frame-error correlation (threshold placeholders).
• Troubleshooting FAQ: symptom → first check → fix → pass criteria (threshold placeholders).

The highlighted region is the scope: selecting an ultra-low-C ESD/TVS array and placing it so the return path is short, symmetric, and low-inductance. Other blocks are intentionally greyed out to prevent content overlap with sibling pages.

Camera/display links often run with tight margin. A protection device that “clamps well” can still degrade the channel through added shunt capacitance, package/PCB inductance, and P/N mismatch that converts differential energy into common-mode noise.

• Cj (per line, to GND): the junction capacitance of one I/O pin to the local reference (typically GND), at the datasheet test condition.
• ΔC (P vs N mismatch): the capacitance mismatch between the two lines of a differential pair, including device + pads + vias + nearby copper effects.
• Ultra-low-C target: <0.2 pF class is treated as a starting class for high-resolution camera/display ports; final acceptance is validated by SI checks (placeholders later in the page).
• Frequency caution: if the datasheet does not clearly specify measurement conditions for capacitance, the part is treated as “untrusted” until S-parameter / TDR validation.

The same part can behave very differently depending on return-path inductance and P/N symmetry. For camera/display ports, “ultra-low-C + symmetry” is treated as a first-class constraint, then validated by SI measurements and system error correlation later in the page.

This chapter defines the dominant port-side threat for camera/display links: IEC-style ESD events and their return-loop behavior. Surge/OVP power-path protection and full EMC enclosure strategy are intentionally out of scope here.

• Contact discharge: more repeatable and strongly coupled to the connector metalwork and signal pins.
• Air discharge: more variable; the discharge path and coupling can shift with humidity, angle, and gap.
• Key takeaway: the event has a very fast edge and high peak current, so return-loop inductance becomes the first-order limiter.

A port strike is not “voltage to ground.” It is a current loop: connector shell or signal pin → TVS/ESD array → local reference plane → return path → back to the source. The longer and thinner the loop, the larger the effective inductance and the higher the local overshoot.

The critical variable is loop inductance. A short, local return (via fence + continuous reference) reduces overshoot and improves repeatability across humidity and handling conditions.

For high-speed ports, a TVS is not “just a clamp.” The channel sees a frequency-dependent shunt capacitance plus dynamic resistance and multiple inductances. The smallest useful model is: Cj (freq-dependent) + Rdyn + Lpkg + via/plane inductance.

These fields lock the measurement format without enforcing protocol-specific values. Replace X/Y with project thresholds:

The protector introduces a local discontinuity (pad capacitance + via inductance + stub length). Ultra-low-C and strict symmetry minimize the discontinuity so the channel remains within margin after protection is added.

High-resolution camera and display links are sensitive to imbalance. Even if a protector clamps correctly, ΔC/ΔL mismatch can convert differential energy into common-mode noise, raising EMI and shrinking eye margin.

• Skew and eye shrink: unequal loading shifts timing and reduces margin.
• Higher mode conversion: differential-to-common conversion increases (Sdc21 proxy rises).
• More common-mode noise: stronger coupling into shields/cables/hands.
• EMI regression: radiated/conducted behavior worsens even when insertion loss looks acceptable.
• Higher error rate: BER / frame error sensitivity increases with cable swaps and posture changes.

Keep symmetry at the protector: mirrored vias, matched stub lengths, and continuous reference. Imbalance creates mode conversion and higher sensitivity to handling and cable changes.

• Default: place the TVS array on the connector side to intercept the strike at the entry.
• Allowed exceptions: mechanical shielding or module constraints, as long as return loop and stubs remain controlled.
• Non-goal: placing near the SoC as a habit; it often increases the exposed channel length.

• Short: minimize the distance from TVS to the reference plane connection.
• Wide: avoid narrow neck-downs in the return connection.
• Straight: prevent return detours that add loop inductance.
• Near continuous plane: avoid plane splits, windows, and large keepouts under the protector region.

• Via fence around TVS: stitch the reference so the clamp loop is local (density threshold placeholder X).
• No hidden stubs: keep TVS branches short and avoid extra pads; enforce stub < X (placeholder).
• Stay away from plane discontinuities: avoid screw holes, slots, and shield windows under/near the TVS.
• Keep the main diff channel straight: the TVS should connect as a short shunt, not force detours in the main path.
• Connector-to-TVS first: do not route a long exposed segment before protection.

The template emphasizes connector-side interception, a short shunt to a continuous reference plane, and a via fence to keep the clamp loop local while preserving a straight main differential channel.

This chapter covers only ESD/TVS protection topologies and their SI/return-path risks. It does not expand into protocol electrical details or power-path OVP design.

• Mechanism: shunts strike current into the local reference plane through a short clamp loop.
• Strength: simplest to keep symmetry and a short return.
• Risk: if the plane is discontinuous or the via path is long, loop inductance dominates and overshoot remains high.

• Mechanism: diverts the strike toward rails instead of only to the local reference.
• Risk 1: the return loop can become longer and less predictable than a local shunt.
• Risk 2: rail injection can spread the transient into other domains if the rail impedance is not local.
• Risk 3: symmetry is harder because routing to rails is often less mirror-friendly.

• Different C budgets: high-speed lanes demand ultra-low-C, while low-speed/sideband lines often tolerate higher capacitance.
• Different protection strategy: low-speed lines may prefer stronger clamp behavior and higher robustness.
• Separation trigger: when a port mixes high-speed lanes with low-speed control lines, split protection: HS lanes use ultra-low-C; LS lines use stronger clamp.

Use the pattern that preserves C budget, symmetry, and a local return loop. When mixing high-speed lanes with low-speed lines, split protection strategies instead of forcing one topology across all pins.

• Lane class: HS differential lanes vs LS/sideband lines.
• Operating voltage window: sets VRWM headroom expectations.
• ESD target: required robustness level (test method and level are project inputs).
• Channel margin: insertion/return/eye budget available for added shunt loading.
• Leakage budget: allowable leakage drift across temperature corners.
• Footprint reality: connector-side space, via fence feasibility, and routing symmetry feasibility.

• Cj condition mismatch: a low-frequency Cj number may not reflect high-frequency behavior.
• Missing matching spec: no ΔC spec means higher variance and higher swap risk.
• Wrong pin pairing: selecting non-symmetric pins inside an array breaks symmetry even with a “low-C” part.
• Clamp-first selection: chasing lower VC without controlling C budget often causes SI failure after protection is added.

The flow enforces a repeatable order: set capacitance budget and symmetry first, then satisfy voltage/leakage/clamp, and finally verify SI with measurement correlation.

This workflow validates the port protection solution (TVS/ESD array + placement geometry). It does not replace protocol compliance test programs.

Passing IEC ESD is not equivalent to being SI-clean. The acceptance must close both loops: protection works and channel is not degraded.

• Before/After: compare SI with and without TVS (or rev A vs rev B). Absolute plots alone are insufficient.
• Mode conversion focus: symmetry loss increases common-mode noise and external coupling sensitivity.
• Map failures to metrics: “ESD passes but errors rise” often correlates with skew or mode-conversion proxy increase.

Every change (part swap, placement shift, via fence update) must re-run both IEC and SI checks using the same before/after correlation rules.

Field failures often come from drift and contamination effects, not from a single “ESD pass/fail” moment. Production controls must prevent “passed once but fragile later”.

• Temperature: leakage can rise quickly at high temperature and shift bias margins.
• Humidity: moisture reduces surface resistance and increases susceptibility to micro-leakage paths.
• Contamination: flux residue and ionic contamination create unintended conduction paths near the connector.

• Cleaning discipline: control flux residue and moisture adsorption near the connector zone.
• ESD handling: prevent secondary strikes during assembly and rework operations.
• Rework heat: limit thermal shock cycles; repeated heating can shift parameters or geometry.
• Connector-area hygiene: reduce touch contamination and dust ingress during manufacturing and service.

• ΔC matching check: confirm matching window meets the symmetry budget.
• Leakage bins: verify leakage limits at temperature corners meet the project budget.
• Pin-map symmetry confirmation: ensure substitute lots/vendors keep symmetric pin pairing.

The same board can become more fragile over time if contamination, rework heat, or repeated stress shifts leakage or symmetry. Production controls and audits prevent latent drift.