Topology vs. Op-Amp Choice for Active Filters
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Active filter performance is usually limited by the amplifier’s real capabilities—not the equations. Choose the topology by what the op-amp can guarantee under your actual load (loop gain/phase margin, output drive, noise/distortion entry points, and common-mode control for differential chains).
What this page solves: topology → op-amp choice that works in real hardware
Engineering takeaway: active-filter topology selection is not a pure math exercise. In practice it is governed by loop-gain/phase margin, output-drive stability, and where noise & distortion enter the loop. A “correct” transfer function still fails when the amplifier cannot meet the topology’s dominant constraints.
This chapter translates common active-filter topologies into a pass/fail amplifier checklist. The goal is to prevent the most expensive failure mode in analog filters: the design simulates correctly, but the bench result shows peaking, ringing, elevated noise floor, or unexpected THD/SFDR degradation.
To make the mapping actionable, each topology is treated as a “constraint amplifier”: it amplifies one class of imperfection more than others. The dominant imperfection is the one that should drive amplifier selection (or topology selection when amplifier choice is fixed).
The following “5-line map” is designed for fast use. It links each topology to its dominant constraints and the most common lab symptom when that constraint is violated.
| Topology | Dominant constraints (what matters first) | Typical symptom when under-specified |
|---|---|---|
| Sallen-Key | GBW at target band, output drive, stability with RC/C-load, phase margin under real load | Peaking/ringing near fc, “works at small signal but distorts at level”, intermittent oscillation when connected to ADC |
| MFB (multiple feedback) | Input noise & linearity, Aol(f) in-band, input swing limits, distortion sensitivity to ratios | Noise floor higher than expected, THD/SFDR collapses at modest amplitude, Q & gain shift with frequency |
| State-variable / biquad | Worst-node swing (often BP node), multi-loop stability, SR/THD at internal nodes | One output looks fine while another clips/distorts first; tuning becomes sensitive; unexpected harmonic growth |
| High-Q / notch | Loop gain reserve and phase; sensitivity to small phase errors; amplifier linearity at narrowband peak | Notch depth becomes shallow, notch center shifts, narrowband “buzzing”/ringing appears around notch edges |
| Fully-differential (FDA) | Common-mode control, symmetry, CMRR vs frequency, stable ADC-cap drive, output current/swing | Even-order distortion increases, ADC codes look “odd”, spurs rise with Vcm/RC network changes |
The rest of the page expands this map into specific selection gates (GBW/PM under load, noise entry, distortion vs swing/load, and common-mode constraints for differential chains). The objective is a repeatable, supply-chain-friendly method: when the amplifier is fixed, the topology is chosen to fit what the amplifier can actually do.
A decision flow that never lies: choose topology by what the amplifier can actually do
Real projects rarely allow “any amplifier”. Supply chain, cost, power rails, and existing BOM constraints often fix the amplifier family first. A robust filter design process therefore starts from amplifier reality and backs into topology. This prevents late-stage surprises: designs that simulate well but fail when connected to the true load (ADC sampling capacitance, cable capacitance, low impedance, or common-mode constraints).
Rule of thumb: If the amplifier is fixed, topology should be chosen to minimize the amplifier’s “dominant weakness” (output-drive stability, input noise/linearity, loop-gain reserve, or common-mode control).
The flow below is built from four “forks” that map directly to hardware pass/fail checks. Each fork includes: what to ask, why it matters, and what to verify (datasheet or bench).
-
Fork 1 — Single-ended or differential?
Why it matters: differential chains require controlled output common-mode (Vcm), symmetry, and stable drive into ADC sampling networks—often best served by an FDA.
Verify: FDA Vcm range, CMRR(f), output swing vs Vcm, stability guidance for capacitive/RC loads. -
Fork 2 — Is the load heavy? (ADC sampling capacitance, long cable, low impedance)
Why it matters: heavy loads create extra poles/phase lag and raise output-stage distortion; many “filter problems” are actually load-stability problems.
Verify: capacitive load stability region, recommended isolation resistor, output current at target swing, THD vs load. -
Fork 3 — Is the design SNR-limited or THD/SFDR-limited?
Why it matters: MFB often exposes input noise/current noise and input linearity; Sallen-Key often exposes output drive linearity and stability under load.
Verify: en/in and 1/f corner (for in-band noise), THD/SFDR vs frequency and output swing, slew rate/full-power bandwidth. -
Fork 4 — Is Q high (narrowband/notch/peaking sensitive)?
Why it matters: high-Q or deep-notch designs magnify finite loop gain and phase errors; marginal phase margin becomes visible as peaking, ringing, or shallow notch depth.
Verify: loop-gain reserve (GBW/Aol(f) headroom), phase margin guidance, distortion near the narrowband peak.
After these four forks, topology selection becomes a short list rather than guesswork: Sallen-Key tends to be preferred when output drive and stability are strong; MFB is preferred when input noise and linearity are excellent; SVF/biquad is chosen when multiple responses or tunable Q are required; FDA-based differential is chosen when common-mode control and ADC-drive symmetry are primary constraints.
The common physics: loop gain, phase margin, and where errors enter
Different active-filter topologies “stress” different amplifier imperfections, but the physics is shared. Real-world deviations (Q error, fc shift, peaking, ringing, elevated noise, or degraded THD/SFDR) can be traced to loop-gain reserve, phase margin under the actual load, and where noise/distortion is injected.
Field symptoms map to physics:
(1) Insufficient loop gain → Q error, fc drift, passband ripple.
(2) Insufficient phase margin → peaking, ringing, intermittent instability.
(3) Weak output stage (swing/drive/cap-load behavior) → THD rises and phase lag increases, making Q appear “soft” or unpredictable.
The table below is a fast diagnostic tool. It lists four dominant error sources, what they look like on the bench, which topology is most sensitive, and the first datasheet/bench check that typically resolves ambiguity.
| Error source | Typical symptom | Topology most affected | First check (datasheet/bench) |
|---|---|---|---|
| Finite GBW / Aol(f) roll-off | Q shifts, fc drifts, passband ripple appears; notch becomes shallow | High-Q, notch, SVF/biquad; also any 2nd-order near bandwidth limit | Check Aol/GBW curves; sweep response to locate peaking growth vs frequency; reduce Q and compare |
| Input noise (en/in) + source impedance | Noise floor higher than expected; “quiet” sim becomes noisy hardware | MFB (especially with higher R values), high source-Z sensors | Compare noise with input shorted vs with source-Z; check en/in + 1/f corner; verify resistor levels |
| Output swing/current + capacitive-load stability | Peaking/ringing only when connected to ADC/cable; THD worsens with amplitude | Sallen-Key; ADC-driver stages; any topology with heavy RC/C-load | Disconnect load and compare; add isolation-R; check datasheet cap-load stability guidance and THD vs load |
| Input CM range / output CM control (differential) | Even-order distortion rises; spurs change with Vcm; ADC codes look “odd” | FDA differential filters / SE↔diff converters | Sweep Vcm (if available); check CMRR vs f; verify output swing vs Vcm and stability into ADC sampling network |
With this shared model, each topology chapter becomes simple: identify the dominant injection point, then select the amplifier to harden that point (or choose a topology that avoids the amplifier’s known weakness).
Sallen-Key: why GBW and output drive dominate (and when it quietly fails)
Sallen-Key filters are popular because the topology is simple and component count is low. In hardware, however, the amplifier is often forced into a buffer + driver role that must remain stable while driving a frequency-dependent impedance. This is why Sallen-Key success is frequently governed by output-stage behavior and phase margin under real load, not by the ideal transfer function.
What dominates in Sallen-Key:
(1) Output drive + cap-load stability sets ringing/peaking and can add phase lag that reshapes Q.
(2) GBW headroom limits how faithfully the intended Q and fc are realized, especially near the top of the band.
(3) Large-signal behavior (swing/current/SR) controls THD and can “soften” the filter shape under level.
Typical quiet-failure modes show up as “almost correct” results that still break system requirements:
- Low frequency looks correct, but high-frequency shows peaking or ringing. (Phase margin is consumed by load poles and finite loop gain.)
- Changing the op-amp or capacitor type suddenly flips stability. (The stability margin is narrow; small parasitic changes move the pole/zero balance.)
- THD suddenly worsens at larger amplitude. (Output stage or slew behavior becomes dominant, especially with capacitive drive.)
The checklist below converts amplifier specs into selection gates for Sallen-Key use. Each gate includes a “why” and a quick bench action that helps isolate the root cause without redesigning the whole filter.
| Selection gate | Why it matters in Sallen-Key | Failure signature | Fast bench action |
|---|---|---|---|
| Phase margin under load | Output sees RC network plus real Cload/ADC; extra poles reduce PM and create peaking/ringing. | Ringing near fc; stable in sim but unstable on board; “connect ADC → oscillation”. | Disconnect load; add isolation-R; compare response change to confirm cap-load sensitivity. |
| GBW headroom / Aol(f) | Finite loop gain reshapes Q and shifts fc; margin shrinks near the band edge. | Measured Q differs from design; fc drifts; passband ripple appears. | Reduce Q target and re-test; if response improves sharply, loop-gain reserve is the limiter. |
| Output current & capacitive drive | Capacitive drive demands peak charge/discharge current; non-ideal drive adds distortion and phase lag. | THD increases with amplitude; spurs appear; waveform edges show “tails”. | Lower amplitude/frequency; compare THD; change load C to check whether distortion tracks drive demand. |
| Slew / full-power behavior | Large-signal operation can become slew-limited, producing harmonics that look like filter “wrongness”. | THD collapses at modest amplitude; higher harmonics rise quickly with level. | Reduce amplitude by 6–12 dB; if THD improves strongly, SR/full-power behavior is the main limiter. |
| Swing headroom (rails) | Near-rail operation degrades linearity and can alter stability; Q becomes level-dependent. | Good at mid-supply but worse near rails; distortion and peaking vary with operating point. | Shift bias point (if possible) and compare; verify output swing margin at target frequency and load. |
Practical implication: if the available amplifier is weak in output drive or cap-load stability, a topology that pushes stress to the input side (or uses an FDA/driver stage) often yields a more predictable outcome than forcing Sallen-Key to operate on a narrow stability margin.
MFB: why input noise & distortion dominate (and why ratios feel “friendly”)
Multiple-feedback (MFB) filters place the amplifier inside an inverting, loop-shaping structure. In hardware, this pushes sensitivity toward the front end: input-referred noise terms (en/in) and the amplifier’s input linearity show up prominently in the passband. The payoff is that many target responses can be achieved with “friendly” component ratios, but the trade is that noise matching and large-signal linearity become first-order constraints.
MFB in one line: when the feedback network does the shaping, the dominant errors enter near the input summing region—so en/in, input swing/headroom, and THD vs frequency & amplitude often decide success before GBW does.
Typical bench failures are “quiet” at first because the magnitude response looks correct at small signal, while noise floor or SFDR misses the system target. The table below maps symptoms to root causes and the fastest confirmation checks.
| Field symptom | Most likely root cause | Why MFB is sensitive | Fast confirmation |
|---|---|---|---|
| Noise floor higher than expected | en/in not matched to source impedance; resistors too large; 1/f enters passband | Noise is injected near the summing region and projected into the passband by impedance ratios | Compare noise with input shorted vs with source-Z; re-scale R network (same ratios) and compare |
| Small-signal OK, THD/SFDR collapses at level | Input stage or output stage leaves linear region under target swing; SR/full-power behavior limits | Loop-shaping plus large feedback currents expose nonlinearity at the input and output under stress | Reduce amplitude by 6–12 dB and re-measure; if THD improves sharply, large-signal behavior is dominant |
| Response changes with bias point | Input common-mode range or output swing headroom insufficient under single-supply bias | MFB often uses a biased “virtual ground” and relies on headroom for linearity | Shift bias/Vcm (if available) and compare; verify datasheet input CM range and output swing vs load |
| “Ratios feel friendly” but performance still misses | Correct fc/Q achieved, but noise/THD not validated at target frequency & swing conditions | Component ratios help set the response, but do not guarantee noise/linearity in-band | Check THD vs frequency and vs Vout curves at the actual test condition; validate en/in curves |
Practical selection gates for MFB filters:
- Noise matching: prioritize low en when source impedance is low; prioritize low in and low 1/f corner when source impedance or resistor levels are high.
- Linearity where it matters: verify THD/SFDR is specified (or measured) at the target frequency, target swing, and expected load.
- Headroom & bias: ensure input common-mode range covers the chosen bias point and output swing stays away from rails under the worst-case amplitude.
State-variable & biquads: multiple outputs, multiple constraints (stability + dynamic range)
State-variable filters (SVF) and biquad realizations are common when a design needs multiple simultaneous outputs (LP/BP/HP/notch), tunable Q, or an easy path to higher order filtering via modular building blocks. In practice, the main challenge is not “can it be built”, but that different internal nodes and different outputs run at different dynamic ranges. The best amplifier choice is therefore determined by the worst-case node, not by the output that looks clean on a scope.
Key idea: the BP node often has the largest swing, so it tends to hit slew/linearity limits first. Multi-loop structures also make phase margin and device consistency more visible—marginal stability can appear as “Q tuning instability” or unexpected ringing even when one output still looks acceptable.
Common field signatures (and what they usually mean):
- LP output looks clean, BP output distorts or clips first. (The internal “worst node” has exceeded swing/SR/linearity headroom.)
- Ringing appears when Q is increased. (Multi-loop phase margin reserve is insufficient at the target frequency.)
- One response deviates while others seem fine. (Node-to-node dynamic range or loop-gain distribution is uneven.)
Selection gates should be anchored to the worst-case node (commonly BP). Verify that the amplifier meets targets at the largest internal swing, at the operating frequency, and under the expected load and bias.
| Gate | Why it becomes dominant | Failure signature | Fast confirmation |
|---|---|---|---|
| Worst-node swing headroom | Internal nodes (often BP) can run larger than the observed LP output, especially at higher Q. | BP clips/distorts first; “filter shape” changes with level. | Probe BP node; reduce Q or amplitude; if distortion collapses, worst-node headroom is limiting. |
| Slew rate / full-power behavior | Large internal swing at the BP node raises dV/dt demand; SR limitation produces harmonics. | High harmonics rise rapidly as level increases; BP looks “triangular”. | Reduce amplitude 6–12 dB and compare THD; if improved strongly, SR/full-power behavior is dominant. |
| Phase margin / multi-loop stability | Multiple loops and integrators stack phase; weak reserve shows up as ringing when Q is increased. | Q tuning becomes “touchy”; ringing or near-instability appears. | Lower Q and re-test; if ringing disappears abruptly, stability margin is the limiter. |
| THD vs f and vs swing | Even when magnitude response is correct, nonlinearity at internal nodes can dominate SFDR. | LP looks fine but SFDR misses target; spurs rise with Q or level. | Validate THD/SFDR at operating frequency and worst-node swing conditions, not only at low level. |
Notch & high-Q cases: where finite Aol turns into shallow notch / notch shift
Deep notch and high-Q designs are uniquely sensitive because their performance depends on very accurate amplitude-and-phase conditions around a narrow frequency region. In practice, finite open-loop gain versus frequency (Aol(f)) and limited GBW introduce small amplitude/phase errors that would be harmless in low-Q filters, but here they directly translate into shallower notch depth, center-frequency shift, and greater temperature/lot sensitivity.
Deep-notch reality: notch depth is often limited by loop-gain and phase accuracy, while component drift/mismatch consumes margin. The amplifier must provide extra Aol/GBW and stable phase margin so that inevitable passive errors do not “fill in” the notch.
Use the mapping below to connect field symptoms to the dominant mechanism, and to decide whether the amplifier is the limiting factor (versus passive matching/thermal drift that should be handled elsewhere).
| Field symptom | Most likely mechanism | Why high-Q/notch amplifies it | Fast confirmation |
|---|---|---|---|
| Notch depth is shallow | Finite Aol/GBW introduces amplitude/phase error near the cancellation point | Small phase error breaks cancellation; the notch “fills in” | Lower Q/relax notch target and compare; if depth improves sharply, loop-gain reserve is limiting |
| Notch center shifts | Phase margin reduced by real load poles or internal phase lag; effective response rotates | High-Q sensitivity turns extra phase into measurable f0 movement | Disconnect downstream load / reduce Cload; if f0 moves back, load-induced phase is dominant |
| Depth changes with temperature | Passive drift/mismatch changes cancellation condition; amplifier margin is too tight | Any drift consumes cancellation margin; finite Aol makes it more visible | Heat/cool and measure depth change; if depth varies strongly while topology stays stable, margin is insufficient |
| Depth collapses at larger signal | Nonlinearity under stress (swing/SR/drive) adds harmonics and distorts phase | High-Q regions increase sensitivity to distortion and phase perturbation | Reduce amplitude by 6–12 dB; if notch depth improves, large-signal behavior dominates |
Amplifier requirements must be tightened for high-Q and deep-notch cases:
- Higher GBW and stronger Aol(f) reserve to reduce amplitude/phase error near the notch.
- Better phase margin under the real network and load to prevent notch shift and peaking around the sensitive region.
- Linearity at the operating frequency and swing so the notch does not “fill in” under level.
- Predictable thermal behavior (bias and operating point remain stable) so passive drift does not consume all margin.
Differential filters & FDAs: common-mode control is the whole game
Differential filters and ADC front ends are not simply “two copies” of a single-ended path. The dominant requirement is controlled common-mode and symmetry: the output common-mode must match the ADC’s recommended operating point, both outputs must be driven with matched amplitude/phase and matched impedance, and the driver must remain stable while charging sampling capacitors through the RC network. This is why a fully differential amplifier (FDA) is often the cleanest solution: it provides explicit VOCM/Vcm control, balanced outputs, and predictable behavior across load and bias.
Differential success criteria: correct differential amplitude is necessary but not sufficient. The common-mode loop and symmetry typically decide THD/SFDR, noise, and “strange ADC codes” in real systems.
Common failure signatures map cleanly to common-mode control and symmetry problems:
| Field symptom | Most likely cause | Why it happens in differential chains | Fast confirmation |
|---|---|---|---|
| THD gets worse after SE→diff | VOCM mismatch or reduced headroom; unstable interaction with sampling cap/RC | Large dynamic currents and bias dependence expose nonlinearity and phase error | Adjust VOCM/Vcm (if available) and compare THD; add/increase Riso and observe ringing/THD change |
| Noise increases after conversion | CMRR insufficient in-band; asymmetry converts CM noise to differential error | Layout/network imbalance degrades effective CMRR at the frequency of interference | Measure CM at ADC pins; improve symmetry (matched R/C) and check if noise floor improves |
| ADC codes look “odd” | Common-mode drifts or violates ADC input window | ADC performance is strongly tied to input common-mode operating point | Measure (Vout+ + Vout−)/2; confirm it stays within ADC recommended Vcm across conditions |
| Even-order spurs rise | Output mismatch (gain/phase/impedance) or unbalanced RC network | Mismatch converts differential to common-mode and re-injects as even-order distortion | Match Riso and RC components tightly; compare 2nd harmonic vs mismatch changes |
Selection gates for FDAs in differential filters and ADC drivers:
- VOCM/Vcm control range: must cover the ADC’s required common-mode point with margin.
- Output swing & drive capability: verify swing and linearity at the target frequency and load (including dynamic sampling currents).
- Stability into RC + sampling capacitance: check guidance for capacitive load; use isolation resistors when needed.
- CMRR vs frequency: in-band CMRR matters more than DC CMRR for real interference and noise suppression.
- THD vs VOCM and vs load: confirm distortion stays low as common-mode and load conditions vary.
Selection checklist: translate specs into pass/fail gates (GBW, SR, noise, THD, load)
This checklist converts datasheet specs into pass/fail gates that match real filter behavior. Each gate is written as: Why it matters → What to look for → Typical symptom. Example part numbers are included as “known reference options” to speed up A/B validation—final selection should always be confirmed under the exact topology, load (including ADC sampling), swing, and bias.
How to use the gates: define the operating point first (target frequency/Q/order, max swing, load/Csample, single-supply vs dual, required Vcm). Then check each gate against the worst node (often the largest-swing internal node for SVF/biquads, or the sampling-load node for ADC drivers).
- Why it matters: insufficient loop gain at the operating frequency turns into Q/fc error, notch shallowing, peaking, or response “softening”.
- What to look for: curves or application notes that indicate usable loop gain/GBW margin near the target band (not only DC Aol).
- Typical symptom: response is “close” at low Q, but drifts or peaks when Q increases, when load changes, or when temperature shifts.
- Why it matters: datasheets often show stability on light loads; ADC sampling networks can add poles that reduce phase margin and create ringing/spurs.
- What to look for: “capacitive-load stability” guidance, step response vs Cload, recommended isolation resistor (Riso) ranges, and settling behavior.
- Typical symptom: peaking/ringing appears only after connecting the ADC, or only with one RC network value; SFDR drops unexpectedly.
- Why it matters: high-Q or SVF/biquad internal nodes can swing more than the observed output; slew-limiting causes abrupt THD rise.
- What to look for: full-power bandwidth / large-signal settling behavior; THD vs level curves near the operating frequency.
- Typical symptom: small-signal looks correct, but THD “falls off a cliff” above a certain amplitude or Q setting.
- Why it matters: MFB often exposes input-referred noise more strongly; resistor level and source impedance decide whether en or in dominates.
- What to look for: voltage noise + current noise + 1/f corner; validate under the actual bias and frequency band (not a single “typical” point).
- Typical symptom: magnitude response meets target, but noise floor is higher than expected; noise changes sharply with source impedance.
- Why it matters: THD is condition-dependent; differential chains add even-order sensitivity to symmetry and common-mode behavior.
- What to look for: THD/SFDR curves vs frequency and output level; for differential paths, THD vs VOCM and vs load.
- Typical symptom: “spec looks great” but spurs rise at the operating frequency, at the required swing, or after SE→diff conversion.
- Why it matters: ADC sampling caps demand high dynamic current; unstable interaction creates ringing, settling errors, and SFDR loss.
- What to look for: datasheet guidance for driving capacitive loads and for ADC-driver use cases; recommended Riso and external RC examples.
- Typical symptom: connecting the ADC introduces spikes/settling issues; changing Riso or Cload changes spurs dramatically.
- Why it matters: single-supply designs often “calculate correctly” but fail because the input CM or output swing cannot reach the operating point.
- What to look for: input CM range at the selected bias point; output swing vs load near rails; behavior across temperature and supply tolerance.
- Typical symptom: THD rises near one rail; offset or bias-dependent distortion appears; response changes with small bias shifts.
A practical bring-up approach is to keep a small, diverse set of “reference amplifiers” on hand to isolate which gate is failing.
| Role | Example part numbers | What it helps isolate |
|---|---|---|
| Low noise bipolar | ADI AD797; LT/LTC LT1028; TI OPA211 | Noise floor vs source-Z; notch/high-Q loop-gain sensitivity |
| Low noise FET | TI OPA140; TI OPA2140 | Bias current / high source impedance noise behavior |
| Low distortion audio | TI OPA1612; TI OPA1656; ADI ADA4625-2 | THD/SFDR limits at operating frequency and swing |
| High-speed / strong drive | ADI ADA4807-1; ADI ADA4898-2; TI OPA828 | Load stability, ringing, settling into RC/Cload |
| FDA for differential ADC | TI THS4551; TI THS4541; ADI ADA4940-1; LT/LTC LTC6363 | VOCM control, even-order spurs, driving Csample |
Bring-up & debug: symptoms → root causes → fastest tests
This section provides a field-ready mapping from observed behavior to the most likely root causes, plus the fastest tests to separate “topology limitations” from “amplifier/load interaction”. The same symptom language can be reused directly in FAQs and support playbooks.
Rule of thumb: first isolate the load (especially ADC sampling), then isolate large-signal behavior (amplitude/Q), then isolate noise entrance (source impedance / resistor level). That order prevents wasted iterations.
| Symptom | Likely root causes | Fastest tests (separate variables) | Swap parts to confirm |
|---|---|---|---|
| Peaking / ringing | Phase margin reduced by Cload/RC; GBW margin insufficient; output stage interaction with sampling currents | Change Riso / reduce Cload; disconnect ADC and replace with a controlled dummy load; compare step response | ADI ADA4807-1; ADI ADA4898-2; TI OPA828 |
| Notch is shallow or f0 shifts | Finite Aol(f) / phase accuracy near cancellation; load-induced phase error; margin consumed by drift (passive effects not expanded here) | Reduce Q/relax notch target and compare; remove downstream load; validate whether notch depth returns | TI OPA211; TI OPA188; ADI ADA4522-2 |
| Noise floor is high | MFB input noise entrance dominates; source impedance + resistor level mismatch; 1/f corner enters band | Short input vs connect source-Z; scale resistor level (keep ratios) and compare; verify low-frequency noise trend | ADI AD797; LT/LTC LT1028; TI OPA140 |
| THD worsens sharply with amplitude | Slew rate / full-power behavior; output swing headroom; output current under dynamic load | Reduce amplitude 6–12 dB; reduce bandwidth/order temporarily; compare THD change to identify large-signal limit | TI OPA1612; TI OPA1656; ADI ADA4625-2 |
| Even-order spurs high (diff chain) | Asymmetry (R/C/layout); VOCM drift; in-band CMRR insufficient; sampling network perturbs balance | Check (V+ + V−)/2 stability; match Riso/RC precisely; swap outputs; validate spur sensitivity to mismatch | TI THS4551; ADI ADA4940-1; LT/LTC LTC6363 |
| ADC “codes look odd” | Input common-mode violates ADC window; CM loop interaction; settling errors into Csample | Measure input common-mode at ADC pins; disconnect ADC and test with dummy load; add Riso and re-check settling | TI THS4541; ADI ADA4945-1; TI THS4551 |
- Load isolation: disconnect the ADC and replace it with a controlled dummy load; re-add RC and Csample step-by-step to localize the instability or settling limiter.
- Riso sweep: change isolation resistor value and observe ringing/spurs; strong sensitivity indicates a phase-margin / sampling-load interaction.
- Amplitude drop test: reduce output amplitude by 6–12 dB; if THD improves abruptly, the limiter is large-signal (SR/headroom/drive), not small-signal response.
- Topology A/B: swap between Sallen-Key and MFB (keeping fc/Q close) to identify whether the dominant entrance is output-drive (SK) or input noise/linearity (MFB).
- Differential sanity checks: verify symmetry (matched R/C and routing) and common-mode stability ((V+ + V−)/2); even-order spurs often track these directly.
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FAQs: topology symptoms, root causes, fastest tests, and swap parts
Each answer stays within this page boundary: topology ↔ op-amp choice. The “swap parts” are reference candidates for fast A/B isolation (final selection must be verified under the exact load, swing, and bias conditions).
› Sallen-Key calculates the right Q—why does measurement show obvious peaking?
The most common cause is phase margin collapse under the real load, not the math. Sallen-Key pushes the op-amp output stage to drive the RC network, and ADC sampling (Csample + kickback) often adds a hidden pole that turns “barely stable” into peaking.
- Fast tests: disconnect the ADC and use a dummy load; sweep isolation resistor (Riso) and observe peaking sensitivity.
- Gates to check: Gate B (PM under load), Gate F (drive/Cload), then Gate A (Aol(f)/GBW).
› Why does MFB make op-amp noise more “visible”, while Sallen-Key can look cleaner?
MFB places the amplifier inside an inverting shaping loop where input-referred noise couples directly through the noise gain and impedance ratios. With higher resistor values or higher source impedance, current noise and 1/f corner can dominate quickly. Sallen-Key often appears “cleaner” because other limits (drive/stability) can dominate before noise becomes obvious.
- Fast tests: scale resistor values down (keep ratios); vary source impedance and compare noise floor changes.
- Gates to check: Gate D (en/in/1/f), plus Gate A if high-Q response shape also shifts.
› GBW is “enough” but the circuit is still unstable—what hidden pole usually causes it?
The most common hidden pole is created by output-stage interaction with capacitive/dynamic loads: ADC sampling caps, input clamps, long traces, or an RC network placed “inside” the effective loop. This reduces phase margin even when GBW looks adequate on paper, especially if datasheet stability is shown only on light loads.
- Fast tests: sweep Riso and compare step response; disconnect ADC and reintroduce RC/Csample incrementally.
- Gates to check: Gate B (PM under real load) and Gate F (capacitive stability), then Gate A.
› THD collapses at higher output amplitude—suspect slew rate or output current first?
A quick discriminator is the amplitude drop test. If reducing output level by 6–12 dB dramatically improves THD, slew-rate/full-power behavior (or headroom) is usually the limiter. If THD improves more when disconnecting the ADC or reducing Cload, output current and dynamic drive into sampling networks are more likely.
- Fast tests: -12 dB amplitude; then disconnect ADC/dummy-load comparison.
- Gates to check: Gate C (SR/full-power) vs Gate F (drive/Cload) and Gate G (headroom).
› Same op-amp becomes hard to tune at high-Q/narrowband—why does high Q demand more loop gain?
High-Q responses amplify small magnitude/phase errors: finite Aol(f) and phase lag around the operating band translate into larger Q error, notch shallowing, and frequency shift. What looked “fine” at low Q can become sensitive to load and temperature because the loop-gain margin is consumed more quickly.
- Fast tests: reduce Q and observe whether the response “snaps back”; remove load and compare notch depth/peaking.
- Gates to check: Gate A (Aol(f)/GBW margin) and Gate B (PM under load).
› Can dual op-amps replace an FDA for differential filters? When is an FDA mandatory?
Dual op-amps can form a differential path, but FDA solutions provide native common-mode control (VOCM), symmetry, and predictable ADC-drive behavior. An FDA becomes effectively mandatory when the chain must set VOCM precisely, minimize even-order distortion, maintain balance over frequency, and drive sampling capacitors with stable settling.
- Fast tests: compare even-order spurs and settling with the same RC/Csample using an FDA driver reference design approach.
- Gates to check: Gate B/F for settling/stability and H2-8 common-mode control rules.
› FDA drives ADC: VOCM is correct, but codes look odd or spurs are high—why?
A correct static VOCM does not guarantee dynamic common-mode stability and symmetric settling during sampling kickback. Spur-heavy behavior often comes from imbalance (RC mismatch, unequal loading) or insufficient settling into Csample. The symptom typically tracks Riso/RC changes and the presence of the ADC more than it tracks the nominal VOCM setting.
- Fast tests: probe both ADC pins and verify (V+ + V−)/2 stability; disconnect ADC, then re-add RC/Csample step-by-step; swap outputs to see if spurs follow imbalance.
- Gates to check: Gate B/F and H2-8 symmetry/common-mode rules.
› In MFB, when does current noise (in) become more critical than voltage noise (en)?
Current noise becomes dominant when effective input impedance is high: high source impedance, large feedback/input resistors, or low-frequency operation where 1/f rises. In those cases, in·R converts to a large input-referred voltage term and shows up as elevated in-band noise. MFB tends to expose this faster because the inverting node sets the noise gain.
- Fast tests: reduce resistor values by 5–10× (keep ratios) and check whether the noise floor drops meaningfully.
- Gates to check: Gate D (en/in/1/f) and resistor-level dependence.
› Stable on light load, rings with ADC: how to place isolation resistor without ruining phase/magnitude?
ADC sampling creates a dynamic capacitive load; the isolation resistor should act as a stability valve at the driver output, keeping Csample “outside” the effective loop. Too small Riso fails to isolate the sampling pole; too large Riso can interact with the RC network and shift amplitude/phase. The correct value is verified by step response and SFDR sensitivity.
- Fast tests: sweep Riso while measuring at ADC pins; disconnect ADC and compare; re-add RC/Csample gradually to identify the threshold of ringing.
- Gates to check: Gate B (PM under load) and Gate F (drive/Cload).
› Why does Sallen-Key hit output-drive limits more easily than MFB at the same fc?
In Sallen-Key, the op-amp frequently behaves like a buffer/driver for a reactive network, so output current, capacitive stability, and dynamic phase lag directly shape Q and distortion. MFB keeps the shaping inside a tighter feedback structure and often reduces direct capacitive stress on the output node, making drive limitations appear later (though noise/linearity can surface earlier).
- Fast tests: increase load capacitance and check whether Q/peaking shifts; add Riso and compare distortion/settling changes.
- Gates to check: Gate F (drive/Cload) and Gate B (PM under load).
› SVF/biquad multi-output: which node distorts first, and how to pre-budget it?
In SVF/biquads, the earliest distortion often occurs at the largest-swing internal node (commonly the band-pass/integrator node), not at the final low-pass output. Budgeting should treat the worst node as the primary constraint: set SR/headroom/THD gates based on that node’s expected swing, then verify by probing the node and observing how THD changes when Q or amplitude is reduced.
- Fast tests: monitor the high-swing node; reduce Q and compare THD improvement; isolate load to avoid confusing node-limits with drive-limits.
- Gates to check: Gate C (SR/full-power) and Gate E (THD/SFDR), then Gate G (headroom).
› What single A/B experiment can tell whether the issue is topology-driven or op-amp-driven?
A reliable one-pass isolation uses three steps: (1) isolate the load (disconnect ADC, use a dummy load), (2) topology A/B (implement Sallen-Key and MFB with similar fc/Q), then (3) swap amplifier categories using a small reference kit. If the problem disappears only when the ADC is removed, the limiter is drive/settling. If topology changes shift noise/THD behavior strongly, the entrance point is topology-driven.
- Fast tests: disconnect ADC → topology swap (SK↔MFB) → swap kit (noise vs drive vs FDA).
- Gates to check: Gate B/F first, then Gate D/E/C depending on symptom.
