What this page solves

This page focuses on the secondary side of isolated AC adapters: from the transformer secondary and synchronous rectifier, through the regulation loop, out to low-voltage rails, LEDs and basic housekeeping I/O. Typical targets include 5–65 W wall-warts, phone and IoT chargers, and 90–250 W notebook or gaming-laptop bricks.

In these adapters, load conditions can swing rapidly: phone fast-charge negotiation, notebook plug-in or removal, sudden CPU/GPU load steps or an external hub drawing bursts of current. Poorly designed secondary power often shows up as deep voltage sags, slow recovery, excessive overshoot, audible noise or LEDs that flicker and look unstable.

Another frequent issue appears when the main output rail is combined with several small rails such as 3.3 V logic, indicator LEDs, bias for optocouplers or USB-PD controllers. If start-up sequencing and power-good logic are treated as afterthoughts, adapters pass bench measurements but misbehave in the field: devices reset during start-up, USB-C negotiation falls back to lower profiles, or status LEDs flash in ways that trigger customer complaints.

Component substitutions can amplify these weak points. Replacing a synchronous rectifier controller, secondary-side regulator or small LDO with a similar-looking part may change SR turn-off delay, power-good thresholds or bias current. Without a clear secondary-side architecture, such changes create intermittent field failures that are difficult to reproduce in the lab.

The role of this page is to treat secondary power as its own subsystem: synchronous rectification after the transformer, secondary-side regulation behavior, low-voltage LDO/buck rails for controllers and LEDs, and the power-good and indicator glue that connects the adapter to the outside world.

Topics such as primary-side start-up, burst or valley switching and spread-spectrum control are covered in the Adapter Primary Controller page. High-speed GaN gate drive, CMTI and Miller management belong to GaN Driver for Adapters. USB-C PD/QC/PPS negotiation, PDO/PPS profiles and cable authentication are handled in USB-C PD/QC/PPS Controller. Upstream eFuse, hot-swap and hold-up functions are detailed in eFuse & Hot-Swap and Hold-Up / Backup for Adapters.

Secondary-side scope, interfaces & constraints

For the rest of this page, the secondary power domain starts at the transformer secondary and the synchronous rectifier or diode bridge, passes through the LC output filter and regulation path, and extends out to the adapter output connector and low-voltage housekeeping rails. This definition keeps the focus on behavior that lives entirely on the safety-isolated side of the design.

On the left boundary, energy arrives from the isolation transformer into a synchronous rectifier FET stage or a simpler diode topology. This block converts high-frequency secondary waveforms into a rectified waveform that the output inductor and capacitor bank can smooth. Transformer design, primary switching strategy and magnetics optimization are handled in the primary-side and topology-specific pages; here the synchronous rectifier is treated as part of the secondary power subsystem because its timing and losses strongly affect efficiency and thermal behavior.

The center of the secondary domain contains the output inductor, the capacitor array and the feedback path. The choice of sampling point, remote-sense routing and error-amplifier connections determines what the primary controller “sees” when VOUT responds to load steps. From the secondary perspective, the important questions are where to sense the output, how to route sense lines cleanly and how to expose a stable, well-conditioned feedback signal across the isolation barrier to the primary controller or digital isolator.

On the right side, the secondary domain interfaces with the outside world. The main DC output rail feeds the adapter connector and, in many designs, an internal tree of small buck or LDO rails that power USB-PD controllers, microcontrollers, logic and indicator LEDs. Downstream PoL converters, USB-C power paths, eFuse and hot-swap stages and hold-up or backup subsystems appear as intelligent loads with expectations on ramp shape, regulation, power-good timing and inrush behavior rather than as part of this page’s design scope.

The upward interface to the primary controller is defined by the feedback signal crossing isolation. This can be implemented with a classic optocoupler, a digital isolator carrying PWM or error information, or an isolation amplifier that exposes a scaled version of VOUT. The details of loop compensation, modulation strategy and drive timing belong to the primary-side control pages; the secondary power design must simply provide a clean, well-placed sense point and an error signal that is robust against noise and layout parasitics.

Several practical constraints shape this secondary scope. Safety requirements such as isolation class and creepage distances limit placement of LDOs, buck converters and sense traces and define the relationship between secondary ground, chassis and protective earth. Efficiency targets restrict how much power can be burned in linear regulators, pushing designs toward small buck stages followed by LDOs only where low noise is critical. Standby and no-load power limits mean secondary controllers and housekeeping rails must tolerate burst or skip operation on the primary side without causing unstable LEDs, repeated resets or negotiation failures.

With this scope, secondary power is defined as everything from the transformer secondary and rectification, through the LC filter and feedback network, up to the main DC output, auxiliary rails, power-good signals and indicators. Primary controllers, GaN drivers, USB-C protocol ICs and upstream protection remain separate building blocks with their own dedicated design pages.

Synchronous rectification topologies & control strategies

Rectification on the secondary side sets the baseline for adapter efficiency and thermal performance. At low power levels a Schottky diode can still meet loss and temperature limits. As designs move into 19 V notebook space with several amperes of load current, diode forward loss quickly grows into multiple watts of heat inside a compact enclosure, forcing larger heatsinks or lower output power. Synchronous rectifier MOSFETs reduce conduction loss dramatically but require an appropriate topology and control strategy to avoid reverse current and light-load instability.

In flyback adapters, the secondary rectifier sees pulsed current and a changing polarity across the transformer winding. The synchronous FET must turn off promptly when current decays to zero or when the primary starts the next conduction interval. Some controllers integrate SR drive inside the primary IC and derive timing from primary gate signals. Others implement a dedicated secondary-side SR controller that monitors secondary drain or winding voltage directly. Integrated approaches offer tight timing and fewer components, while discrete SR controllers provide flexibility across multiple flyback and forward designs if their thresholds and delays are matched to the transformer and switching frequency.

In LLC-based adapters, secondary synchronous rectification must deal with near-sinusoidal currents and phase shifts between voltage and current. Full-bridge, center-tap and half-bridge rectifier structures each expose different node swings and dv/dt to the SR controller. Devices must discriminate true conduction intervals from resonant node ringing and tolerate high dv/dt without false turn-on or excessive blanking. As power levels rise and output current increases, these details have a strong impact on both efficiency and EMI.

Control strategies can be grouped into voltage-sensing and current-sensing implementations. Voltage-sensing SR controllers observe FET drain-source voltage or winding voltage to infer conduction direction. They rely on well-chosen thresholds and blanking windows to avoid reacting to ringing or parasitic spikes. Current-sensing SR architectures use shunts or coupled windings to sense real current direction and magnitude, enabling more robust reverse-current suppression at the cost of extra components. In both cases, excessive turn-off delay or overly aggressive filtering can allow reverse current, disturb resonant behavior or increase output ripple.

Light-load and no-load operation require special attention. Adapters often spend long periods at very low load current or in burst and skip modes driven by the primary controller. If the SR stage continues to hunt for conduction windows during these phases, the result can be audible noise, visible output jitter or poor standby efficiency. Practical SR devices therefore include modes that reduce or disable synchronous operation under light load, transition toward diode-like behavior or coordinate with primary burst strategies.

For adapter secondary power design, the key selection criteria for synchronous rectifier and controller devices include supported topologies, turn-on and turn-off delays, blanking times, dv/dt immunity, light-load behavior and gate drive capability. Focusing on these parameters reduces the risk of reverse conduction, field instability and marginal thermal performance even when bench efficiency measurements look acceptable.

Secondary regulation loops & transient performance

Secondary power behavior during load steps and line disturbances is set by how the output voltage is sensed, how the error signal is shaped and how it reaches the primary controller. The regulation path starts at the chosen sampling point on the output rail, passes through a resistive network and possibly a differential amplifier, crosses the isolation barrier and finally drives an error input inside the primary controller or a digital control loop. Even when the control law and compensation are implemented on the primary side, secondary-side sensing decisions strongly influence stability and transient response.

The first choice is where to sense VOUT. Sampling at the capacitor node near the LC filter keeps the sense path short and relatively quiet but ignores voltage drops in cables and connectors. Sampling closer to the adapter output connector or using remote-sense leads allows the system to compensate these drops and keep the load-side voltage within a tight window. In that case, sense traces must be routed as a clean pair with appropriate filtering because injected noise or ground shifts can feed directly into the control loop.

The error amplifier can reside inside the primary controller, inside a dedicated secondary controller or in a discrete op amp that provides differential sensing. Primary-integrated error amplifiers expect a specific sense and compensation network around an optocoupler or isolation amplifier. Secondary-side controllers often integrate an error amplifier and present a conditioned signal to the isolation device, simplifying layout on the primary side. Discrete differential amplifiers help reject common-mode disturbances between secondary ground and the sense point, especially when remote-sense wiring is used or when the connector ground is not tightly coupled to the internal reference plane.

Compensation networks shape the loop to achieve stable operation over the full input and load range. From the secondary perspective, the important aspects are the flexibility offered by the device pins and the placement of RC components that set crossover and phase margins. Whether the final design uses a Type II or Type III compensation structure and how its poles and zeros are positioned are decisions handled in the primary controller and topology-specific design flow; however, component values and layout on the secondary side still affect noise pickup and the accuracy of the sensed voltage.

Transient performance becomes visible when a notebook adapter steps from light load to heavy load, or when a charger switches fast-charge profiles and the effective current demand changes abruptly. During a 10 % to 80 % load step, end users care about how deep the voltage sag is, whether overshoot exceeds downstream device limits and how quickly the output recovers to its regulation band. These behaviors depend on the combined loop gain, the isolation device delay and the dynamic sourcing capability of the secondary LC network and bias rails.

Adapter secondary power ICs influence these results through integrated soft-start, output ramp control and power-good timing. A controlled voltage ramp limits inrush current and protects the secondary rectifier, magnetics and output capacitors during start-up and voltage reconfiguration. Power-good thresholds and delays determine when downstream controllers, USB-C ports or logic rails are allowed to turn on. If PG asserts too early, digital loads may start running while the loop is still settling, leading to brownouts and resets. If PG asserts too late, adapters appear sluggish or fail system-level boot timing requirements.

This section focuses on secondary-side choices: where to sense VOUT, whether to use differential or single-ended sensing, which isolation device to employ and how soft-start and power-good timing are defined. Loop-compensation mathematics and primary modulation strategies are handled in the adapter primary controller design, but the quality of secondary regulation and transient behavior depends strongly on these secondary-side implementation details.

Small rails: LDO/buck rails, indicators & housekeeping I/O

Secondary power does not end at the main DC output. A typical adapter also generates several small rails to supply control logic, USB-PD controllers, microcontrollers, references and visual indicators. Common examples include 5 V and 3.3 V rails for digital interfaces and protection ICs, and 2.5 V or 1.8 V rails for internal digital cores or quiet reference domains. The structure and protection of these rails strongly influence how the adapter behaves during start-up, negotiation and fault events.

When the main output is 12 V or 19 V, small rails can be created through direct LDO drops, small buck converters followed by LDOs, or cascaded combinations. Direct LDO conversion from 19 V to 3.3 V is simple and clean but burns significant power at moderate currents. Using a small buck stage to generate an intermediate 5 V rail and then LDOs for 3.3 V and 1.8 V improves efficiency while keeping noise-sensitive domains on linear regulation. Sensitive loads such as analog references, precision ADCs or PLLs often benefit from a final LDO stage even when their upstream source is a switching rail.

Many LDO and small buck devices expose power-good or reset pins. These outputs can be combined to form a system-level power-good signal that only asserts when all required rails sit within their valid operating window. By wiring PG signals from 5 V and 3.3 V rails into simple logic or a supervisor IC, the adapter can control when USB-PD controllers, microcontrollers and digital interfaces are allowed to start. This approach reduces the chance of configuration attempts, protocol negotiation or memory transactions occurring while rails are still ramping or recovering from disturbances.

Housekeeping I/O driven from these rails include status LEDs, small relays and MOSFET load switches. The available current, output topology and fault behavior of the small-rail converters matter: an LED short or miswired GPIO should not collapse the entire 3.3 V rail and reset the USB-C subsystem. Devices that support per-rail current limiting, short-circuit protection and clear PG behavior allow local faults to be isolated without disturbing the main output or other small rails.

From a selection perspective, secondary-side small-rail solutions should be evaluated not only on efficiency and dropout but also on PG functionality, startup sequencing options, fault protection and the ability to power LEDs and housekeeping outputs without destabilizing the primary control system. A secondary power IC that integrates bias rails, LDOs, buck stages and PG logic reduces external circuitry and gives a more predictable adapter start-up and run-time behavior.

Secondary-side protections & reliability hooks

The primary controller and any upstream eFuse or hot-swap circuit form the first line of defense against catastrophic shorts and overloads. Secondary-side protections complement these functions by shaping how the adapter responds to local faults on the main output and small rails, limiting stress on components and providing clear fault signaling for system firmware and end users. A well-designed secondary protection scheme improves field reliability without masking issues that should be handled by primary current limits and front-end protection.

Common secondary-side stress cases include output short circuits, large capacitive loads and cable hot-plug events. When a discharged load capacitor or long cable is connected, inrush current can be high enough to stress the secondary rectifier, inductor and output capacitors. Soft-start and controlled dv/dt limit this surge and give upstream protection circuits a well-defined profile to work with. Under genuine short-circuit conditions, secondary protections can fold back current or shut down quickly to avoid sustained heating while upstream limits prevent primary-side damage.

Protection of small rails and housekeeping paths is equally important. Shorted LEDs, miswired connectors or overdriven I/O pins can overload a 3.3 V or 5 V rail. If these faults pull down the rail that powers USB-PD controllers or microcontrollers, the entire adapter may exhibit repeated resets, negotiation failures and unpredictable behavior. Secondary power ICs with per-rail current limiting and short-circuit protection allow local faults to be isolated, keeping the main output in regulation while signaling a fault to the system level.

Typical secondary-side protection features include over-voltage and under-voltage protection, over-current and short-circuit protection and thermal shutdown. Over-voltage protection prevents uncontrolled output rise due to feedback path failures or incorrect sense wiring. Under-voltage protection can force a restart or latch-off if a rail remains in a marginal region where digital logic may malfunction. Over-current and short-circuit protection define how aggressively the adapter responds when output current exceeds its rating, whether through constant-current limiting, foldback characteristics or immediate shutdown.

Thermal protection relies on internal die temperature sensing or external NTC sensors placed near hot components on the secondary side. When temperatures exceed defined thresholds, the protection scheme can reduce output current, limit duty cycle or shut down fully until the system cools. Hiccup-mode restart strategies periodically reapply power after a fault to test whether a short circuit or overload has cleared, reducing average power dissipation in the fault condition. Latch-off strategies keep the output disabled until input power is cycled or a control signal is toggled, which is desirable for persistent or safety-critical faults.

Effective adapter designs use secondary-side protections as fine-grained tools that coordinate with primary current limits and upstream eFuse or hot-swap circuits. The secondary domain manages local output behavior, rail-level protection, thermal limits and power-good or fault signaling, while the primary and front-end blocks handle overall energy flow and safety. Together, these layers create a protection system that is both robust and transparent to system integrators.

IC roles mapping for adapter secondary power

Secondary-side control in an adapter is usually split across a small set of functional blocks rather than a single device. Synchronous rectifier controllers and drivers manage conduction losses on the main output. Secondary controllers integrate SR drive, regulation and protection. LDOs and mini bucks create housekeeping rails and supply control logic. Supervisors and reset ICs enforce rail-valid conditions and start-up sequences, while temperature sensors and fan drivers support reliability in higher-power designs. Mapping these roles to the right IC classes avoids both overdesign and fragile, ad-hoc solutions.

Synchronous rectifier controllers and drivers

SR controllers and drivers sit next to the transformer secondary, driving MOSFETs that replace Schottky diodes in flyback, forward and LLC stages. They sense drain-source voltage, winding polarity or current direction to decide when to turn the MOSFET on and off. For adapters in the 30–120 W class, these devices must tolerate high dv/dt, support the target switching frequency and behave predictably in burst and skip modes.

Key selection points include supported topologies (flyback-only versus flyback/forward/LLC), sensing method, maximum dv/dt, light-load behavior and gate-drive capability. Devices in the same class as UCC24610, UCC24612, UCC24624, UCC24636 or SRK1000/SRK2000 families illustrate the range from simple VDS-sensing flyback SR controllers to more advanced controllers capable of handling LLC bridge rectification with improved noise immunity.

Secondary controllers with integrated SR and regulation

Integrated secondary controllers combine SR drive, voltage regulation, error amplification, protection logic and often small bias rails or drivers. They are common in higher-power notebook and gaming adapters where efficiency, transient behavior and telemetry are more tightly specified. These devices accept feedback from the main output and small rails, implement OVP, OCP and OTP, and hand off an error signal or digital command stream to the primary-side controller.

Important parameters include the number of SR channels, support for flyback or LLC structures, presence of integrated error amplifiers and references, PG/FAULT outputs, protection configuration and any PMBus, I²C or proprietary serial interface. Digital power controllers such as UCD3138/UCD3138064 or LTC38xx-class devices show how secondary-side regulation, SR drive and telemetry can be consolidated when building more complex adapter platforms.

Secondary LDOs and mini bucks for housekeeping rails

Housekeeping rails for USB-PD controllers, microcontrollers, interfaces and references are usually generated by a mix of compact buck converters and low-noise LDOs. These rails often start from the main 12 V or 19 V output or from an intermediate 5 V bias rail. Choices range from simple linear regulators supplying tens of milliamps to synchronous mini bucks that can efficiently feed higher-current 3.3 V or 5 V rails.

Selection parameters include input-voltage range, output current rating, dropout voltage, noise and PSRR, PG pin availability and basic protection features. Low-noise regulators in the TLV7xx and TPS7Axx classes and compact bucks in the TPS6217x, TPS62xxx or MP23xx series are typical building blocks for 3.3 V and 1.8 V housekeeping rails in adapter designs.

Supervisors and reset ICs

Voltage supervisors and reset generators observe one or more small rails and generate clean reset and PG signals for digital loads. They define when microcontrollers, USB-PD controllers and logic devices are allowed to start, and when they must be reset after dips or brownouts. This avoids inconsistent states caused by rails hovering near threshold levels during transients.

Key attributes include the number of monitored rails, threshold accuracy, configurable delay and reset width and output stage type. Simple single-rail supervisors can be drawn from TLV803/TLV810 or MCP100/MCP101 classes. Multi-rail and window supervisors such as those in the TPS386000 class support more complex sequencing where 3.3 V, 5 V and core rails must all be valid before system logic runs.

Temperature sensors and fan drivers

Higher-power and high-density adapters often rely on local temperature monitoring and small fans or pumps to maintain acceptable surface and component temperatures. Temperature sensors in the TMP100/TMP102 class provide I²C-accessible temperature readings that can feed derating logic in a secondary controller or system MCU. Fan and pump drivers in TC64x or LV880x classes convert this temperature information into PWM or multi-level speed control.

By treating synchronous rectifier controllers, integrated secondary controllers, housekeeping regulators, supervisors and thermal devices as distinct IC roles, adapter designers can choose parts that match power level, efficiency and observability requirements without relying on ad-hoc combinations that are difficult to scale across product families.

Design checklist & BOM hooks for adapter secondary power

A structured checklist helps ensure that the secondary side of an adapter matches the intended power level, efficiency target, start-up behavior and fault performance. Working through the items below turns abstract requirements such as “low standby power” or “support USB-C PD negotiation” into concrete parameters for synchronous rectifiers, secondary controllers, housekeeping regulators and supervisors. This also reveals when a legacy primary-only flyback architecture with a simple optocoupler can no longer cover the full specification.

Secondary power design checklist

• Output voltage and power range: confirm whether the adapter targets a 5–30 W wall-wart, a 45–100 W notebook supply or a higher-power gaming or workstation brick. Match SR controller voltage and current range, dv/dt tolerance and thermal margins to this level.
• Standby and light-load power targets: define no-load and light-load input power limits. Derive allowable quiescent currents for SR and secondary controllers and check for eco-mode or burst-mode compatibility on the secondary side so that standby targets can be met without sacrificing stability.
• Number and type of small rails: list required housekeeping rails (for example 5 V, 3.3 V, 1.8 V) and their current levels. Decide whether a single LDO is sufficient, or whether a combination of mini bucks and low-noise LDOs or a multi-output secondary controller is needed.
• PG and sequencing requirements: identify downstream USB-PD controllers, microcontrollers, logic ICs and interface transceivers. Determine their power-up order and minimum PG delays, then choose LDOs, bucks and supervisors with suitable PG pins and reset timing to coordinate the sequence.
• Protection behavior on the secondary side: specify desired responses to output short circuits, large capacitive loads, cable hot-plug and housekeeping rail faults. Decide which faults should trigger hiccup-style retries and which ones should latch off until input power is cycled or a control signal is toggled.
• Thermal margins and derating: consider expected ambient conditions, enclosure size and component placement. Decide whether local temperature sensing and fan or pump control is required, and whether the secondary controller or system MCU should implement temperature-based current derating.
• Isolation and creepage constraints: confirm the required insulation class and creepage distances for the target market. Verify that secondary devices, transformers and layout can meet these requirements without compromising sense accuracy or the routing of feedback paths.
• Telemetry and debug needs: determine whether system-level firmware must observe voltages, currents, temperature and fault counters. If so, plan for secondary or front-end devices with PMBus or I²C telemetry instead of relying solely on analog PG and FAULT pins.

BOM hook: when to move beyond a simple primary flyback

Many low-cost adapters use a primary-side flyback controller with optocoupler feedback and a few discrete LDOs for housekeeping rails. This can be adequate for a single regulated output with limited sequencing constraints. Once the design requires multiple secondary rails, strict PG timing, robust short-circuit and thermal protection and support for USB-C PD or similar logic, this minimal architecture becomes fragile and difficult to extend across product families.

If the checklist reveals a need for multiple small rails, coordinated PG and sequencing, local protections and observability, the BOM should consider secondary controllers or integrated bias solutions that bring SR drive, regulation, housekeeping rails and PG logic into one device class. Parts that only provide a simple error amplifier and optocoupler drive no longer cover the full secondary specification and will limit future adapter variants built on the same platform.

FAQs: Adapter Secondary Power