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Battery Charger PMICs — Architectures, JEITA Profiles, USB-C/PD & Power-Path

Battery Charger PMICs — What Problems Do They Solve?

A charger PMIC coordinates adapter input, battery charging, and the system rail. It implements CC–CV with JEITA temperature rules, safety timers, power-path control (IN/BAT/SYS), and optional OTG boost for peripherals. Neighbor topics such as Fuel Gauge, eFuse/Hot-Swap, and PMBus PSM are covered on their own pages.

Quick sizing rule I_adapter ≳ 1.3 × I_CHG × (V_batt / (V_adapter × η))
Tune ICHG, termination current, CV setpoint, JEITA table, and timers per datasheet.
System overview showing adapter, charger PMIC, battery, system rail, eFuse and fuel gauge Adapter feeds Charger PMIC which manages Battery and System Rail via power-path; eFuse on input; Fuel Gauge senses battery; OTG to peripherals. ADAPTER 5–20 V USB-C/PD / BC1.2 eFuse / Ideal Diode CHARGER PMIC CC/CV • JEITA • Timers USB-C/PD Sink • Power-Path BATTERY (1S / nS) Fuel Gauge SYSTEM RAIL (SYS) MCU/SoC • Peripherals • OTG IN BAT SYS OTG (optional)
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Architectures & Topologies

Linear (LDO-style)

Simple, low noise, minimal externals; heat is the limiter: P_loss ≈ (V_IN − V_BAT) × I_CHG. Best for compact/low-power (≤1–2 A).

Switching (Buck / Buck-Boost / Charge-Pump)

High efficiency and current. Buck is most common; Buck-Boost covers adapter–battery cross-over; Charge-Pump suits medium power with good EMI/size trade-offs. Synchronous rectification improves light-load.

Single-Cell vs Multi-Cell

1S for handheld/wearables (often USB-C/PD). 2–6S for tools/robots/industrial; balancing is handled by the BMS (see sibling page). External FETs scale power and protections.

Linear vs Switching charger topologies for single-cell and multi-cell designs Left: Linear topology with pass element; Right: Switching charger with inductor; footer shows 1S vs multi-cell notes and sync rectification. Linear (LDO-style) Adapter Pass FET BAT Low noise • Few externals Heat limited: P ≈ (V_IN − V_BAT) × I_CHG Switching (Buck / Buck-Boost / CP) Adapter BAT High efficiency • Higher current Sync rectification improves light-load 1S: handheld/wearables (often USB-C/PD) 2–6S: tools/robots/industrial (balancing by BMS)

Selection flow: Power level → Topology (Linear / Switching) → Cell count (1S / nS) → Interface (USB-C/PD/BC1.2) → Protections & thermals.

Charge Profiles & Chemistry — CC/CV, JEITA, and Cell Types

A practical charger profile follows pre-charge → constant-current (CC) → constant-voltage (CV) → termination/trickle. JEITA temperature rules adapt ICHG and VCV across zones to keep the pack safe. Cell chemistry (Li-ion/LiPo/LFP) sets the CV setpoint and termination behavior; NiMH uses a different algorithm and is included as a compatibility note.

Quick planning rules
I_pre ≈ 0.1–0.2 × I_CHG (cell below VTH_pre, typically 2.8–3.0 V/1S)
I_term ≈ 0.05–0.1 × I_CHG (stop or trickle per chemistry)
t_charge ≈ 1.2 × (Capacity_Ah / I_CHG) (includes taper/overhead)

Li-ion / LiPo

High energy density. Typical VCV=4.2/4.35 V. Trickle/termination policy per cell vendor. Ensure safety timer and cable-drop margin.

LiFePO4 (LFP)

Flat plateau, robust at temperature. VCV=3.6/3.65 V. Use slightly higher Iterm to avoid “never-finish” near plateau.

NiMH (Supplement)

Not CC-CV; use ΔV/ΔT + timer. Keep as compatibility mode in mixed portfolios; primary focus is Li-based chemistries.

JEITA temperature zones with CC/CV adjustments Zones Tcold, Tlow, Tnorm, Thigh, Thot with example reductions of charge current and CV setpoint outside normal range. Temperature Charge current / CV setpoint Tcold Tlow Tnorm Thigh Thot CV nominal CV derated CV derated
Charging timeline: pre-charge, CC, CV, termination Time axis with regions for pre-charge, constant current, constant voltage, and termination/trickle. Time Pre-Charge CC CV Terminate / Trickle I_pre ≈ 0.1–0.2×I_CHG I_CHG + T_CC V_CV + Taper I_term ≈ 0.05–0.1×I_CHG
TI — 1S switching charger, JEITA, I²C control, OTG option, compact QFN.
ST — 1–2S CC/CV charger with NTC table, safety timers, power-path.
NXP — Portable 1S charger PMIC, BC1.2 detection, ship mode, I²C regs.
Renesas — Multi-cell controller with external FETs, sense/NTC inputs.
onsemi — High-efficiency 1S buck charger, thermal foldback, OTG.
Microchip — USB-powered 1S charger + power-path, configurable timers.
Melexis — System-sensing front-ends that complement charger control.
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USB-C/PD & BC1.2 Negotiation — Getting Real Power In

PD exposes voltage/current PDOs (SPR 5/9/15/20 V; EPR 28/36/48 V). A charger PMIC as Sink (or DRP) requests a suitable PDO or PPS window. BC1.2 and Type-C default current ads provide a baseline when PD is absent. Always validate cable limits (E-Marker for 5 A) and input foldback behavior under load steps.

Quick power check P_PD ≥ 1.25 × V_CV × I_CHG / η_path
Reserve margin for cable drop and EMI filtering. With PPS, step voltage/current to track thermal limits.
PD handshake: Source_Capabilities → Sink_Request → Accept → PS_RDY Timeline of key PD messages between source and sink with role notes. Time Source_Capabilities Sink_Request Accept PS_RDY Source → Sink Sink → Source Source Power ready
SPR/EPR PDO ladder and PPS region Bars showing 5/9/15/20 V SPR levels, extended EPR voltages, and a shaded area for PPS adjustable region. 5 V 9 V 15 V 20 V 28 V 36/48 V PPS adjustable window
  • Sniff PD logs: request matches PDO, and PS_RDY arrives before enabling CC.
  • Verify input foldback (IIN_LIMIT/FOLDBACK) and brown-in/out thresholds.
  • Swap cables (3 A vs 5 A E-Marker) and repeat thermal runs.
TI — 1S charger with integrated Type-C/PD sink & PPS options; I²C config.
ST — USB-C DRP front-end + charger PMIC path; BC1.2 fallback.
NXP — Type-C attach + sink policy helper, charger register map sync.
Renesas — PD/PPS controller for multi-rail chargers; telemetry hooks.
onsemi — Compact Type-C sink managers paired with 1S chargers.
Microchip — PD controller + charger reference designs; I²C/SPI control.
Melexis — Complementary sensing/interfaces for safe negotiation paths.
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Power-Path, OTG & System Rail — IN/BAT/SYS Priority & Switching

A charger PMIC arbitrates adapter (IN), battery (BAT), and the system rail (SYS). Typical priority is IN→SYS, then IN→BAT (charge). BAT→SYS is used on brown-in/out or in OTG mode. Robust paths block reverse current and respect soft-start on SYS to avoid brown-outs.

Quick sizing & timing
t_SS ≈ C_SYS × ΔV_SYS / I_LIMIT (estimate SYS soft-start)
P_OTG_avail ≈ η × V_BAT × I_DISCHARGE (upper bound for OTG peripherals)
ΔV_SYS ≈ I_step × ESR_SYS + I_step × (t_resp / C_SYS) (load step droop)

Power-Path Modes

Direct IN→SYS, controlled path with ideal-diode FETs, and parallel assist with BAT. Gate control limits inrush and enforces priorities.

SYS Rail Bring-Up

Order: IN_VALID → SYS_SOFTSTART → CHG_EN → (optional) OTG_EN. Capture IN/SYS/BAT/EN pins on a scope to confirm sequencing.

Reverse Blocking & Brown Events

Detect/stop reverse current on IN and SYS. Verify brown-in/out thresholds and foldback behavior (IIN_LIMIT/FOLDBACK).

IN/BAT/SYS power-path with ideal diode FETs, OTG boost, and SHIP isolation Adapter feeds SYS and charger; BAT ideal-diode to SYS; OTG boosts SYS for peripherals; SHIP mode opens FETs to minimize leakage. ADAPTER (IN) USB-C/PD / BC1.2 eFuse / Ideal Diode SYSTEM RAIL (SYS) MCU/SoC • Loads • Peripherals CHARGER PMIC Path ctrl • CC/CV • JEITA BATTERY (PACK) Ideal-Diode to SYS OTG Boost (BAT→SYS) SHIP SYS_SOFTSTART IN→PMIC OTG
SYS bring-up sequence: IN_VALID → SYS_SOFTSTART → CHG_EN → OTG_EN Stacked timing bars for key enables with markers for measurement points. Time IN_VALID SYS_SOFTSTART CHG_EN OTG_EN (optional) Probe: IN Probe: SYS Probe: BAT Probe: OTG
TI — Charger with ideal-diode path, SYS soft-start, OTG, SHIP mode.
ST — Power-path control, programmable IIN limit, OTG boost, alarms.
NXP — 1S PMIC with SYS prioritization and brown-in/out handling.
Renesas — Multi-cell controller + external FETs for high-power paths.
onsemi — High-efficiency 1S path with reverse blocking and OTG.
Microchip — USB-powered charger with path control and SHIP function.
Melexis — Complementary sensing to supervise path currents/temps.

Protections & Compliance — Electrical, Thermal, and Timers

Safety depends on a stacked strategy: electrical limits (OVP/UVP/OCP/short-circuit), thermal control (OTP/thermal foldback), and time windows (pre-charge/fast-charge/overall timers, watchdog). Couple these with JEITA zones and clear fault→action policies (retry/derate/shutdown/latch).

Thermal & loss quick checks
T_j ≈ T_amb + P_loss × θ_JA (predict junction temp)
P_loss_linear ≈ (V_IN − V_BAT) × I_CHG (linear path worst-case)
P_loss_switch ≈ P_FET + P_ind + P_switch (switching budget)

Electrical Limits

IN/BAT/SYS OVP/UVP with hysteresis, input OCP & foldback, short-circuit response, reverse-polarity & reverse-current block.

Thermal Strategy

OTP + thermal foldback: reduce ICHG and/or VCV, or suspend charging. Validate heatspread and vias under pad.

Timers & Watchdog

Pre-charge/fast-charge/overall safety timers, watchdog keep-alive. Define fault recovery: retry, cooldown, or latch-off.

Fault → Log → Policy (Retry/Derate/Shutdown/Latch) → Action Flow from fault detection to logging and policy-driven action. Fault Detect Log Policy: Retry / Derate / Shutdown / Latch Action OVP/UVP/OCP/Short NTC Hot/Cold (JEITA) Safety Timer Expired Thermal Foldback Define deglitch times & back-off strategy. Expose status via IRQ pin / I²C registers for logging.
Thermal foldback: charge current vs temperature Charge current derates as temperature increases; OTP threshold halts charging. Temperature Charge current OTP halt
  • Verify OVP/UVP thresholds (IN/BAT/SYS) with hysteresis; inject shorts & foldback.
  • Thermal runs: log Tamb, I/V, throttling events; confirm OTP shutdown.
  • Safety timers: pre-charge, fast-charge, overall; watchdog keep-alive & recovery.
  • EMC pre-scan (conducted/radiated), ESD (contact/air); product-level certification per region.
TI — Full protection set with IRQ/log registers and timer controls.
ST — JEITA tables, OTP with programmable derate, watchdog support.
NXP — Integrated OVP/UVP/OCP matrix and fault pin aggregation.
Renesas — Multi-cell safety timers and configurable fault policies.
onsemi — Thermal foldback profiles with path-aware limiting.
Microchip — Flexible timer/watchdog scheme and IRQ reporting.
Melexis — Sensing front-ends complementing protection coverage.
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Thermal & Layout — Heat Paths, Switching Loops, Kelvin Sense & EMI

A robust charger layout starts with clear heat paths, a tight SW loop, clean Kelvin sense, and well-placed NTC. Validate with LISN/near-field probes and keep GND planes continuous.

Quick thermal & loop checks
ΔT ≈ P_loss × θ_JA_eff (reduce by copper area + dense thermal vias)
Minimize HS-FET ↔ SW ↔ CIN loop (place CIN at pins; short return to GND)
Kelvin sense: star ground (keep sense away from SW node / high dv/dt)

Heat Path & Vias

Large copper under power FETs/IC pad; dense via array to inner planes; avoid long necks to the plane; keep mask-less via field for better conduction.

Switching Loop

Shrink HS-FET–SW–CIN loop; optional RC snubber on SW; route SW away from sensors/NTC; solid inner GND plane as return shield.

Kelvin Sense & NTC

BAT/SYS sense pairs as Kelvin connections; star to analog ground; NTC close to the cell hotspot, avoid self-heating and SW coupling.

Thermal vias and copper spreading from charger IC to planes Top copper under IC with via array to inner planes; wide copper necks; ground plane heat spreading. Charger IC / Power FETs Large copper pour to inner planes Avoid narrow necks; connect to wide plane
Minimized switching loop with CIN placement and RC snubber High-side FET to SW node loop minimized; input capacitor tight; optional RC snubber on SW. HS FET SW LS FET/Diode CIN close to HS RC Snubber
Kelvin sense routing and NTC placement near the cell Kelvin sense lines kept away from SW; NTC close to battery hotspot with short leads. Battery Cell BAT_SENSE+ BAT_SENSE− NTC near hotspot Avoid SW coupling near sense
  • Dense thermal via field under hot parts; mask-less if allowed.
  • Shortest HS-FET–SW–CIN loop; solid return to GND plane.
  • Kelvin sense routed as a pair; star ground; isolate from SW.
  • NTC close to cell; verify β table; avoid self-heating.
  • EMI: input π/LC near connector; common-mode choke for long USB cables.

Sizing Rules & Quick Math — Adapter, Current, Time, Loss & JEITA

Start with adapter power, back-solve charge current to meet timeline and thermal limits, then pin down JEITA/NTC parameters. The quick math below is copy-and-paste friendly for early sizing.

One-liners
P_PD_min ≈ 1.25 × V_CV × I_CHG / η_path
t_charge ≈ 1.2 × (Capacity_Ah / I_CHG)
I_ADP_est ≈ I_CHG × (V_BAT / (V_ADP × η)) × 1.3

Adapter Sizing

Budget power with margin for cable loss and efficiency. Prefer PPS to trim voltage/current for thermal headroom.

Charge Current & Time

Pick ICHG from thermal/adapter limits; estimate total time with taper factor α=1.1–1.3; ensure Iterm is appropriate.

Loss & Thermal

Linear worst-case loss (V_IN−V_BAT)×I_CHG; switching loss split across FET/inductor/switching; keep Tj < limit − margin.

Adapter power sizing flow: budget → margin → cable/efficiency corrections Choose PD power level with safety margin and corrections for cable resistance and efficiency. Target V_CV & I_CHG η_path estimate P_PD_min with 1.25× Cable drop Pick PDO/PPS accordingly
Charge time vs charge current for different taper factors Inverse relationship between I_CHG and t_charge with α=1.1–1.3. I_CHG t_charge α=1.3 α=1.2 α=1.1
Loss comparison and thermal rise Linear loss grows with VIN−VBAT; switching loss is distributed; temperature rise estimated from total loss and θ_JA. Condition Loss / ΔT Linear Switching ΔT (θ_JA)
JEITA zones and NTC parameters quick card Table-style card listing Tcold/Tlow/Tnorm/Thigh/Thot and typical I/V adjustments with NTC beta and divider info. JEITA & NTC Quick Card Tcold/Tlow/Tnorm/Thigh/Thot → adjust I_CHG and/or V_CV; suspend at Tcold/Thot. NTC: β value, divider resistors, tolerance; calibrate at 25°C and hot/cold points.
Quick 3-in → 3-out (copy these formulas)
Inputs: Capacity_Ah, I_CHG, V_CV, η_path
Outputs: t_charge = 1.2 × Capacity_Ah / I_CHG, I_ADP_est = I_CHG × (V_BAT/(V_ADP×η)) × 1.3, P_PD_min = 1.25 × V_CV × I_CHG / η_path
TI — PPS/JEITA tables, I²C tuning; thermal throttling hooks.
ST — Charger + power-path with PPS options; layout notes in EVB guides.
NXP — USB-C sink + charger controls; sense/NTC integrations.
Renesas — Multi-cell controllers, external FET sizing app notes.
onsemi — High-efficiency 1S with EMI-oriented layouts.
Microchip — USB-powered chargers, PPS/JEITA examples.
Melexis — Sensing/front-ends complementing charger telemetry.
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Bring-Up & Troubleshooting — Steps, Probe Points, Remedies

Follow this bring-up path: wiring checks → adapter attach → SYS soft-start → enable charging → verify CC→CV→termination. Capture PD logs if present, and scope IN/SYS/BAT/SW/NTC.

Quick sanity math
t_SS ≈ C_SYS × ΔV_SYS / I_LIMIT (SYS soft-start time)
t_charge ≈ 1.2 × Capacity_Ah / I_CHG (with taper)
I_ADP_est ≈ I_CHG × (V_BAT/(V_ADP×η)) × 1.3 (adapter current estimate)
  1. Pre-power checks: polarity, shorts, eFuse orientation, NTC wiring, SYS bulk cap ESR.
  2. Attach adapter: verify 5 V then PD/BC1.2; confirm IIN_LIMIT and brown-in.
  3. SYS sequence: IN_VALID → SYS_SOFTSTART → CHG_EN → (optional) OTG_EN.
  4. Charge path: Pre-charge → CC → CV → Termination; log thresholds and times.
  5. Don’ts: no long thermal runs without monitoring; set safety timers before EVT/DVT.
Bring-up probe points on charger board Probe IN, SYS, BAT, SW, NTC and IRQ/STAT pins with expected measurement windows. CHARGER PMIC IN SYS BAT SW NTC IRQ/STAT Expect: IN steady; SYS ramps; BAT rises CC→CV; SW switching; NTC within JEITA; IRQ flags faults.
Charging events timeline: pre-charge, CC, CV, termination Time segments with annotations for current and voltage behavior. Time Pre-Charge CC CV Terminate I_pre ≈ 0.1–0.2×I_CHG I_CHG + T_CC V_CV + taper I_term
PD handshake compact: Source_Cap → Request → Accept → PS_RDY Key messages exchanged when negotiating power delivery. Source_Capabilities Sink_Request Accept PS_RDY

Troubleshooting — Symptoms → Causes → Actions

Symptom Likely Cause Action
Not reaching 100% I_TERM too high; cable drop; NTC mis-zoned Lower I_TERM; better cable/PDO; calibrate NTC/JEITA
Early CV transition Adapter limiting; input foldback; trace resistance Increase PDO/IIN_LIMIT; thicken path; reduce drop
Thermal current throttling High θ_JA; copper/vias insufficient Add copper/vias; improve airflow; use PPS lower V
OTG disconnects Limit too low; cable lacks 5 A E-Marker Raise limit; use 5 A cable; cap load inrush
Ripple / pulse jitter Loop compensation; sense coupling Snubber; better Kelvin; ground shielding

Bring-Up Record Template

Project/Board: _______   Ambient (°C): _______   Airflow: _______

Adapter: PDO/PPS _______   Cable: Model/Length _______

Key Params: I_CHG _____, I_TERM _____, V_CV _____, IIN_LIMIT _____, JEITA table rev _____

Waveforms: IN / SYS / BAT / SW / PD logs   |   Notes: Risks & Actions → Owner / Due

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Chip Shortlist — 7 Brands at a Glance

Below are concise charger PMIC picks per brand (series-level), highlighting cell count, power/path features, interface, and package. For pin-to-pin or cross-brand replacements, ask us—we provide register maps and thermal/loop validation support.

≤10 W 10–45 W 45–100 W+ I²C PD-ready/PPS

TI — 1S Switching + Path

1S, 2–5 A; power-path, OTG, JEITA; I²C; some variants with USB-C/PD sink; QFN/WLCSP.

ST — 1–2S Compact

NTC table, timers, OTG; up to mid-power; I²C/GPIO; QFN.

NXP — Portable 1S

BC1.2/Type-C front-end friendly, ship mode, low I_Q; I²C; WLCSP/QFN.

Renesas — Multi-Cell Ctrl

2–6S controller + external FETs; telemetry; I²C/PMBus; QFN/TQFP.

onsemi — Efficient 1S

Buck charger, thermal foldback, OTG; good EMI; GPIO/I²C; QFN.

Microchip — USB-Powered

1S charger + path; flexible timers; I²C/SPI; QFN; BC1.2/Type-C friendly.

Melexis — Sensing Front-Ends

Complements chargers with accurate NTC/current sense; improves protection telemetry; small packages.

Charger PMIC shortlist across TI, ST, NXP, Renesas, onsemi, Microchip, Melexis Seven compact cards listing brand, cells/power, path features, interface, and package. TI 1S, 2–5 A • Path/OTG • I²C • QFN/WLCSP ST 1–2S • NTC/Timers/OTG • I²C/GPIO • QFN NXP 1S portable • BC1.2/Type-C • I²C • WLCSP Renesas 2–6S ctrl + FETs • I²C/PMBus • QFN/TQFP onsemi 1S buck • foldback/OTG • I²C • QFN Microchip USB-powered 1S • I²C/SPI • QFN Melexis Sensing/front-ends • NTC/Current • small pkgs
Pin-to-Pin / Cross-Brand Replacement — We can propose drop-in options, provide register mapping, and validate thermal/loop stability on your board.
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Frequently Asked Questions — Charger PMICs

Practical answers for bring-up, USB-C/PD negotiation, power-path/OTG, JEITA/thermal, and sizing rules. See also USB-C/PD, Power-Path, Thermal & Layout, and Sizing Rules.

1) Why does charging enter CV “too early”? Cable drop vs. adapter current limit?
Watch IN voltage and input-limit/foldback flags. Linear IN droop with current suggests cable/trace drop; a flat IN with clamped current points to adapter limit. Quick check: switch to higher PDO or a low-resistance cable. Estimator: I_ADP ≈ I_CHG × (V_BAT/(V_ADP×η)) × 1.3. See #usbc.
2) How should I set termination current (I_TERM)? Will it affect “100%” readout?
Typical range is 0.05–0.1 × I_CHG. Too high → stops early (capacity left); too low → long taper and heat. SOC gauges may still show ~100% with different I_TERM; rely on runtime tests as well.
3) What pre-charge threshold (V_TH_pre) and current (I_pre) should I use?
Common single-cell thresholds are 2.8–3.0 V with I_pre ≈ 0.1–0.2 × I_CHG. Keep a safety timer; do not stay in pre-charge for long without monitoring.
4) Which PDO should a Sink request — 9/15/20 V? When is PPS better?
Choose the lowest voltage that still meets P_PD ≥ 1.25 × V_CV × I_CHG / η_path. PPS is ideal for thermal tuning: reduce voltage as current drops to minimize loss and inductor ripple. See #usbc.
5) How do Type-C 3 A vs. 5 A cables (E-Marker) cap my maximum charge current?
Without an E-Marker the source advertises ≤3 A; with E-Marker it may allow 5 A. Adapter and cable ratings together bound your requested PDO/PPS and IIN_LIMIT.
6) Recommended priority across IN/BAT/SYS? Any brown-in/out tips?
Typical: supply SYS from IN first, then charge BAT; fall back BAT→SYS on brown-out or OTG. Verify thresholds and reverse-current blocking; log foldback behavior (IIN_LIMIT).
7) OTG boost keeps dropping — what are the usual causes?
Under-set current limit, cable not 5 A capable, or load inrush. Fix: raise limit within thermal budget, use 5 A E-Marked cable, and add soft-start on the peripheral.
8) How do JEITA zones map to I_CHG and V_CV adjustments?
In T_norm use nominal I/V. In T_low/T_high reduce I_CHG and sometimes V_CV; at T_cold/T_hot suspend. Keep NTC placement tight to the cell and align tables with firmware/registers.
9) Thermal foldback vs. OTP — what’s the difference on the scope?
Foldback smoothly reduces I_CHG (sometimes V_CV) as temperature rises; OTP is a hard shutdown at a threshold. Quick model: T_j ≈ T_amb + P_loss × θ_JA.
10) My ripple looks “jittery”. Could the SW loop or sensing be the culprit?
Likely yes. Shrink the HS-FET–SW–CIN loop, add an RC snubber, and route Kelvin sense pairs away from SW with a solid ground reference.
11) Where should the NTC go? Do I need calibration?
Place near the cell hotspot with short leads and minimal self-heating. Calibrate at 25 °C plus hot/cold reference points; align β and divider values with the PMIC/MCU tables.
12) Linear vs. switching charger — how do time and heat trade off?
Linear is simple/quiet but worst-case loss is (V_IN − V_BAT) × I_CHG; switching is efficient but needs layout care. For ≥1–2 A, switching is usually preferred thermally.
13) How do I estimate adapter power and input current quickly?
Use P_PD_min ≈ 1.25 × V_CV × I_CHG / η_path and I_ADP_est ≈ I_CHG × (V_BAT/(V_ADP×η)) × 1.3. Add margin for cable drop and EMI filtering.
14) Cross-brand pin-to-pin replacement — what must I verify?
Check pin map, power-path topology, JEITA tables, IIN_LIMIT foldback rules, OTG limits, IRQ polarity, and default timers. We can provide register-map deltas and validation. See #ics.
15) A full charge stops at ~95–98%. Is it a fault?
Not necessarily. With tight I_TERM and realistic voltage accuracy, some cells plateau below “textbook” capacity. Validate runtime and pack temperature rather than SOC alone.

Downloads & RFQ

Fixed-name resources (each ≤30 KB) plus fast RFQ. Replace the URLs with your actual file paths if needed.

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charger-sizing-worksheet.xlsx

Quick current/time & adapter power estimator (≤30 KB).

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jeita-curve-cheatsheet.pdf

JEITA zones and I/V adjustments (≤30 KB).

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power-path-reference.pdf

IN/BAT/SYS path, OTG & ship reference (≤30 KB).

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charger-bringup-checklist.pdf

Bring-up steps, probe points & logs (≤30 KB).

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charger-layout-emi-notes.pdf

Layout & EMI quick notes (≤30 KB).

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