CSI-2 D-PHY / C-PHY (Rx/Tx) for Camera & Vision Systems
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This page focuses strictly on CSI-2 over D-PHY / C-PHY (Rx/Tx) for camera/vision links: HS/LP behavior, lane aggregation, timing calibration/deskew, and board-level bring-up criteria.
Positioning & Quick Map (What to read next)
Establish a strict scope boundary and route readers to the correct page within the MIPI subtree, so content does not overlap across sibling pages.
- CSI-2 links on D-PHY / C-PHY: HS/LP modes, lane aggregation, timing calibration/deskew.
- Board-level SI/layout checkpoints that directly affect link stability and sampling margin.
- Bring-up validation and production-friendly pass criteria (error counters, correlation checks).
- Bridges / Extenders: long-reach coax/twisted-pair SerDes (FPD-Link/GMSL) — use the Extenders page.
- Switch / Mux: multi-camera routing/switching topologies — use the Switch/Mux page.
- Port Protection (ESD/TVS): ultra-low-C arrays and protection placement library — use the Port Protection page.
Use these one-line rules to avoid debugging in the wrong layer. Each rule points to the first page that should own the problem.
- LP works but HS is unstable → This page → settle/deskew/margin.
- Works on short FFC, fails on long coax/twisted pair → Extenders → channel model changed.
- Fails only when switching cameras → Switch / Mux → routing/settle mismatch.
- After ESD testing, link becomes fragile → Port Protection → parasitics/symmetry.
- Only one lane shows errors → This page → asymmetry/return-path.
- Temperature swing increases drops → This page → drift vs calibration strategy.
- Need lane count / throughput → see the bandwidth + lane aggregation section later.
- HS/LP transitions fail → see the HS/LP fundamentals + timing calibration section later.
- Layout / SI validation → see the PCB & interconnect rules section later.
- Bring-up and production gates → see the engineering checklist section later.
- Field triage → see the FAQ section later (fixed 4-line answers).
What is CSI-2 on D-PHY / C-PHY
CSI-2 defines how image data is packetized and transported (streams, packet types, line/frame structure). D-PHY / C-PHY defines how those packets move electrically over lanes (HS/LP behavior, lane timing, sampling margin). Tx/Rx identifies which side drives transitions and which side must sample within a stable window.
- Lanes: determine peak throughput and deskew sensitivity (lane-to-lane alignment).
- Line/Frame: determines burstiness and receiver FIFO stress (drops can occur even with “average bandwidth” headroom).
- VC (Virtual Channel): splits multiple streams on one link (used for bandwidth partition, not for PHY stability).
- Data Type: identifies payload format (used to validate stream expectations and debug mismatches).
Selection and budgeting should focus on wire count, effective payload throughput, and timing calibration sensitivity—not on memorizing spec tables.
- Clear HS/LP states; HS entry/settle margin is a primary stability gate.
- Lane aggregation increases throughput but tightens deskew and symmetry requirements.
- Layout errors often show up as HS payload CRC/ECC spikes or intermittent link flaps.
- Uses trios; effective throughput budgeting uses a different “payload per symbol” view.
- Symmetry across the trio strongly impacts margin; coupling imbalance can look like random drops.
- Bring-up should validate stability across temperature and supply corners to expose drift.
- Bandwidth + lane count becomes a deterministic worksheet: resolution/fps/bpp + overhead → lane rate target.
- HS/LP stability becomes an observable margin problem: entry/settle/deskew windows and their drift.
- Bring-up failures become layer-local: packet/stream mismatches vs sampling/physical margin.
System Architecture (Sensor–ISP/SoC/FPGA) & Topologies
Establish a system-level topology contract for CSI-2 links (direct connect, short interconnect, or via FPGA), and define the interface gates that determine whether the link can come up reliably.
- Direct connect is the baseline when the interconnect is short and stable (board-level or short FFC) and the receiver has sufficient margin.
- Short interconnect changes the physical reference (connector/FFC) and often shifts skew/return-path risk; validation must include temperature + assembly conditions.
- Via FPGA is chosen when preprocessing/aggregation is required; the CSI-2 link must still pass the same bring-up gates (clock/reset/I²C) before any higher-layer logic helps.
- Escalation triggers: if distance/medium changes beyond board/short FFC, route to the Extenders page (out of scope here).
- Default when: board-level link, stable reference ground, short return path.
- Primary risk: HS entry/settle margin and lane-to-lane skew sensitivity as rate increases.
- First bring-up gate: LP idle stable → HS entry success → payload stability.
- Observability: link-up state, CRC/ECC counters, frame drop correlation.
- Escalation: if instability appears only with longer medium, route to Extenders (out of scope).
- Default when: camera module is separable; interconnect remains short.
- Primary risk: impedance discontinuity, return-path detours, and symmetry loss at the connector/FFC.
- First bring-up gate: verify LP stability under touch/assembly variation → verify HS settle margin.
- Observability: lane-specific error bias; failures that appear after enclosure assembly.
- Escalation: if distance or medium becomes long/coax, route to Extenders (out of scope).
- Default when: preprocessing, aggregation, or capture timing control is needed.
- Primary risk: two CSI-2 interfaces must both pass timing/deskew gates; failure on either side can mimic “system instability”.
- First bring-up gate: validate Sensor→FPGA link independently before enabling FPGA→SoC link.
- Observability: isolate failures by segment; compare counters at each receiver boundary.
- Escalation: bridge/extender implementation details belong to sibling pages (out of scope here).
- Goal: ensure the PHY is not forced into undefined states before configuration begins.
- Quick check: stable rails, valid reference clock, reset release ordering consistent with the device requirements.
- First suspicion if failing: clock not stable at reset release, brownout during HS entry, or rail coupling into the PHY.
- Goal: align both ends on lane mode, stream expectations, and state transitions.
- Quick check: address + speed sanity, correct mode (D-PHY/C-PHY), lane count, and stream enable sequence.
- First suspicion if failing: configuration mismatch between sensor and receiver, or a stale register image applied after reset.
- Goal: localize failure to entry, settle, payload, or exit.
- Quick check: confirm LP idle, then confirm HS entry, then confirm payload stability at reduced rate/lane count.
- First suspicion if failing: settle margin or skew; if only after assembly/temperature, suspect reference/return-path changes.
The diagrams below keep focus on CSI-2 link ownership and bring-up gates. Long-reach transport and protection libraries are intentionally routed to sibling pages.
D-PHY Fundamentals (HS/LP States & Electrical Intuition)
Build a practical HS/LP state model for D-PHY that supports bring-up decisions: where transitions are sensitive, what physical margin is consumed, and how failures map to the first suspicion point.
- LP-11 (Idle): stable baseline; control-plane changes should not disturb idle stability.
- LP-01 / LP-00 (Preparation): transitions toward HS; sensitivity increases to reference shifts and asymmetry.
- HS entry: the link moves from slow-level behavior to sampling-window behavior; small discontinuities start to matter.
- HS settle: the receiver’s critical window; consumed margin here often decides whether payload can start cleanly.
- HS payload: sustained sampling; SI/crosstalk/noise coupling shows as CRC/ECC spikes and lane-biased errors.
- HS exit → LP recovery: the link returns to LP; marginal timing can cause intermittent “exit failures” even when payload is stable.
- LP behavior is dominated by level detection and slow transitions; it is sensitive to reference shifts, weak pull bias, leakage, and ground changes.
- HS behavior is dominated by sampling window and edge integrity; it is sensitive to impedance discontinuity, return-path detours, crosstalk, and noise-coupled jitter.
- Practical consequence: LP may appear “fine” while HS fails, because HS consumes margin in settle and sampling where LP never measures.
- LP stable, HS fails at entry → suspect settle margin, skew, or a discontinuity near the receiver.
- HS enters, payload CRC/ECC spikes → suspect crosstalk, return-path break, or supply noise coupling into sampling jitter.
- Payload stable, exit fails intermittently → suspect exit/recovery timing, weak-bias integrity, or marginal reference stability.
- Only one lane shows errors → suspect lane asymmetry, connector pin issues, or layer transition causing return-path imbalance.
- Fails only after assembly/touch → suspect reference/ground path change at connector/FFC and mechanical intermittency.
- Fails only at hot/cold corners → suspect drift + insufficient calibration strategy; validate settle margin across corners.
- Confirm LP-11 idle stability at rest (no flaps, no lane-bias anomalies).
- Attempt HS entry with reduced stress: fewer lanes and/or reduced rate where possible.
- Verify HS settle success before trusting payload stability; treat settle failures as margin failures.
- Run a short payload window and check for lane-biased errors and burst-correlated spikes.
- Validate HS exit → LP recovery stability; intermittent exit issues are often timing/reference related.
Next hook: once the failure is localized to entry/settle/payload/exit, quantify timing margin and deskew calibration in the timing section later in this page.
The timeline highlights the most sensitive windows (entry/settle and exit/recovery). Many “LP OK, HS fails” cases are margin losses concentrated in these windows.
C-PHY Fundamentals (Trio Signaling & Symbols)
Build a usable mental model for C-PHY: trio as the wiring unit, symbols as the PHY rate unit, and payload throughput as the budgeting unit. The goal is reliable estimation and faster localization when BER/margin issues appear.
- D-PHY lane is pair-based: the main stability intuition is sampling margin (entry/settle) and differential continuity.
- C-PHY trio is 3-wire based: the main stability intuition is trio symmetry and balanced coupling within the trio.
- Practical consequence: C-PHY can reduce wire count for a target payload, but it becomes more sensitive to trio imbalance (length/spacing/reference changes).
- Rsym: symbol rate per trio (symbols/s).
- Ephy: effective bits per symbol (bits/symbol), platform- and mode-dependent.
- ηpkt: packet/framing efficiency factor (0–1), driven by blanking + headers + embedded data.
Ephy is a PHY encoding efficiency term (from platform/device documentation). ηpkt is a CSI-2 framing term (expanded in the throughput budgeting section).
- Only fails at higher symbol rate → trio symmetry/coupling imbalance → compare trio length/spacing and reference continuity across all three wires.
- Trio-specific error bias → one trio differs mechanically/electrically → swap mapping (if possible) and see whether the error follows the trio.
- Payload errors but control-plane looks clean → margin loss concentrated in HS sampling → reduce symbol rate and re-check counter slope.
- Works cold, fails hot → drift + insufficient calibration margin → compare error-rate growth vs temperature corners.
- Intermittent failures after assembly → connector/FFC reference shift → correlate failures with enclosure state or flex movement.
Next hook: trio imbalance and coupling mechanisms are quantified in the SI/layout section later in this page.
The diagram keeps focus on the budgeting chain: trio wiring unit → symbol unit → payload unit, plus the stability knobs that dominate margin in practice.
Lane Aggregation & Throughput Budgeting (Camera/Vision)
- Total payload requirement from resolution × fps × bpp (active image only).
- Total on-wire requirement after accounting for blanking + packet/framing + metadata.
- Lane/trio count and target per-lane/per-trio rate with headroom margin.
- Burst & FIFO sanity so “average bandwidth looks fine” does not hide peak-rate drops.
Payload_bps = Res_active × FPS × bpp
- Res_active: active pixels per frame (exclude blanking in this step).
- bpp: bits per pixel for the transported format (raw/YUV/etc.).
- This step defines the minimum data requirement before any transport overhead is added.
- Blanking / timing gaps: line/frame gaps reduce duty cycle and raise peak/average ratio.
- Packet overhead: headers and integrity fields consume on-wire capacity beyond payload.
- Line/frame structure: structural packets create burstiness even when average payload is fixed.
- Embedded data / metadata: extra streams or sideband payload reduce effective image throughput.
Total_on_wire_bps = Payload_bps × M_overhead
M_overhead is a project margin term that aggregates blanking + packet/framing + metadata effects. Keep it traceable by listing which items dominate.
Per_lane_rate_target ≈ Total_on_wire_bps / (N_lanes × η_phy_d)
η_phy_d represents PHY transport efficiency on the target platform. Use a conservative headroom if exact efficiency terms are not yet fixed.
Per_trio_symbol_target ≈ Total_on_wire_bps / (N_trios × E_phy × η_phy_c)
E_phy is the effective bits per symbol term; η_phy_c is a platform efficiency term. This keeps the budgeting chain consistent: symbol → payload.
- Platform first: match the receiver’s supported lane/trio counts and rate ladders.
- Routing constraint: if pin/trace count is tight, C-PHY can reduce wires, but trio symmetry becomes a primary margin knob.
- Margin management: more lanes reduce per-lane rate but increase deskew sensitivity; more trios reduce per-trio stress but increase layout symmetry burden.
- Why burst exists: line/frame structure and blanking compress payload into active windows, raising peak rate.
- Burst factor: B = Peak_rate / Avg_rate; small duty cycle implies higher B and higher FIFO stress.
- FIFO rule: ensure receiver buffering covers (Peak_rate − Service_rate) across worst-case service latency.
- Drops correlate with peak activity → suspect burst/FIFO before blaming raw link SI.
- Reducing FPS or bpp improves stability → confirms stress is throughput-related (budget or buffering).
Next hook: once target lane/trio rate is known, timing calibration and PCB return-path rules become the primary margin levers.
Use this flow to build a traceable worksheet: active payload → overhead → on-wire requirement → lane/trio mapping → rate targets + headroom.
Timing Calibration & Deskew (Bring-up Critical Path)
Define the calibration targets, triggers, observables, and pass criteria that keep CSI-2 stable across skew, drift, and operating corners. The goal is to prevent “looks fine on scope” from turning into sporadic frame errors in system run.
- Lane-to-lane / trio-to-trio skew: routing length differences, asymmetrical via stacks, connector pin-environment mismatch, and per-channel internal delay spread.
- PVT drift: temperature/voltage shifts move IO delay and sampling phase, slowly eating deskew headroom.
- Asymmetry & coupling imbalance: within a pair/trio, uneven geometry changes effective delay and stability (keep symmetry measurable and auditable).
- Mode/gear transitions: rate ladders, power-state changes, and retrain events can change effective internal latency and re-open timing risk.
Practical framing: deskew stability is a margin budget problem—skew + jitter + drift + discontinuity penalties must remain below the available sampling window.
- Entry/settle windows are the weakest point: during HS entry and settle, the effective margin is smallest, so skew and drift show up as intermittent failures.
- “Scope looks fine” can miss the failure mode: sporadic errors are often statistical—rare jitter + drift + deskew shortage can cross a boundary even if a single capture looks clean.
- Engineering model: Margin = Sampling_window − (Skew + Jitter + Drift + Discontinuity_penalty)
When margin becomes “occasionally negative,” CRC/ECC bursts, sync/SoT-class errors, and frame drops appear even if average throughput is within limits.
- Boot-time calibration: run once after power-up; best when the environment is stable and rate/power transitions are rare.
- Periodic calibration: re-run on a schedule; best for long runtimes with unavoidable thermal drift; requires a defined “calibration window” to avoid service disruption.
- Event-triggered calibration: re-run when risk rises; typical triggers include temperature crossing a threshold, voltage rail changes, link retrain events, or error-rate slope anomalies.
- Trigger: ΔT ≥ X °C or Vrail step ≥ Y mV, or retrain event.
- Action: re-calibrate deskew / sampling phase within Z ms.
- Acceptance: CRC/ECC increment ≤ N over W minutes; frame-drop rate ≤ P per hour; no sync/SoT-class errors during Y minutes of stress run.
- CRC/ECC spikes → suspect payload sampling margin / deskew headroom → reduce rate or reduce payload stress and observe slope change.
- Sync/SoT-class errors → suspect HS entry/settle window and reference integrity → check whether errors cluster at link-up or after retrain.
- Frame drop / short frame → suspect sustained error bursts or burst/FIFO stress → align drops with peak payload windows and buffering telemetry.
- Lane-biased errors → suspect one channel’s asymmetry or internal delay spread → swap mapping (if supported) to see if the error follows.
Next hook: once deskew margin is characterized, PCB return-path continuity and symmetry rules become the strongest deterministic controls.
Bars represent per-lane arrival offsets; the sampling window must cover the spread with headroom. Margin shrinkage explains sporadic errors.
PCB & Interconnect Design (SI/Layout Rules That Matter)
This section focuses on the rules that measurably protect timing margin: symmetry, return-path continuity, and controlled transitions. Each rule is paired with why it matters and a minimum pass gate.
- Must-do: keep lane/trio geometry auditable—length, via count, and reference behavior should be consistent within the group.
- Avoid over-chasing: forcing extreme serpentine can harm return-path continuity and increase discontinuity penalties.
- C-PHY note: trio symmetry (all three wires) dominates margin; imbalance shows up as trio-biased errors.
- Must-do: keep reference planes continuous; avoid crossing split planes/gaps; provide return stitching when transitioning layers.
- Why: broken return paths amplify common-mode noise and timing uncertainty, shrinking sampling margin.
- Must-do: minimize unnecessary layer swaps; keep via stacks symmetric across lanes/trios; avoid one-channel-only detours.
- Why: asymmetrical transitions create lane-biased delay, loss, and reflection differences that deskew must absorb.
- Insertion loss: how quickly the channel attenuates at the operating rate.
- Return loss: reflection sensitivity that can distort entry/settle and consume margin.
- Crosstalk (NEXT/FEXT): coupling that converts neighbor activity into timing noise.
- Pin-environment symmetry: some pins have different return/coupling conditions; treat mapping symmetry as part of the budget.
- Mechanical variation: assembly pressure and flex can shift spacing/reference and change error rate over time.
- Long stubs (test pads, T-branches): reflections and time spreading steal entry/settle margin.
- Crossing plane splits: broken return paths inject common-mode noise and increase timing uncertainty.
- Asymmetric “fixes”: adding a pad/component/test hook on only one lane/trio creates lane-biased behavior.
- Over-serpentine: length match that destroys return continuity often performs worse than a small, auditable length delta.
If protection components (ESD/filters/CMC) are needed, maintain symmetry and treat them as separate design gates (deep details belong to the port-protection section).
- In-group match: ΔL (within lane group / within trio) ≤ X (fill X from platform deskew range).
- Transition symmetry: via-stack count difference within the group ≤ N; avoid “one-lane-only” layer detours.
- Return continuity: no plane-split crossings; if unavoidable, provide defined return stitching (required condition list).
- Stub control: stub length ≤ X; test features must be symmetric and minimized.
- Mapping symmetry: connector/FFC pin mapping keeps return/coupling conditions consistent for all lanes/trios.
Left side shows a margin-friendly channel; right side shows typical failure patterns: plane gaps, asymmetry, and long stubs.
Clocking, Jitter, and Power Noise Coupling
Convert “link instability” caused by invisible jitter and power noise into actionable checks, correlation tests, and design gates—without expanding into a full system-clock tutorial.
- What it affects: sampling uncertainty, HS entry/settle tolerance, deskew headroom, and retrain robustness.
- Typical patterns: stable at low rate but fails at high rate; errors cluster after retrain; failures increase at hot corners.
- Engineering model: Sampling uncertainty = clock jitter + supply-induced jitter + threshold noise
Practical takeaway: when deskew margin is thin, jitter sources that look “minor” can become the dominant failure trigger.
- Supply ripple → delay / threshold movement: receiver decision thresholds and buffer delays shift with rail noise, appearing as timing uncertainty.
- Ground bounce / return disturbance → common-mode jitter: unstable return paths translate load current edges into sampling instability.
- Domain partitioning: keep PHY/IO rails isolated from large load-step aggressors where possible.
- Decoupling strategy: cover frequency bands and minimize loop areas; keep high-speed return paths short and continuous.
- Load-step awareness: treat workload transitions as first-class stress cases because they amplify ripple and ground bounce.
- Error counters: CRC/ECC + sync/SoT-class + frame drop/retrain events.
- Windowing: snapshot every X seconds; keep the same window across runs.
- Context: temperature, workload state (resolution/FPS/mode), rail status or ripple proxy, and retrain timestamps.
- Temperature monotonicity: error slope increases with temperature → drift + jitter margin is shrinking.
- Load-step correlation: errors spike on workload transitions → power coupling likely dominates.
- Rail correlation: errors align with ripple peaks / rail alerts → supply-induced jitter path is active.
- Rate / stress reduction: lower rate or reduce payload stress; if errors drop sharply, margin is the limiting factor.
- Controlled load steps: toggle workload states; if errors follow transitions, power coupling is confirmed.
- Temperature sweep: record the “stable region” and the failure threshold to define production gates.
- Stress: ΔLoad step ≥ X, temperature range [Tmin, Tmax], rate = target.
- Acceptance: CRC/ECC increment ≤ N per W minutes; no sync/SoT-class errors in Y minutes; frame-drop rate ≤ P per hour.
A compact causal graph linking clock/power/ground disturbances to PHY sampling uncertainty and observable error signatures.
Engineering Checklist (Design → Bring-up → Production)
The checklist is grouped by phase: Design gates define budgets and observability; Bring-up SOP finds the limiting factor quickly; Production gates standardize sampling, bins, and regression coverage.
- Build the throughput sheet: Res × FPS × bpp × overhead; select lane/trio count; set headroom target.
- Define calibration policy: boot / periodic / event-triggered; specify trigger thresholds (ΔT, Vstep, retrain).
- Lock observability: CRC/ECC + sync/SoT-class + frame drop + retrain events; define snapshot window X seconds.
- Freeze layout gates: ΔL ≤ X; via-stack delta ≤ N; no plane-gap crossings; stub ≤ X; mapping symmetry.
- Define noise stress gates: load-step scenario (ΔLoad ≥ X); temperature range [Tmin, Tmax]; correlation logging plan.
- Control-plane sanity: ensure configuration is deterministic (register set + timing order).
- LP-first check: validate LP behavior; treat LP pass as necessary but not sufficient for HS stability.
- HS step-up: start low rate → step to target; record error slope per step under the same window.
- Lane/trio incremental enable: enable one at a time; detect lane-biased errors early.
- Stress matrix: temperature sweep + controlled load steps + retrain events; track correlation evidence.
- Minimal interventions: reduce payload, reduce rate, or reshape load; verify whether errors follow the intervention.
- Target mode: target resolution/FPS/rate under nominal rails.
- Stability: CRC/ECC increment ≤ N per W minutes; zero sync/SoT-class errors in Y minutes; frame drop ≤ P per hour.
- Corner: repeat under [Tmin, Tmax] and ΔLoad ≥ X transitions.
- Sampling plan: define sample rate X% and stress coverage (temperature, voltage, load steps).
- Fail bins: Entry/Settle · Payload(CRC/ECC) · Lane-biased · Load-step correlated
- Regression set: mandatory cases (low/high rate, max payload, temp sweep, load-step, long-run).
- Limits & traceability: freeze thresholds (N/W/Y/P) and store logs/metadata for reproducibility.
Production intent: the same evidence loop used in bring-up becomes a standardized acceptance gate and a debug accelerant.
A single flow view of what must be defined, executed, and frozen across the lifecycle.
H2-11. Applications (Camera / Vision Use-Cases)
- Pick the closest use-case card (row) → identify the dominant stress variables (columns).
- Apply the recommended gates (budget headroom, calibration triggers, observability split).
- If the trigger says “Escalate”, route to the sibling page (Extenders / Switch-Mux) rather than expanding here.
- Frequent LP↔HS transitions, standby/wake stability, thermal hotspots.
- FPC/board stack constraints (return path discontinuity risk).
- Power noise coupling under burst load (frame start / lane enable).
- Define a wake-up gate: “no sync/SoT errors within X seconds after wake” (windowed counters).
- Event-triggered recalibration when temperature crosses ΔT (placeholder) or after repeated frame drops.
- Keep HS bursts away from known noisy rails; validate by correlating errors vs ripple windows.
- Wider temperature swing → skew drift and sampling margin erosion.
- Heavier EMI environment → common-mode injection and threshold jitter.
- Long duty cycles → intermittent errors must be observable and classifiable.
- Budget headroom conservatively; treat “passes at room temp” as insufficient without temp sweep.
- Split counters by lane/trio and by time window (X seconds) to catch lane-biased drift.
- Periodic calibration cadence (placeholder) plus event-trigger on ΔT and supply excursions.
- If interconnect length and EMI cannot meet the sampling margin gate → route to “Bridges / Extenders”.
- Simultaneous frame start → burst throughput spikes and FIFO stress.
- Lane-to-lane skew sensitivity increases when multiple streams align.
- Error impact is amplified (frame alignment breaks pipelines).
- Budget “instantaneous” throughput (burst) separately from average payload throughput.
- Require per-stream/per-lane observability: CRC/ECC, SoT/sync, frame drop counters.
- Bring-up sequence: LP stable → enable lanes progressively → then enable sync mode.
- Lane aggregation and rate headroom become first-order constraints.
- Thermal + power noise coupling worsens at sustained throughput.
- Calibration cadence may need to increase under drift.
- Require a numeric headroom gate: lane rate ≤ (MaxRate × X%) placeholder.
- Validate with load-step testing and temperature sweep, logging error counters per window.
- State transitions (LP/ULPS ↔ HS) can fail intermittently without obvious SI symptoms.
- Wake timing windows shrink under drift and supply transients.
- Define a “wake acceptance” pass gate: X wake cycles, Y seconds window, zero sync/SoT errors.
- Use event-triggered recalibration after repeated wake failures or ΔT crossing.
H2-12. IC Selection Logic (PHY / Sensor / SoC Interface Choices)
- Bandwidth: resolution × FPS × bpp (+ overhead).
- Interconnect: board/FPC/connector and practical length class.
- Noise: EMI and power integrity risk level (normal / harsh).
- Thermal: temperature range and drift sensitivity (ΔT, sustained throughput).
- Wiring pressure: C-PHY can reduce wiring count pressure, but trio symmetry and coupling uniformity become hard gates.
- Bring-up risk: choose the PHY mode that provides clearer observability (lane/trio split counters and stable HS/LP transitions).
- Margin definition: “eye looks OK” is not a pass; the pass is windowed error-free operation under temp + load + noise gates.
- Lane/trio count support (2/4/8…)
- Target rate + headroom gate (placeholder %)
- Stable HS/LP transitions at the chosen mode set
- Supports periodic and event-trigger calibration strategy (ΔT / supply excursion / retrain)
- Lane-to-lane deskew observability
- Bring-up modes: per-lane enable and downshift validation
- CRC/ECC error counters + sync/SoT error flags
- Frame-drop counters with time-window logging (X seconds)
- Split by lane/trio (to identify asymmetry-driven failures)
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H2-13. FAQs (field troubleshooting + acceptance gates)
LP works, HS fails to enter intermittently — first check HS-settle margin or lane skew?
Likely cause: HS-settle/sampling margin is too tight during entry, often amplified by lane-to-lane skew or unstable entry sequencing.
Quick check: Log entry failures per 60 s window; check SoT/sync-related errors; downshift lane rate or enable lanes progressively to see if failures track margin/skew.
Fix: Adjust receiver timing (HS-settle window) within supported range; reduce skew via routing symmetry; ensure clock/reset/power-up sequence reaches stable state before HS entry.
Pass criteria: HS entry failures = 0 over Y minutes and N link-up cycles at target mode; SoT/sync errors ≤ X per Y minutes.
Works at low FPS, fails at high FPS — lane rate headroom or burst/FIFO underrun?
Likely cause: Lane-rate headroom is insufficient at peak throughput, or burst behavior causes Rx FIFO underrun/overrun despite acceptable average bandwidth.
Quick check: Compare payload budget vs configured lane rate; check FIFO underrun/overrun counters (or DMA starvation indicators); reduce FPS/bpp temporarily and see if failures disappear.
Fix: Add headroom (more lanes / higher rate within limits); tighten burst handling (FIFO depth, watermark, DMA priority); validate with stress streaming at the target mode.
Pass criteria: Frame drops ≤ X over Y minutes at target FPS; FIFO underrun/overrun counters = 0 over N start/stop cycles.
Only one lane shows errors — asymmetry/return-path discontinuity or connector pin issue?
Likely cause: Lane-specific asymmetry (length/impedance/return path) or a mechanical/electrical issue on a specific connector pin/contact.
Quick check: Compare per-lane error counters; swap lane mapping if the platform supports it; inspect connector seating/contact; check for lane-local discontinuities (stubs, via transitions, reference breaks).
Fix: Restore symmetry (length-match and reference continuity); remove stubs/test pads that bias one lane; correct connector footprint/escape routing and ensure robust mechanical retention.
Pass criteria: Per-lane error delta ≤ X over Y minutes; CRC/ECC ≤ X per 10^9 bits over Y minutes; repeat across N reseats.
Passes at room temp but fails hot/cold — static deskew calibration or drift-related?
Likely cause: Deskew/timing margin shrinks with temperature/voltage drift; one-time calibration is not sufficient for the operating envelope.
Quick check: Run a temperature sweep and log errors by time window; compare lane/trio skew indicators before/after drift; check whether recalibration actually runs when conditions change.
Fix: Enable periodic or event-trigger calibration (ΔT / supply excursion / retrain); add margin by downshifting rate if needed; tighten power/thermal stability around the PHY.
Pass criteria: 0 link drops at Tmin/Tmax with ≥ Y minutes streaming per point; CRC/ECC ≤ X over each Y minutes; repeat for N temp cycles.
CRC/ECC errors spike when power load changes — supply noise coupling or clock jitter?
Likely cause: Supply/ground noise couples into sampling thresholds, or reference clock quality/jitter worsens under load transients.
Quick check: Correlate error bursts with load-step timing and rail ripple (capture window); check PLL/clock health indicators if available; repeat with controlled load patterns.
Fix: Improve PHY rail isolation (separate LDO/filters), strengthen decoupling close to PHY pins, reduce ground bounce via return-path continuity; protect the ref clock routing and grounding.
Pass criteria: During N load steps, CRC/ECC ≤ X per 10^9 bits; SoT/sync errors = 0 over Y minutes at target streaming mode.
Random frame drops with “clean-looking” waveforms — first sanity check: counter window/denominator?
Likely cause: Measurement definition mismatch (window/denominator) or pipeline starvation (FIFO/DMA scheduling) masquerading as a link problem.
Quick check: Standardize the counter window (e.g., per 60 s); cross-check sensor-side vs host-side drop definitions; look for underrun/overrun or watermark events around drops.
Fix: Align metrics and logging (same window/timebase); add per-window counters for CRC/ECC/SoT/frame-drop; tune FIFO/DMA thresholds and priorities to eliminate starvation.
Pass criteria: Drop rate ≤ X per Y minutes over N runs; measurement consistency within ±X% across sensor/host logs.
C-PHY link unstable after layout change — trio symmetry or coupling imbalance?
Likely cause: Trio geometry drifted (length/spacing/return path), creating coupling imbalance and reducing symbol margin.
Quick check: Compare per-trio/per-lane error counters; audit trio symmetry (length/spacing/plane continuity); test at reduced symbol rate to confirm margin sensitivity.
Fix: Restore trio symmetry and reference continuity; eliminate trio-specific stubs and asymmetrical via structures; refresh calibration strategy if drift is involved.
Pass criteria: Link stable for Y minutes at target rate; per-trio error counters ≤ X per Y minutes; repeat across N temperature points.
HS is stable, but exit/LP transitions glitch — sequence/timing or pull-up/pull-down integrity?
Likely cause: Exit timing/sequence is marginal, or LP biasing (pull-up/pull-down) is not clean, causing incorrect LP state detection.
Quick check: Count transition-related errors per cycle; verify LP state stability (LP-11/LP-xx detection) after exit; check reset/power sequencing around state changes.
Fix: Adjust exit timing within supported parameters; clean up LP bias network and contention sources; enforce deterministic sequencing (clock stable → power stable → state transition).
Pass criteria: 0 LP/exit glitches over N HS↔LP cycles; LP state valid within X ms after exit; no frame drops over Y minutes.
After ESD test, link becomes “more fragile” — degradation check: impedance/connector damage or marginal settle?
Likely cause: Post-stress margin shrank due to interconnect degradation (connector/contact/impedance shift) or a previously marginal settle/skew setting becoming insufficient.
Quick check: Compare pre/post error rate under the same test window; inspect connector/FFC mechanically; downshift rate to confirm margin sensitivity; look for lane-biased errors.
Fix: Replace suspect interconnect; restore entry/settle margin (timing/deskew); if repeated stress is expected, route to the Port Protection page for system-level hardening decisions.
Pass criteria: Post-stress CRC/ECC ≤ X per 10^9 bits over Y minutes; 0 link drops over N start/stop cycles; no increasing error trend across N repeats.
One sensor model works, another fails on the same board — timing mismatch or calibration capability?
Likely cause: Receiver timing expectations do not match the new sensor’s output timing, or the sensor/receiver pairing lacks sufficient calibration/observability at the target mode.
Quick check: Compare configured lane count/rate and timing parameters; validate sensor registers for the intended mode; check whether errors cluster at entry, burst peaks, or temperature drift.
Fix: Align timing configuration on both ends (mode, settle/deskew strategy); enable the same observability counters and windowed logs; select components that support the required calibration triggers.
Pass criteria: Both sensors meet identical gate: 0 link failures over Y minutes; CRC/ECC ≤ X over Y minutes; repeat across N power cycles.
Errors only when cable/FFC is touched — shielding/ground reference or mechanical intermittency?
Likely cause: Mechanical intermittency at the connector/FFC, or a weak ground/reference path that becomes unstable when the cable is moved.
Quick check: Perform a controlled flex test while logging per-window counters; check continuity of ground/shield contacts; verify latch/retention and contact integrity.
Fix: Add strain relief and improve retention; ensure robust ground contacts and reference continuity; remove mechanical leverage points that introduce micro-movement at the connector.
Pass criteria: During N flex events, error increments ≤ X; 0 link drops over Y minutes streaming; repeat after N reseats.
Bench OK, enclosure assembled fails — first check: return path via chassis grounding change?
Likely cause: Assembly changes the return path and common-mode environment (chassis bonding, ground reference, coupling), shrinking the link margin.
Quick check: Compare error rates with/without chassis bonding; measure common-mode noise near the interface; try a temporary bonding strap to validate sensitivity.
Fix: Define a consistent chassis/ground strategy; ensure reference continuity and controlled return path; validate with assembled-system stress tests (temp + load-step).
Pass criteria: Assembled unit: CRC/ECC ≤ X over Y minutes at target mode; 0 link drops over N assembly cycles; sample N units with consistent results.
