Build a system-level mental model in 30 seconds: who transmits, who receives, what data moves, and why the PHY is a transport layer—not the semantic owner of pixels.

MIPI DSI / DSI-2 is a display interface that packetizes pixel streams (video) and control commands (DCS), and transports them over D-PHY or C-PHY to a panel or a bridge receiver. The protocol defines what is sent and when; the PHY defines how the bits move on wires.

• Payload model: video pixels (long packets) + control/metadata (short packets, DCS).
• Operating modes: video-mode streaming vs command-mode with scheduling/TE interactions.
• Transport options: D-PHY (HS/LP) or C-PHY (symbol/gear style transport).
• System-level “must-align”: lane configuration, pixel format, timing model, and error-check policy.
• Debug visibility: link/PHY state, error counters, clock lock status, and frame pacing observability.

Explain how a pixel stream becomes link packets, so later chapters can close the loop on bandwidth math and sync control without guesswork.

• Video mode: stream pixels continuously with explicit frame/line timing; simplest for steady refresh.
• Command mode: schedule updates using command transfers; enables selective/partial updates and tighter power control, but depends on pacing and TE behavior.
• Engineering implication: mode choice changes how “frame boundary correctness” is enforced and how latency/pacing failures manifest.

• Long packets: carry bulk payload (typically pixel data). Key property: word count must match what Rx expects for reconstruction.
• Short packets: carry lightweight events (sync markers or short commands). Key property: they shape boundaries and control flow.
• DCS command channel: control-plane traffic for panel configuration and updates. It is not the pixel payload itself, but it can enable/disable the pixel path.
• Error checks (concept level): ECC/CRC improve detectability of corruption, but do not replace correct timing/format alignment.

Rx reconstruction depends on three anchor fields: Data Type (DT) to interpret payload meaning, Virtual Channel (VC) to route streams, and Word Count (WC) to size payload correctly. When any one of these is mismatched, the link can look “active” while the displayed image is wrong.

• Black screen with “link active”: verify DT/format and timing parameters before blaming SI.
• Wrong colors: validate pixel format mapping and packing assumptions end-to-end.
• Tearing: confirm frame pacing strategy and boundary markers, especially in command mode.
• Intermittent artifacts: check whether WC/line sizing is stable across dynamic mode switches.

Detailed HS/LP timing and training behavior is handled in later chapters; this section stays at the “pixel → packet → lane” abstraction boundary.

Make HS entry and HS exit predictable. Many black-screen and flicker issues originate from state-machine windows rather than “raw signal quality”.

• D-PHY: LP for control/handshake and HS for payload bursts; typically a clock lane plus data lanes at the transport boundary.
• C-PHY: symbol/gear framing at the transport boundary; triad/lane mapping must match end-to-end.
• Practical implication: stable video requires both sides to agree on mode, lane/triad mapping, and transition windows.

Treat mode transitions as a state machine with timing windows: a receiver-ready window, a stable-capture window, and an exit window. When any window is violated, the link may appear “partially alive” but produce black frames, flicker, or recovery loops.

• ULPS entry: do not assume “idle equals safe”; ULPS is a controlled state with explicit preconditions.
• Resume risk: recovery often fails due to missing guard time between power/clock readiness and HS entry.
• Recovery principle: prove the state machine completes LP→HS entry and HS→LP exit deterministically before tuning SI or bandwidth.

• Clock readiness: PLL lock / reference stable before HS entry.
• Transition state: HS entry/exit completion without retries.
• Lane status: lane stop/ready state is coherent across lanes/triads.
• Recovery count: unexpected re-entry or retrain attempts are treated as a failure indicator.

Determine the minimum lane count and lane rate with a margin policy. Avoid “it works at 60 fps but fails at 90/120” due to missing blanking or overhead.

• Resolution: active pixels (W × H).
• Frame rate: FPS (including dynamic targets if used).
• Color depth: bits-per-pixel (BPP) or pixel format mapping.
• Blanking model: line/frame blanking or equivalent timing overhead.
• Compression (if any): effective throughput multiplier and its corner-case behavior.

• Protocol overhead: headers + ECC/CRC and any required markers.
• Blanking overhead: time not carrying active pixels but still consuming link budget.
• LP/Escape overhead: transition/low-power time that reduces effective HS payload time.
• Margin overhead: explicit engineering margin to cover PVT, jitter, and layout sensitivity.

Treat overhead as a controllable budget. A “barely meets math” design often fails in temperature corners and resume scenarios.

• Required payload throughput: pixels × FPS × BPP (active payload).
• Required link throughput: payload scaled by overhead proportions (protocol + blanking + LP/escape).
• Required lane rate: link throughput ÷ (lane count) with a margin policy.
• Margin policy: reserve X% headroom (placeholder) to cover worst-case corners.

• Only active pixels counted: stable at low FPS, fails at higher FPS due to missing blanking/time overhead.
• Blanking ignored: “math looks fine” but real timing model pushes occupancy too high.
• BPP/format changed without re-budgeting: color upgrade quietly consumes lane-rate margin.
• Dual display not additive-budgeted: single display passes; dual output flickers or drops under peak.

Turn tearing, jitter, and occasional wrong frames into a timing-consistency problem: stable frame boundaries, predictable pacing, and coherent line reconstruction.

• Frame boundary: the exact start/end of a frame as understood by both Tx and Rx timing engines.
• Line boundary: the start/end of each line used to map payload into raster order.
• Active vs blanking: blanking is not “free time”; it consumes budget and affects pacing.
• TE (optional): a pacing/synchronization cue (commonly in command-mode flows), not the video payload.

If boundaries are not coherent, symptoms may look like random tearing or occasional frame jumps even when the link remains up.

Pacing is a system contract: when cadence changes, both boundary timing and buffering must remain consistent or the display may tear or “hiccup”.

• Boundary cues: Rx timing logic uses sync boundaries and payload mapping to re-create raster order.
• Coherency requirement: Tx timing model and Rx reconstruction must agree on line/frame boundaries.
• Command-mode sensitivity: updates may be gated by TE/pacing cues; missing or unstable cues can create partial updates and tearing.

• Buffer depth trade: deeper buffers smooth jitter but increase latency and hide boundary mistakes until overflow/underflow events.
• Queue alignment: pacing changes must be aligned with safe windows to avoid mid-frame updates.
• Practical rule: verify frame boundaries and pacing stability before changing bandwidth or PHY parameters.

• Tearing / partial updates: check boundary coherence and pacing/TE gating behavior; require stable frame boundary over X frames (placeholder).
• Occasional wrong line / frame jump: validate VS/HS/blanking parameters match end-to-end and remain constant during a frame.
• TE missing / TE jitter: treat as a synchronization signal quality issue; require TE stability within X (placeholder).

Explain “looks OK on a scope but still unstable” as a jitter-tolerance and injection-path problem across multiple clock domains.

• PLL/ref reference: the stability anchor; ref noise can amplify through PLL dynamics.
• Pixel clock: controls pixel production cadence (display pipeline timing).
• Byte/HS clock: controls transport cadence (PHY/lane timing).
• Key risk: if domain relationships drift near tolerance edges, the result is often intermittent flicker instead of a permanent link-down.

Periodic or load-correlated instability is a strong hint of injection, not just average “eye quality”.

• Lock is not binary: near the edge, small disturbances can inflate phase noise and jitter.
• Field signature: OK at cold start, worse after warm-up; worse at peak load; sensitive to supply ripple.
• Bring-up rule: confirm robust lock margin before pushing lane rate or enabling aggressive pacing changes.

• SSC changes instantaneous frequency: EMI improves, but Rx tracking tolerance must keep up.
• Coordination point: treat SSC enable/disable as a timing-mode change requiring safe windows.
• Pass criteria: no flicker/tearing while SSC is toggled within X cycles (placeholder).

• Switching is a sequence: adjust clocks, verify lock/settle, then re-enter stable transport and pacing.
• Common signature: single flash at the moment of switching; intermittent drop only at one FPS gear.
• Guard policy: enforce a settle window tX (placeholder) before sending critical frame boundaries.

Provide DSI-specific SI/layout rules centered on FPC/connector transitions and ESD symmetry—avoid generic SerDes/USB/PCIe guidance.

• Zdiff consistency: keep the lane bundle consistent across SoC → connector → FPC → panel/bridge transitions.
• Intra-pair skew: control within each differential pair to protect eye symmetry.
• Inter-pair skew: keep lanes aligned so one lane does not become the systematic worst case.
• Segment continuity: minimize sudden width/spacing changes and uncontrolled stubs around the connector region.

Intermittent flicker that worsens with touch/pressure often points to transition and symmetry issues, not peak bandwidth.

• Reference plane: keep the differential bundle tightly referenced to a continuous plane.
• Plane splits: avoid crossing gaps; a split is a return-path break that excites common-mode.
• Via transitions: treat layer changes as return-path rebuild events—add stitching GND vias near transitions.
• Connector region: make return paths short and obvious; do not “force detours” around keepouts.

• Pin ground strategy: GND distribution around lanes defines how “tight” the return path stays through the connector.
• Density & reference: dense routing without stable reference increases bundle imbalance sensitivity.
• Shield bond concept: prefer a return-path-first mindset; avoid creating long, inductive return detours.

• Ultra-low C is necessary: but ΔC asymmetry is often the real killer.
• Mode conversion: imbalance turns differential energy into common-mode, reducing margin and increasing sensitivity.
• Placement rule: close to entry, keep stubs short, and preserve left/right symmetry around each pair.

• Symmetry check: lane-side parasitics balanced within X (placeholder).
• Return continuity: no plane split crossings; stitching near transitions passes a visual audit.
• Assembly sensitivity: touch/bend A/B test shows error/flicker delta ≤ X (placeholder).

• Pressing near connector changes flicker: prioritize connector return-path and GND pin strategy.
• Swapping ESD worsens stability: suspect ΔC imbalance and stub symmetry before blaming lane rate.
• Temperature/load sensitivity: treat as common-mode/return-path stress first, then revisit clock injection (H2-6).

Systematize “works once but fails after reboot/resume” as an incomplete state-machine loop with guard times and observable pass criteria.

• Power-off → Rails up: rails reach stable conditions before releasing reset.
• Reset hold → Reset release: exit from a known state, then wait a guard window tX.
• LP ready → Init envelope: send initialization in a controlled envelope (avoid panel-specific tables here).
• Video on → Sleep/ULPS → Resume: transitions require safe windows to avoid mid-frame discontinuities.
• Recovery: a minimal closed loop that is re-entrant and observable.

• Stability gate: require rails stable for tX before reset release.
• Domain separation: treat “display content path” and “backlight/power domain” as separate controls.
• Repeatability: sequence must work cold boot, warm reboot, and resume with the same gates.

• Reset hold: enforce a known baseline and prevent partial init from prior cycles.
• Guard after release: allow internal readiness before sending init envelope (tX placeholder).
• Field signature: cold boot OK, warm reboot fails → suspect missing reset gate or insufficient guard time.

• Role: establish mode/format/timing assumptions and prepare the sink to accept video.
• Re-entrant design: initialization must be repeatable after any recovery path.
• Do not hardcode: avoid embedding panel-specific command tables in a generic design doc.

• Enter: stop video cleanly, complete boundary, then transition to sleep/ULPS.
• Exit: restore rails/clock readiness → wait tX → re-init envelope → video on.
• Common failure: resume black screen despite link up → order is correct but windows are insufficient.

1. Reset PHY / link state: return transport to a known baseline.
2. Re-enter stable transport: ensure HS/LP state is coherent before proceeding.
3. Re-send init envelope: re-apply the minimal initialization needed for the sink.
4. Validate: confirm the sink is responsive and frame boundaries are stable.

• Rails stable: within X (placeholder) before reset release.
• Reset guard: reset release to init start ≥ tX (placeholder).
• Init completion: init envelope completes within X ms (placeholder).
• Video stability: stable frames over X frames (placeholder).
• Resume robustness: no recovery loop within X cycles (placeholder).

Convert symptoms into a repeatable, layer-based workflow: symptom → first measurement → layer classification → next action.

• Protocol config: mode/format/lanes/timing fields alignment between Tx and Rx.
• PHY state & timing: HS/LP coherence, lane enable/stop state, ULPS transitions.
• Clock & PLL: lock status, safe switching windows, noise-coupled instability.
• SI/layout: connector/FPC/ESD symmetry and return-path discontinuities.
• Power noise & sequencing: rail stability, ripple correlation, brownout-like resets.

Recommended logging format: timestamp + state snapshot + counter deltas + active mode (FPS/format/lanes).

• State first: confirm state coherence before interpreting counters.
• Freeze mode: fix FPS/format/lanes before testing dynamic switches.
• Correlation before redesign: run minimal A/B tests (rail, temperature, pressing) to classify the layer.

1. Baseline: fixed mode burn-in for X minutes (placeholder).
2. Switching: controlled sequence of FPS/format/resolution changes (fixed order).
3. Corners: temperature/voltage corners and mechanical A/B (FPC bend/press) trials.
4. Log: time-stamped state snapshots + counter deltas + re-train/re-init counts.

• Stable operation ≥ X min (placeholder).
• Error counter increment ≤ X per minute (placeholder).
• Re-train / re-init count ≤ X (placeholder).
• No visible flicker/artifacts across switch sequence (with recorded correlation notes).

Define what “pass” means via measurable stability and a stress matrix—without relying on vendor-specific CTS details.

• Transport stability: link/state coherence with no bouncing and no unexpected retrain.
• Data integrity: error counters stable (ECC/CRC or platform equivalents).
• Timing robustness: frame boundary stability under mode and refresh changes.
• Stress survivability: corners and mechanical sensitivity do not trigger intermittent failure.

• Purpose: isolate PHY/SI margin from protocol and application timing variables.
• Interpretation: loopback/PRBS fails → prioritize PHY/SI/power; passes → re-focus on config/timing.
• Fallback: if PRBS is not exposed, use fixed-pattern video + state/counter stability as the transport proxy.

• Temp corner: cold/hot sweep (placeholder range) while monitoring stability metrics.
• Voltage corner: rail variation/ripple scenarios (placeholder) to expose noise sensitivity.
• Mode switching: FPS/resolution/color-depth changes in a fixed sequence, repeated for X cycles.
• Mechanical A/B: controlled FPC bend/press near connector to screen assembly-induced intermittents.

• Connector/FPC fit: quick mechanical sensitivity trial to catch borderline contact/return-path issues.
• ESD symmetry risk: screen for assembly-induced asymmetry (ΔC-like effects) using repeatable A/B patterns.
• Short stress script: prefer short, high-coverage switch/corner scripts over long, single-mode runs.

• Baseline stable time ≥ X min (placeholder).
• Error increment ≤ X per minute (placeholder).
• Re-train count ≤ X (placeholder).
• Mode-switch success ≥ X% (placeholder).
• Mechanical A/B delta ≤ X (placeholder).