Topologies (low-/high-side, half/full-bridge, multiphase VR, gate transformer), switch-specific drivers (IGBT/SiC/GaN/LV MOSFET), isolation & integration, protection & control, interfaces & timing, application playbooks, key specs, and design hooks.
Topologies
Low-Side Gate Driver
High peak source/sink, split Rg,on/off, UVLO—great for SR and low-side switches.
High-Side Gate Driver (Bootstrap/Charge Pump)
Bootstrap/charge-pump bias, UVLO and shoot-through prevention for HB/3-phase.
Half-Bridge / Full-Bridge Driver
Cross-conduction interlock with programmable deadtime & matched delay for FOC/LLC/inverters.
Multiphase Gate Driver for VR
Interleaving & share signals for CPU/GPU VR with thermal spreading.
Gate-Transformer Driver
Push-pull primary with synchronous secondary—very high isolation for pulsed/RF supplies.
By Switch Technology
IGBT Gate Driver
−VGOFF, DESAT fast SC detect, soft/two-level turn-off—traction/industrial.
SiC MOSFET Driver
High CMTI (100–200 kV/µs), Miller clamp, +18/−3…−5 V options, & <2 µs SC protection.
GaN HEMT Driver
Ultra-fast edges, minimal loop inductance, precise 0–6 V gate control & shoot-through guard.
Low-Voltage MOSFET Driver
5–12 V VG with ≥2–10 A peaks for synchronous bucks and BLDC stages.
Isolation & Integration
Isolated Gate Driver
Reinforced isolation, high CMTI and independent HS/LS channels—ideal for SiC/GaN inverters.
Driver with Integrated Isolated Bias
Built-in secondary bias with UVLO/OTP/fault—simplifies high-side supplies.
Digital Isolator + Gate Driver Combo
One-package isolator+driver for tighter timing/skew in multiphase/multibridge systems.
Driver w/ Current/Temp Sensing
Shunt/DESAT telemetry & thermal foldback—faster protection loops.
Protection & Control
UVLO (On/Off Thresholds)
Independent ON/OFF thresholds to prevent half-conduction loss.
DESAT Short-Circuit Detection
Programmable blanking/filter, soft turn-off current source, latch/auto-retry.
Active Miller Clamp
Clamps gate during turn-off to suppress dv/dt induced false turn-on.
Split/Programmable Gate Resistors
Separate Rg,on/off or programmable slew to balance EMI vs losses.
Deadtime & Shoot-Through Interlock
Fixed/programmable deadtime with hardware interlocks.
Two-Level Turn-On/Off
Fast primary + gentle secondary edges to limit dI/dt and ringing.
Fault Reporting & Disable
/FLT, /RDY, and safe fault paths across isolation.
Synchronous Rectifier Driver
Bootstrap’d SR with reverse-conduction criteria and gm protection for flyback/LLC secondary.
Interfaces & Timing
Differential / Single-Ended Inputs
Noise-robust inputs; wire directly from digital isolators.
Propagation Delay & Matching
Low jitter with inter-channel skew of only a few ns—vital for 3-phase/VR.
CMTI / dv/dt Immunity
50–200 kV/µs robustness for SiC/GaN high-frequency hard-switching.
Gate Voltage & Drive Current
2–20 A peak source/sink; optional −VG rails—dimension by Qg & switching freq.
Application-Focused
3-Phase Motor / Servo
HB/3-phase stacks, OC/OT linkage and Hall/encoder synchronization.
PFC + HB/FB/LLC
Main-bridge drivers + SR drivers; tuned for ZVS/ZCS stages.
Automotive Traction Inverter
ASIL hooks, redundant turn-off, cold-crank and load-dump strategies.
PV/ESS Inverters & DC-DC
Multi-string/paralleled stages with isolated drivers and synchronized iso-ΣΔ sampling.
POL/VR/Modular Power
Multiphase drivers, remote sense and PMBus coordination.
Key Specs & Selection
Peak Source/Sink Current
Sets gate charge speed—size from Qg and target tr/tf.
UVLO Thresholds
Match device-recommended VG to avoid half-conduction loss.
Delay/Skew/Jitter
Channel matching defines PWM resolution and control bandwidth.
CMTI & dv/dt
Common-mode transient immunity—top metric for SiC/GaN hard-switch.
Gate Voltage Range (+/−)
Supported +/− VG ranges and programmability.
Protection Response Time
DESAT detect, soft-turn-off delay and safe deactivation times.
Temp/Package/Creepage
Wide-temp reliability, thermal path and safety spacings.
Design Hooks & Pitfalls
Gate Loop & Parasitics
Minimize loop area, use Kelvin-source; split Rg/series ferrite to tame ringing.
Negative VGOFF & Miller
Use −2…−5 V for SiC/GaN with active clamp and two-level turn-off.
Bootstrap Sizing
Cboot ≥ (Qg,total + losses)/ΔV; watch diode recovery & dv/dt.
Isolated Bias Noise
De-couple from ADC sampling; align switching to avoid sample windows.
Layout & Grounding
Partition power/control; no return across splits; stagger driver vs power layers.
SOA & Short-Circuit Energy
Set DESAT thresholds/blanking, soft-turn-off current and external clamps.
Thermal & Mismatch
Maintain arm-to-arm symmetry; add thermal coupling and drift compensation.
Production Test & Safety
Verify interlocks, inject faults, and prep EMC/safety documentation.
